Techniques For Programming Circuits Using Mode Decoding

1. An integrated circuit comprising: programmable circuits; a configuration status register circuit that stores configuration bits and that is coupled to provide the configuration bits to the programmable circuits to program the programmable circuits to implement functions of a first mode; a mode register circuit coupled to store mode bits; a mode decoder circuit that decodes at least a subset of the mode bits received from the mode register circuit to generate decoded bits; and a first multiplexer circuit that provides the decoded bits from the mode decoder circuit to the programmable circuits to reprogram the programmable circuits to implement functions of a second mode in response to at least one of the mode bits.

2. The integrated circuit of claim 1 further comprising: an address register circuit coupled to store address bits; an address decoder circuit coupled to receive the address bits from the address register circuit and to decode the address bits to generate a decoded address bit; and a second multiplexer circuit that provides the configuration bits to the configuration status register circuit in response to the decoded address bit from either a first input of the second multiplexer circuit or from a second input of the second multiplexer circuit that is coupled to an output of the configuration status register circuit.

3. The integrated circuit of claim 1 further comprising: a write data register circuit coupled to store the configuration bits, wherein the configuration bits are provided from an output of the write data register circuit to the configuration status register circuit to program the programmable circuits to implement the functions of the first mode.

4. The integrated circuit of claim 3 further comprising: a second multiplexer circuit comprising an output that is coupled to an input of the configuration status register circuit, wherein the first multiplexer circuit is coupled to an output of the write data register circuit, the mode decoder circuit, and a first input of the second multiplexer circuit, wherein the second multiplexer circuit further comprises a second input that is coupled to an output of the configuration status register circuit.

5. The integrated circuit of claim 3 further comprising: a second multiplexer circuit comprising a first input that is coupled to an output of the write data register circuit and an output that is coupled to an input of the configuration status register circuit, wherein a first input of the first multiplexer circuit is coupled to an output of the configuration status register circuit, and wherein a second input of the first multiplexer circuit is coupled to the mode decoder circuit.

6. The integrated circuit of claim 1 , wherein the programmable circuits, the configuration status register circuit, the mode decoder circuit, and the first multiplexer circuit are all in a first configurable circuit block.

7. The integrated circuit of claim 6 further comprising: a second configurable circuit block that comprises additional programmable circuits, an additional mode decoder circuit, a second multiplexer circuit, and an additional configuration status register circuit, wherein the mode register circuit is a global mode register circuit that is coupled to provide at least a subset of the modes bits to the mode decoder circuit and to the additional mode decoder circuit.

8. The integrated circuit of claim 7 , wherein an input of the second multiplexer circuit is coupled to an output of the additional configuration status register circuit, wherein the additional mode decoder circuit generates additional decoded bits based on the mode bits, and wherein the second multiplexer circuit is coupled to provide the additional decoded bits to reprogram the additional programmable circuits to implement functions of the second mode.

9. The integrated circuit of claim 6 , wherein the mode register circuit is in the first configurable circuit block.

10. The integrated circuit of claim 1 , wherein the integrated circuit is a programmable logic integrated circuit, and wherein the programmable circuits are programmable logic circuits.

11. The integrated circuit of claim 1 further comprising: an additional configuration status register circuit that stores additional configuration bits and that is coupled to provide the additional configuration bits to the programmable circuits to program the programmable circuits to implement the functions of the first mode, wherein the mode decoder circuit decodes the subset of the mode bits to generate additional decoded bits; and a second multiplexer circuit that provides the additional decoded bits from the mode decoder circuit to the programmable circuits to reprogram the programmable circuits to implement the functions of the second mode in response to the at least one of the mode bits.

12. A method for changing a mode of a configurable circuit block, the method comprising: storing configuration bits in a configuration status register circuit; configuring the configurable circuit block to implement functions of a first mode using the configuration bits provided from the configuration status register circuit; storing mode bits in a mode register circuit; decoding at least a subset of the mode bits received from the mode register circuit to generate decoded bits using a mode decoder circuit; providing the decoded bits from the mode decoder circuit through a first multiplexer circuit to the configurable circuit block instead of the configuration bits in response to at least one of the mode bits; and reconfiguring the configurable circuit block to implement functions of a second mode using the decoded bits.

13. The method of claim 12 further comprising: providing the configuration bits to the configuration status register circuit from either an output of a write data register circuit or from an output of the configuration status register circuit through a second multiplexer circuit in response to a decoded address bit.

14. The method of claim 13 further comprising: storing address bits in an address register circuit; and decoding the address bits received from the address register circuit using an address decoder circuit to generate the decoded address bit.

15. The method of claim 12 further comprising: storing additional configuration bits in an additional configuration status register circuit; configuring an additional configurable circuit block to implement the functions of the first mode using the additional configuration bits provided from the additional configuration status register circuit; decoding the subset of the mode bits received from the mode register circuit to generate additional decoded bits using an additional mode decoder circuit; providing the additional decoded bits from the additional mode decoder circuit through a second multiplexer circuit to the additional configurable circuit block instead of the additional configuration bits in response to the at least one of the mode bits; and reconfiguring the additional configurable circuit block to implement the functions of the second mode using the additional decoded bits.

16. The method of claim 12 , wherein providing the decoded bits from the mode decoder circuit through the first multiplexer circuit to the configurable circuit block instead of the configuration bits in response to at least one of the mode bits further comprises providing the decoded bits through the first multiplexer circuit to the configuration status register circuit.

17. A computer readable non-transitory medium storing executable instructions for changing a mode of a configurable circuit block, the executable instructions comprising: instructions executable to store configuration bits in a configuration status register circuit; instructions executable to configure the configurable circuit block to implement functions of a first mode using the configuration bits provided from the configuration status register circuit; instructions executable to store mode bits in a mode register circuit; instructions executable to decode at least a subset of the mode bits received from the mode register circuit to generate decoded bits using a mode decoder circuit; instructions executable to provide the decoded bits from the mode decoder circuit through a first multiplexer circuit to the configurable circuit block instead of the configuration bits in response to at least one of the mode bits; and instructions executable to reconfigure the configurable circuit block to implement functions of a second mode using the decoded bits.

18. The computer readable non-transitory medium of claim 17 further comprising: instructions executable to provide the configuration bits to the configuration status register circuit from either an output of a write data register circuit or from an output of the configuration status register circuit in response to a decoded address bit using a second multiplexer circuit.

19. The computer readable non-transitory medium of claim 18 further comprising: instructions executable to store address bits in an address register circuit; and instructions executable to decode the address bits received from the address register circuit using an address decoder circuit to generate the decoded address bit.

20. The computer readable non-transitory medium of claim 17 further comprising: instructions executable to store additional configuration bits in an additional configuration status register circuit; instructions executable to configure an additional configurable circuit block to implement the functions of the first mode using the additional configuration bits provided from the additional configuration status register circuit; instructions executable to decode the subset of the mode bits received from the mode register circuit to generate additional decoded bits using an additional mode decoder circuit; instructions executable to provide the additional decoded bits from the additional mode decoder circuit through a second multiplexer circuit to the additional configurable circuit block instead of the additional configuration bits in response to the at least one of the mode bits; and instructions executable to reconfigure the additional configurable circuit block to implement the functions of the second mode using the additional decoded bits.

21. The computer readable non-transitory medium of claim 17 , wherein the instructions executable to provide the decoded bits from the mode decoder circuit through the first multiplexer circuit to the configurable circuit block further comprises instructions executable to provide the decoded bits through the first multiplexer circuit to the configuration status register circuit.