Semiconductor Devices and Semiconductor Systems

1. A semiconductor system comprising: a first semiconductor device configured for outputting a reset signal, command and address (command/address) signals and data; and a second semiconductor device configured to generate internal commands, internal addresses and internal data for performing an initialization operation according to a start signal generated based on the reset signal and configured to store the internal data in a plurality of memory cells selected by the internal commands and the internal addresses during the initialization operation, and wherein the start signal is enabled from a point of time that a level of the reset signal is changed till a point of time that all of bits of the internal addresses are counted.

2. The semiconductor system of claim 1 , wherein the internal data are stored in the plurality of memory cells to have the same logic level during the initialization operation.

3. The semiconductor system of claim 1 , wherein the second semiconductor device is configured to stop receiving the command/address signals and the data while the start signal is enabled.

4. The semiconductor system of claim 1 , wherein the second semiconductor device includes: a start signal generation circuit configured to generate an oscillation signal including pulses which are periodically created based on the reset signal and configured to generate the start signal which is enabled based on a point of time that a level transition of the reset signal occurs; an initialization operation control circuit configured to generate the internal addresses which are sequentially counted and the internal commands which are sequentially counted based on the pulses of the oscillation signal while the start signal is enabled and configured to generate the internal data having a predetermined logic level based on the pulses of the oscillation signal while the start signal is enabled; and a memory area configured to include the plurality of memory cells and configured to store the internal data into the plurality of memory cells selected by the internal addresses based on the internal commands.

5. The semiconductor system of claim 4 , wherein the start signal generation circuit includes: an oscillator configured to generate the oscillation signal including the pulses which are periodically created based on the reset signal; and a start signal driving circuit configured to generate the start signal which is enabled based on the oscillation signal and which is disabled if all of bits of the internal addresses are counted.

6. The semiconductor system of claim 5 , wherein the start signal driving circuit includes: a pulse signal generation circuit configured to generate a pulse signal including a pulse which is created based on the pulses of the oscillation signal being inputted by a predetermined number of times; a start signal output circuit configured to generate the start signal which is enabled based on the pulse of the pulse signal and which is disabled based on a detection signal; and an address sensing circuit configured to generate the detection signal which is enabled if all of bits of the internal addresses are counted.

7. The semiconductor system of claim 5 , wherein the start signal driving circuit includes: a pulse signal generation circuit configured to a pulse signal including a pulse which is created based on the pulses of the oscillation signal or a mode set signal; a start signal output circuit configured to generate the start signal which is enabled based on the pulse of the pulse signal and which is disabled based on a detection signal; and an address sensing circuit configured to generate the detection signal which is enabled if all of bits of the internal addresses are counted.

8. The semiconductor system of claim 7 , wherein the pulse signal generation circuit includes: a boot-up signal generation circuit configured to generate a boot-up signal including a pulse which is created based on the pulses of the oscillation signal being inputted by a predetermined number of times; a test mode signal generation circuit configured to generate a test mode signal including a pulse which is created based on the mode set signal; and a logic circuit configured to execute a logical OR operation of the boot-up signal and the test mode signal to generate the pulse signal.

9. The semiconductor system of claim 4 , wherein the initialization operation control circuit includes: an internal signal generation circuit configured to generate addresses and commands that are sequentially counted and storage data having a predetermined logic level, based on the pulses of the oscillation signal while the start signal is enabled; and an input control circuit configured to output the addresses or some bits of the command/address signals as the internal addresses, configured to output the commands or some other bits of the command/address signals as the internal commands, and configured to output the storage data or the data as the internal data, based on the start signal.

10. The semiconductor system of claim 9 , wherein the internal signal generation circuit includes: an address generation circuit configured to generate the addresses that are sequentially counted based on the pulses of the oscillation signal while the start signal is enabled; a command generation circuit configured to generate the commands based on the pulses of the oscillation signal while the start signal is enabled; and a data generation circuit configured to generate the storage data having a predetermined logic level based on the pulses of the oscillation signal while the start signal is enabled.

11. The semiconductor system of claim 10 , wherein the data generation circuit comprises: a buffer circuit configured to inversely buffer a ground voltage or a power supply voltage and to output an inversely buffered voltage based on the start signal; and a first latch configured to receive the output of the buffer circuit and inversely buffer and latch the output of the buffer circuit to generate the storage data.

12. The semiconductor system of claim 10 , wherein the data generation circuit comprises: a node; a first driving circuit coupled to the node and configured to pull up the node to a power supply voltage based on the start signal; and a second latch circuit coupled to the node and configured to inversely buffer and latch a signal of the node to generate the storage data based on pulses of the oscillation signal.

13. The semiconductor system of claim 10 , wherein the data generation circuit comprises: a node; a second driving circuit coupled to the node and configured to pull down the node to a ground voltage based on the start signal; and a third latch circuit coupled to the node and configured to inversely buffer and latch a signal of the node to generate the storage data based on pulses of the oscillation signal.

14. The semiconductor system of claim 9 , wherein the input control circuit includes: a first transmission circuit configured to output the addresses or some bits of the command/address signals as the internal addresses based on the start signal; a second transmission circuit configured to output the commands or some other bits of the command/address signals as the internal commands based on the start signal; and a third transmission circuit configured to output the storage data or the data as the internal data based on the start signal.

15. A semiconductor device comprising: a start signal generation circuit configured to generate an oscillation signal including pulses which are periodically created based on a reset signal during an initialization operation and configured to generate a start signal which is enabled at a point of time that a level transition of the reset signal occurs; and an initialization operation control circuit configured to generate internal addresses and internal commands which are sequentially counted based on the pulses of the oscillation signal while the start signal is enabled and configured to generate internal data having a predetermined logic level based on the pulses of the oscillation signal while the start signal is enabled.

16. The semiconductor device of claim 15 , wherein the start signal is enabled from a point of time that a level of the reset signal is changed till a point of time that all of bits of the internal addresses are counted.

17. The semiconductor device of claim 15 , wherein the start signal generation circuit includes: an oscillator configured to generate the oscillation signal including the pulses which are periodically created based on the reset signal; and a start signal driving circuit configured to generate the start signal which is enabled based on the oscillation signal and which is disabled if all of bits of the internal addresses are counted.

18. The semiconductor device of claim 17 , wherein the start signal driving circuit includes: a pulse signal generation circuit configured to generate a pulse signal including a pulse which is created based on the pulses of the oscillation signal being inputted by a predetermined number of times; a start signal output circuit configured to generate the start signal which is enabled based on the pulse of the pulse signal and which is disabled based on a detection signal; and an address sensing circuit configured to generate the detection signal which is enabled if all of bits of the internal addresses are counted.

19. The semiconductor device of claim 15 , wherein the initialization operation control circuit includes: an internal signal generation circuit configured to generate addresses and commands that are sequentially counted and storage data having a predetermined logic level, based on the pulses of the oscillation signal while the start signal is enabled; and an input control circuit configured to output the addresses or some bits of command/address signals as the internal addresses, configured to output the commands or some other bits of the command/address signals as the internal commands, and configured to output the storage data or data as the internal data, based on the start signal.

20. The semiconductor device of claim 19 , wherein the internal signal generation circuit includes: an address generation circuit configured to generate the addresses that are sequentially counted based on the pulses of the oscillation signal while the start signal is enabled; a command generation circuit configured to generate the commands based on the pulses of the oscillation signal while the start signal is enabled; and a data generation circuit configured to generate the storage data having a predetermined logic level based on the pulses of the oscillation signal while the start signal is enabled.

21. The semiconductor device of claim 19 , wherein the input control circuit includes: a first transmission circuit configured to output the addresses or some bits of the command/address signals as the internal addresses based on the start signal; a second transmission circuit configured to output the commands or some other bits of the command/address signals as the internal commands based on the start signal; and a third transmission circuit configured to output the storage data or the data as the internal data based on the start signal.

22. The semiconductor device of claim 15 , a first memory area configured to include a plurality of first memory cells and configured to store the internal data into the plurality of first memory cells selected by the internal addresses based on the internal commands; and a second memory area configured to include a plurality of second memory cells and configured to store the internal data into the plurality of second memory cells selected by the internal addresses based on the internal commands.