Legal claims defining the scope of protection, as filed with the USPTO.
1. An anti-interference display panel, comprising: a source driving chip, for generating a data signal; a switching signal line, for transmitting a switching signal; a multiplexer, for receiving the data signal and the switching signal, and for outputting the data signal according to the switching signal; and an anti-interference signal line, for transmitting an anti-interference signal, wherein an equivalent resistor and an equivalent capacitor are formed on the anti-interference signal line, and resistance of the equivalent resistor is approximate to resistance of a load resistor coupled to the switching signal line, and capacitance of the equivalent capacitor is approximate to capacitance of a load capacitor coupled to the switching signal line; wherein the anti-interference signal falls when the switching signal rises, and the anti-interference signal rises when the switching signal falls.
2. The anti-interference display panel according to claim 1 , wherein the anti-interference signal line has a first area and a second area for forming the equivalent resistor on the anti-interference signal line.
3. The anti-interference display panel according to claim 2 , wherein the first area is wider than the second area.
4. The anti-interference display panel according to claim 1 , wherein the anti-interference signal line comprises an anti-interference unit, for enabling the equivalent capacitor to be formed on the anti-interference signal line, and the anti-interference unit comprises: a semiconductor layer, disposed on a surface of a substrate; a first insulation layer, bonded to the surface of the substrate and the semiconductor layer; a second insulation layer, bonded to the first insulation layer; a first conductive layer, partially bonded to the semiconductor layer; and a second conductive layer, located between the semiconductor layer and the first conductive layer, and for receiving the switching signal, wherein the first insulation layer and the second insulation layer cover the second conductive layer.
5. The anti-interference display panel according to claim 4 , wherein the semiconductor layer comprises: a first type doped area, bonded to the first conductive layer; and a second type doped area, located in a closed area formed by the first type doped area, the first insulation layer, and the surface of the substrate.
6. The anti-interference display panel according to claim 4 , wherein the semiconductor layer comprises: a first type doped area, bonded to the first conductive layer; a first type low doped area, bonded to the first type doped area; and a second type doped area, located in a closed area formed by the first type low doped area, the first insulation layer, and the surface of the substrate.
7. The anti-interference display panel according to claim 5 , wherein the second type doped area overlaps with at least one part of a projection of the second conductive layer on the substrate.
8. The anti-interference display panel according to claim 5 , wherein resistance of the second type doped area falls when the switching signal rises, and resistance of the second type doped area rises when the switching signal falls.
9. An anti-interference signal line, for transmitting an anti-interference signal to reduce a coupling effect caused by a switching signal on a switching signal line, comprising: an equivalent resistor, wherein resistance of the equivalent resistor is approximate to resistance of a load resistor coupled to the switching signal line; and an equivalent capacitor, wherein capacitance of the equivalent capacitor is approximate to capacitance of a load capacitor coupled to the switching signal line, wherein the anti-interference signal falls when the switching signal rises, and the anti-interference signal rises when the switching signal falls.
10. The anti-interference signal line according to claim 9 , wherein the anti-interference signal line has a first area and a second area for forming the equivalent resistor on the anti-interference signal line.
11. The anti-interference signal line according to claim 10 , wherein the first area is wider than the second area.
12. The anti-interference signal line according to claim 9 , wherein the anti-interference signal line comprises an anti-interference unit, for enabling the equivalent capacitor to be formed on the anti-interference signal line, and the anti-interference unit comprises: a semiconductor layer, disposed on a surface of a substrate; a first insulation layer, bonded to the surface of the substrate and the semiconductor layer; a second insulation layer, bonded to the first insulation layer, wherein the first insulation layer and the second insulation layer cover the switching signal line; a first conductive layer, partially bonded to the semiconductor layer; and a second conductive layer, located between the semiconductor layer and the first conductive layer, and for receiving the switching signal, wherein the first insulation layer and the second insulation layer cover the second conductive layer.
13. The anti-interference signal line according to claim 12 , wherein the semiconductor layer comprises: a first type doped area, bonded to the first conductive layer; and a second type doped area, located in a closed area formed by the first type doped area, the first insulation layer, and the surface of the substrate.
14. The anti-interference signal line according to claim 12 , wherein the semiconductor layer comprises: a first type doped area, bonded to the first conductive layer; a first type low doped area, bonded to the first type doped area; and a second type doped area, located in a closed area formed by the first type low doped area, the first insulation layer, and the surface of the substrate.
15. The anti-interference signal line according to claim 13 , wherein the second type doped area overlaps with at least one part of a projection of the second conductive layer on the substrate.
16. The anti-interference signal line according to claim 13 , wherein resistance of the second type doped area falls when the switching signal rises, and resistance of the second type doped area rises when the switching signal falls.
17. The anti-interference display panel according to claim 6 , wherein the second type doped area overlaps with at least one part of a projection of the second conductive layer on the substrate.
18. The anti-interference display panel according to claim 6 , wherein resistance of the second type doped area falls when the switching signal rises, and resistance of the second type doped area rises when the switching signal falls.
19. The anti-interference signal line according to claim 14 , wherein the second type doped area overlaps with at least one part of a projection of the second conductive layer on the substrate.
20. The anti-interference signal line according to claim 14 , wherein resistance of the second type doped area falls when the switching signal rises, and resistance of the second type doped area rises when the switching signal falls.
Unknown
December 11, 2018
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