Circuit and Method for Imprint Reduction in Fram Memories

1. A memory device comprising: a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line; and a sense amplifier that includes: first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type; a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, the first inverter including fifth and sixth transistors coupled in series between a first control signal line and a second control signal line, one of the fifth and sixth transistors being of the first conductivity type and the other of the fifth and sixth transistors being of the second conductivity type; and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line, the second inverter including seventh and eighth transistors coupled in series between the first control signal line and the second control signal line, one of the seventh and eighth transistors being of the first conductivity type and the other of the seventh and eighth transistors being of the second conductivity type; wherein the sense amplifier is configured to: in response to a read operation, amplify a difference voltage between a first data signal on the first bit line and a second data signal on the second bit line; and after amplifying the difference voltage, activate the first and second inverters in response to a reference voltage being supplied to the first control signal line and a supply voltage being supplied to the second control signal line to invert the first data signal on the first bit line and invert the second data signal on the second bit line.

2. The memory device of claim 1 , wherein the first conductivity type is n-type and the second conductivity type is p-type, and wherein the first and second transistors are n-channel transistors and the third and fourth transistors are p-channel transistors.

3. The memory device of claim 1 , comprising: a first switching transistor coupled between the first bit line and the first common drain terminal; and a second switching transistor coupled between the second bit line and the second common drain terminal.

4. The memory device of claim 3 , wherein the first and second switching transistors are of the first conductivity type.

5. The memory device of claim 1 , wherein: a gate terminal of the fifth transistor and a gate terminal of the sixth transistor are each coupled to the first common drain terminal; and a gate terminal of the seventh transistor and a gate terminal of the eighth transistor are each coupled to the second common drain terminal.

6. The memory device of claim 1 , wherein a data state indicated by the inverted first data signal is written to the first memory cell and a data state indicated by the inverted second data signal is written to the second memory cell prior to completion of the read operation.

7. The memory device of claim 6 , wherein the memory array comprises a ferroelectric memory array.

8. The memory device of claim 7 , wherein the first and second memory cells each include an access transistor and a ferroelectric capacitor, the first and second memory cells being part of a two-transistor, two-capacitor (2T-2C) ferroelectric memory cell of the ferroelectric memory array.

9. The memory device of claim 8 , comprising: a first word line coupled to each access transistor of the 2T-2C ferroelectric memory cell; and a first plate line coupled to each ferroelectric capacitor of the 2T-2C ferroelectric memory cell.

10. The memory device of claim 7 , wherein the first and second memory cells each include an access transistor and a ferroelectric capacitor, the first memory cell being a first one-transistor, one capacitor (1T-1C) ferroelectric memory cell of the ferroelectric memory array and the second memory cell being a second 1T-1C ferroelectric memory cell of the ferroelectric memory array.

11. The memory device of claim 10 , comprising: a first word line coupled to a first access transistor of the first 1T-1C ferroelectric memory cell; a second word line coupled to a second access transistor of the second 1T-1C ferroelectric memory cell; and a first plate line coupled to the ferroelectric capacitor of the first 1T-1C ferroelectric memory cell and the ferroelectric capacitor of the second 1T-1C ferroelectric memory cell.

12. The memory device of claim 1 , wherein the first and second bit lines are complementary bit lines.

13. A memory device comprising: a memory array that includes a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line; and a sense amplifier that includes: first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type; a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, the first inverter including fifth and sixth transistors coupled in series between a first control signal line and a second control signal line, one of the fifth and sixth transistors being of the first conductivity type and the other of the fifth and sixth transistors being of the second conductivity type, and wherein a gate terminal of the fifth transistor and a gate terminal of the sixth transistor are each coupled to the first common drain terminal; and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line, the second inverter including seventh and eighth transistors coupled in series between the first control signal line and the second control signal line, one of the seventh and eighth transistors being of the first conductivity type and the other of the seventh and eighth transistors being of the second conductivity type, and wherein a gate terminal of the seventh transistor and a gate terminal of the eighth transistor are each coupled to the second common drain terminal.

14. The memory device of claim 13 , wherein the sense amplifier is configured to: in response to a read operation, amplify a difference voltage between a first data signal on the first bit line and a second data signal on the second bit line; and after amplifying the difference voltage, activate the first and second inverters in response to a reference voltage being supplied to the first control signal line and a supply voltage being supplied to the second control signal line to invert the first data signal on the first bit line and invert the second data signal on the second bit line.

15. The memory device of claim 14 , wherein a data state indicated by the inverted first data signal is written to the first memory cell and a data state indicated by the inverted second data signal is written to the second memory cell prior to completion of the read operation.

16. The memory device of claim 13 , comprising: a first switching transistor coupled between the first bit line and the first common drain terminal; and a second switching transistor coupled between the second bit line and the second common drain terminal.

17. The memory device of claim 13 , wherein: the gate terminal of the fifth transistor and the gate terminal of the sixth transistor are each also coupled to a gate terminal of the second transistor and a gate terminal of the fourth transistor; and the gate terminal of the seventh transistor and the gate terminal of the eighth transistor are each also coupled to a gate terminal of the first transistor and a gate terminal of the second transistor.

18. An electronic system comprising: a memory to store instructions; and a processor to execute the instructions stored by the memory, wherein the memory includes: a memory array having a first memory cell coupled to a first bit line and a second memory cell coupled to a second bit line; and a sense amplifier having: first and second transistors arranged in a cross-coupled configuration with third and fourth transistors, the first and second transistors being of a first conductivity type and the third and fourth transistors being of a second conductivity type; a first inverter having an input coupled to a first common drain terminal of the first and third transistors and an output coupled to the first bit line, the first inverter including fifth and sixth transistors coupled in series between a first control signal line and a second control signal line, one of the fifth and sixth transistors being of the first conductivity type and the other of the fifth and sixth transistors being of the second conductivity type; and a second inverter having an input coupled to a second common drain terminal of the second and fourth transistors and an output coupled to the second bit line, the second inverter including seventh and eighth transistors coupled in series between the first control signal line and the second control signal line, one of the seventh and eighth transistors being of the first conductivity type and the other of the seventh and eighth transistors being of the second conductivity type; wherein the sense amplifier is configured to, in response to a read operation, amplify a difference voltage between a first data signal on the first bit line and a second data signal on the second bit line, and, after amplifying the difference voltage, activate the first and second inverters in response to a reference voltage being supplied to the first control signal line and a supply voltage being supplied to the second control signal line to invert the first data signal on the first bit line and invert the second data signal on the second bit line.

19. The electronic device of claim 18 , comprising: a first switching transistor coupled between the first bit line and the first common drain terminal; and a second switching transistor coupled between the second bit line and the second common drain terminal.

20. The electronic device of claim 18 , wherein: a gate terminal of the fifth transistor and a gate terminal of the sixth transistor are each coupled to the first common drain terminal, a gate terminal of the second transistor, and a gate terminal of the fourth transistor; and a gate terminal of the seventh transistor and a gate terminal of the eighth transistor are each coupled to the second common drain terminal, a gate terminal of the first transistor, and a gate terminal of the third transistor.