Opportunistic Increase of Ways in Memory-Side Cache

1. A processor comprising: a processor core; and a cache controller coupled to the processor core, the cache controller to allocate, for a memory, a plurality of cache entries in a cache; and wherein the processor core is to, in response to decoding and executing an instruction: detect an amount of the memory installed in one or more memory sockets of a computing system; determine a maximum allowable amount of memory for the computing system according to maximum capacity of the one or more memory sockets; and responsive to detecting less than the maximum allowable amount of memory installed in the computing system, direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

2. The processor of claim 1 , wherein the cache is a multi-channel dynamic random-access memory (MCDRAM) memory-side cache and the cache controller is a high bandwidth cache controller.

3. The processor of claim 1 , wherein to increase the number ways, the cache controller is to update memory allocation to the cache from direct-mapped to set-associative.

4. The processor of claim 1 , wherein to increase the number of ways, the cache controller is to update memory allocation to the cache from two-way set-associative to four-way set-associative.

5. The processor of claim 1 , wherein the instruction causes the processor core to further: detect, after boot of the computing system, the amount of the memory installed; and direct the cache controller to flush the cache before directing the cache controller to increase the number of ways of the cache.

6. The processor of claim 1 , wherein the cache comprises a metadata storage circuit coupled to the cache controller, the metadata storage circuit to store a metadata array, wherein to increase the number of ways, the cache controller is to couple one or more additional tag comparators to the metadata storage circuit, resulting in a number of tag comparators corresponding to the number of ways.

7. The processor of claim 6 , wherein the cache controller comprises a tag decoder coupled to the metadata storage circuit, wherein to increase the number of ways, the cache controller is further to reconfigure the tag decoder to access the metadata array according to a plurality of sets of ways matching the increase in the number of ways.

8. The processor of claim 1 , wherein the cache further comprises a data storage circuit coupled to the cache controller, wherein the cache controller comprises a data decoder coupled to the data storage circuit, and wherein to increase the number of ways, the cache controller is to reconfigure the data decoder to access the data storage circuit according to a plurality of sets of ways matching the increase in the number of ways.

9. The processor of claim 1 , wherein the cache controller is to employ unused tag bits in incoming addresses for use in one of least-recently used (LRU) tracking or in cyclic redundancy check (CRC) error correction of the cache entries.

10. A system comprising: a processor; a cache controller coupled to the processor; and a cache coupled to the cache controller, wherein the cache controller is to allocate, for a memory, a plurality of cache entries in the cache; and wherein the processor is to, in response to decoding and executing an instruction: detect an amount of the memory installed in one or more memory sockets of the system; determine a maximum allowable amount of memory for the system according to maximum capacity of the one or more memory sockets; and responsive to detecting less than the maximum allowable amount of memory installed in the system: direct the cache controller to flush the cache; and direct the cache controller to increase a number of ways of the cache in which to allocate the plurality of cache entries.

11. The system of claim 10 , wherein the cache is a multi-channel dynamic random-access memory (MCDRAM) memory-side cache and the cache controller is a high bandwidth memory controller.

12. The system of claim 10 , wherein to increase the number ways, the cache controller is to update memory allocation to the cache from direct-mapped to set-associative.

13. The system of claim 10 , wherein to increase the number of ways, the cache controller is to update memory allocation to the cache from two-way set-associative to four-way set-associative.

14. The system of claim 10 , wherein the cache comprises a metadata storage circuit coupled to the cache controller, the metadata storage circuit to store a metadata array, wherein to increase the number of ways, the cache controller is to couple one or more additional tag comparators to the metadata storage circuit, resulting in a number of tag comparators corresponding to the number of ways.

15. The system of claim 14 , wherein the cache controller comprises a tag decoder coupled to the metadata storage circuit, wherein to increase the number of ways, the cache controller is further to reconfigure the tag decoder to access the metadata array according to a plurality of sets of ways matching the increase in the number of ways.

16. The system of claim 10 , wherein the cache further comprises a data storage circuit coupled to the cache controller, wherein the cache controller comprises a data decoder coupled to the data storage circuit, and wherein to increase the number of ways, the cache controller is to reconfigure the data decoder to access the data storage circuit according to a plurality of sets of ways matching the increase in the number of ways.

17. A method comprising: allocating, by a multi-core processor of a computing system and for a memory, a plurality of cache entries in a cache of the memory; detecting, by the multi-core processor, an amount of the memory installed in one or more memory sockets of the computing system; determining, by the multi-core processor, a maximum allowable amount of memory for the computing system according to maximum capacity of the one or more memory sockets; and increasing, by the multi-core processor, a number of ways of the cache in which to allocate the plurality of cache entries, wherein the increasing is in response to detecting less than the maximum allowable amount of memory installed in the computing system.

18. The method of claim 17 , wherein, in response to the increasing, the method further comprising updating memory allocation to the cache from direct-mapped to set-associative.

19. The method of claim 17 , wherein, in response to the increasing, the method further comprising updating memory allocation to the cache from four-way set-associative to eight-way set-associative.

20. The method of claim 17 , further comprising: detecting the amount of the memory installed after boot of the computing system; and flushing the cache before increasing the number of ways of the cache.

21. The method of claim 17 , wherein the multi-core processor comprises a tag comparator, and wherein, to increase the number of ways, the method further comprising coupling one or more additional tag comparators to a metadata storage circuit, resulting in a number of tag comparators corresponding to the number of ways.

22. The method of claim 21 , wherein the multi-core processor further comprises a tag decoder coupled to the metadata storage circuit, wherein, to increase the number of ways, the method further comprising reconfiguring, the tag decoder to access a metadata array of the metadata storage circuit according to a plurality of sets of ways matching the increase in the number of ways.

23. The method of claim 17 , wherein the multi-core processor comprises a data decoder coupled to a data storage circuit of the cache, wherein, to increase the number of ways, the method further comprising reconfiguring the data decoder to access the data storage circuit according to a plurality of sets of ways matching the increase in the number of ways.