Legal claims defining the scope of protection, as filed with the USPTO.
1. An Integrated Circuit (IC) device comprising: a memory system to receive a program command from a controller, the memory system including a non-volatile auxiliary memory to store an Exclusive OR (XOR) program, the non-volatile auxiliary memory to execute the XOR program in response to the program command to achieve reduced system overhead during memory write and read operations in the memory system and to reduce time and power consumption, the non-volatile auxiliary memory, based on the XOR program, to, update a parity bit of previous parity information stored in the non-volatile auxiliary memory of the memory system based on a first value of a parity bit of updated parity information regardless of a value of the parity bit of the previous parity information, wherein the non-volatile auxiliary memory updates the parity bit of the previous parity information without intervention from the controller after the memory system receives the program command from the controller, and keep the parity bit of the previous parity information at a same value based on a second value of the parity bit of the updated parity information, the second value being different from the first value, wherein the non-volatile auxiliary memory keeps the parity bit of the previous parity information at the same value without intervention from the controller after the memory system receives the program command from the controller, wherein the previous parity information is associated with first data stored in the non-volatile auxiliary memory of the memory system, and wherein the updated parity information associated with second data different from the first data, and the updated parity information is included in an accumulated parity sum of data stored in the memory system for recovering an original data from a corrupted data in the memory system.
2. The IC device of claim 1 wherein the XOR program operates to receive an input address and an input data from a controller when the program command is provided to the memory system from the controller.
3. The IC device of claim 2 wherein the XOR program operates to obtain read data stored at the input address, to perform an XOR operation of the read data and the input data to generate the parity information, and to write the parity information in the IC device.
4. The IC device of claim 1 wherein the IC device comprises a memory device.
5. The IC device of claim 1 wherein the IC device comprises a non-volatile memory device.
6. The IC device of claim 5 wherein the non-volatile memory device comprises a phase change memory.
7. The IC device of claim 1 configured to have a command set including the program command.
8. The IC device of claim 1 configured to comprise program instructions for implementing the program command.
9. A method of parity generation in a memory system, the method comprising: receiving a program command at the memory system, the program command provided from a controller, wherein receiving the program command is performed by the memory system, the memory system including a non-volatile auxiliary memory to store an internal program; and responsive to receiving the program command, the non-volatile auxiliary memory of the memory system executing the internal program to achieve reduced system overhead during memory write and read operations in the memory system and to reduce time and power consumption, the non-volatile auxiliary memory, based on the internal program, to accumulate a parity sum by either, updating, performed by the non-volatile auxiliary memory of the memory system without intervention from the controller after the program command is provided to the memory system, a parity bit of previous parity information stored in the memory system regardless of a value of the parity bit of the previous parity information if a parity bit of the updated parity information has a first value, or keeping, performed by the non-volatile auxiliary memory of the memory system without intervention from the controller after the program command is provided to the memory system, the parity bit of the previous parity information at a same value if the parity bit of the updated parity information has a second value, the second value being different from the first value, the previous parity information associated with first data stored in the non-volatile auxiliary memory of the memory system, the updated parity information associated with second data, the second data provided to the memory system from the controller when the program command is provided to the memory system from the controller, wherein the updated parity information is included in an accumulated parity sum of data stored in the memory system for recovering an original data from a corrupted data in the memory system.
10. The method of claim 9 wherein the internal program implements an Exclusive Or (XOR) Program.
11. The method of claim 9 wherein the first value of the parity bit of the updated parity information is equal to 1, and updating the parity bit of the previous parity information includes changing the value of the parity bit of the previous parity information from 1 to 0.
12. The method of claim 9 wherein the first value of the parity bit of the updated parity information is equal to 1, and updating the parity bit of the previous parity information includes changing the value of the parity bit of the previous parity information from 0 to 1.
13. The method of claim 9 wherein the internal program refrains from temporarily storing the updated parity information in external temporary storage areas.
14. The method of claim 9 further comprising: executing the internal program, performed by the non-volatile auxiliary memory, to accumulate a parity sum for a plurality of data pages in the memory system; and recovering an original page of data from a corrupted data page in the plurality of data pages by subtracting from the accumulated parity sum a parity sum of all data pages the plurality of pages except the corrupted data page.
15. A non-transitory computer-readable medium comprising instructions that, when implemented on a machine, cause the machine to: execute an internal program stored in a non-volatile auxiliary memory in a memory system in response to a program command provided to the memory system from a controller to achieve reduced system overhead during memory write and read operations in the memory system and to reduce time and power consumption, wherein the internal program stored in a non-volatile auxiliary memory in the memory system operates to accumulate a parity sum by either, updating, performed by the non-volatile auxiliary memory without intervention from the controller after the program command is provided to the memory system, a parity bit of previous parity information stored in the non-volatile auxiliary memory of the memory system regardless of a value of the bit of the previous parity information if a parity bit of the updated parity information has a first value, or keeping, performed by the non-volatile auxiliary memory without intervention from the controller after the program command is provided to the memory system, the parity bit of the previous parity information at a same value if the parity bit of the updated parity information has a second value, the second value being different from the first value, the previous parity information associated with first data stored in the non-volatile auxiliary memory of the memory system, the updated parity information associated with second data, the second data provided to the memory system from the controller when the program command is provided to the memory system from the controller, and the updated parity information is included in an accumulated parity sum of data stored in the memory system for recovering an original data from a corrupted data in the memory system.
16. The computer readable medium of claim 15 wherein the internal program operates to generate the updated parity information from data pages.
17. The computer readable medium of claim 15 wherein the program implements an XOR logical operation for updating parity bit values of the previous parity information.
18. An apparatus comprising: a first non-volatile memory device in a memory system to store data information; and a second non-volatile memory device in the memory system to store an internal program and to store parity information associated with the data information stored in the first non-volatile memory device, the second non-volatile memory device to execute the internal program in response to a program command to achieve reduced system overhead during memory write and read operations in the memory system and to reduce time and power consumption, the second non-volatile memory device, based on the internal program, to either overwrite old parity information stored in the second non-volatile memory device with new parity information in response to a program command provided by a controller regardless of a value of the old parity information if the new parity information has a first value, wherein the second non-volatile memory device overwrites the old parity information without intervention from the controller after the memory system receives the program command from the controller or keep the old parity information at a same value if the new parity information has a second value, wherein the second non-volatile memory device keeps the old parity information the same value without intervention from the controller after the memory system receives the program command from the controller, the second value being different from the first value, the old parity information associated with first data stored in the second non-volatile memory device, the new parity information associated with second data, the second data provided from the controller when the program command is provided, wherein the new parity information is included in an accumulated parity sum of data stored in the memory system for recovering an original data from a corrupted data in the memory system.
19. The apparatus of claim 18 , wherein the first and second non-volatile memory devices comprise different non-volatile memory types.
20. The apparatus of claim 18 , wherein the first non-volatile memory device includes a flash memory device.
21. The apparatus of claim 18 , wherein the second non-volatile memory device includes a phase change memory device.
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January 8, 2019
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