Performance Scaling for Binary Translation

1. A method performed by a computing device comprising storage hardware and processing hardware, the method performed by the processing hardware executing instructions stored in the storage hardware, the method comprising: executing an operating system kernel that manages execution of threads on the processing hardware, wherein the processing hardware comprises a processor that natively implements a target instruction set architecture (ISA), wherein the threads comprise (i) binary-translated threads comprised of instructions in the target ISA that have been binary-translated from instructions in a source ISA, the source ISA not natively implemented by the processor and (ii) non-translated threads comprised of instructions in the target ISA that have not been translated from instructions in the source ISA, wherein the processor comprises a power-performance adjustment mechanism that can be adjusted by the kernel to (i) increase the speed at which the processor executes instructions in the target ISA, and (ii) decrease the speed at which the processor executes instructions; and the managing the execution of the threads on the processing hardware comprising identifying which threads are binary-translated threads, and based on the identifying, using, by the kernel, the power-performance adjustment mechanism to cause the instructions of the threads identified as binary-translated threads to be executed with higher speed relative to execution of the instructions of the instructions of the non-translated threads.

2. A method according to claim 1 , wherein the power-performance adjustment mechanism comprises a clock rate, a core type, a variable number of cores, a voltage level, and/or a P-state (Performance state).

3. A method according to claim 1 , wherein the identifying comprises determining that code corresponds to the source ISA.

4. A method according to claim 1 , wherein the processor comprises a first core and a second core, the first core configured to operate, for arbitrary instructions, with higher speed and power consumption than the second core, and wherein the using the power-performance adjustment mechanism comprises scheduling threads identified as binary-translated to the first core on the basis of having been identified as binary-translated code.

5. A method according to claim 1 , further comprising receiving translation information corresponding to overhead of translating and/or executing translated code.

6. A method according to claim 1 , wherein the instructions in the source ISA comprise instructions compiled from source code, and wherein the method further comprises analyzing the instructions in the source ISA and, based on the instructions in the source ISA, translating the instructions in the source ISA.

7. A computing device comprising: processing hardware comprising a processor, the processor configured to implement a native instruction set architecture (ISA), the processor configured to vary the speed at which arbitrary instructions of the native ISA are executed; storage hardware storing an operating system comprising a loader and a kernel, and storing executable files, the executable files comprising compiled code comprising machine instructions, the loader configured to load the executable files, the kernel configured to allocate memory to store instructions loaded by the loader from the executable files; the memory hardware from which the memory is allocated, the memory hardware configured to store the instructions of the executable files loaded by the loader; and the kernel configured to vary the speed at which the processor executes the instructions in memory according to whether the instructions have been translated from machine instructions in a non-native ISA not implemented by the processor.

8. A computing device according to claim 7 , the storage hardware and/or the processing hardware comprising a binary translator configured to receive instructions in the non-native ISA and translate the received instructions into instructions in the native ISA, wherein execution units, comprised of instructions for the native ISA provided by the binary translator, are marked to indicate that they have been produced by the binary translator.

9. A computing device according to claim 8 , wherein the kernel varies the speed of the processor based on the flags.

10. A computing device according to claim 8 , wherein the execution units comprise threads.

11. A computing device according to claim 10 , wherein operating system further comprises an power module, wherein the power module is configured to vary power consumption of the processor, and wherein the power module is configured to vary power consumption of the processor on a per-thread basis according to, at least in part, whether threads comprise either native ISA instructions translated from non-native ISA instructions or comprise non-native ISA instructions that are translated to ISA instructions when executed.

12. A computing device according to claim 7 , wherein the speed at which the processor executes the instructions is further varied according to a feature of the instructions.

13. A computing device according to claim 12 , wherein the feature comprises a count or ratio of an instruction among the instructions executed, a workload flag.

14. A computing device according to claim 7 , wherein the speed at which the processor executes the instructions varies in accordance with an estimate of an efficiency of non-native ISA efficiency relative to native ISA efficiency.

15. A method performed by a computing device, the method comprising: executing an operating system that schedules the execution of execution units by a processor that implements a native instruction set architecture (ISA); and executing the execution units by causing the processor to, when executing translated execution units, operate faster than when executing non-translated execution units, the instructions of the translated execution units translated from binary instructions compiled to execute for a non-native ISA, the processor not configured to implement the non-native ISA.

16. A method according to claim 15 , wherein the causing is based on differentiating between the translated execution units and the non-translated execution units.

17. A method according to claim 16 , wherein the differentiating comprises analyzing content of an executable file being loaded for execution.

18. A method according to claim 16 , wherein the differentiating comprises analyzing code to determine that the code comprises instructions corresponding to the non-native ISA.

19. A method according to claim 16 , wherein the differentiating comprises reading a flag that indicates code has been translated from instructions of the non-native ISA.

20. A method according to claim 15 , further comprising maintaining translation information indicating which execution units are the translated execution units, wherein the causing the processor to operate faster than when executing non-translated execution units is based on the translation information.