Hardware-Based Virtual Machine Communication

1. A processing system comprising: a processor to execute a first virtual machine (VM); and a VM-to-VM communication accelerator circuit, communicatively coupled to the processor, the VM-to-VM communication accelerator circuit comprising: a first interface device to support direct memory access (DMA) data transfers by the first VM; a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM; and a direct memory access (DMA) descriptor processing circuit to: process, using a working queue associated with the primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM; and execute, using the first interface device, the DMA data transfer based on the access permission.

2. The processing system of claim 1 , wherein the communication accelerator circuit further comprises a second register to store a reference to a secondary PF associated with a second interface device of a remote processing system hosting the second VM.

3. The processing system of claim 1 , wherein the access permission comprises at least one of a read permission, a write permission, or an execute permission.

4. The processing system of claim 1 , wherein the DMA descriptor comprises a virtual function identifier associated with a first virtual device of the first VM, a destination data address associated with a memory, and one of a source data address associated with the memory or a data payload.

5. The processing system of claim 1 , wherein the second VM resides on a remote processing system, and wherein a virtual machine monitor (VMM) controls the first VM and the second VM.

6. The processing system of claim 2 , wherein the primary PF is further associated with a completion queue referencing a plurality of DMA descriptors processed by the DMA descriptor processing circuit.

7. The processing system of claim 2 , wherein the VM-to-VM communication accelerator circuit further comprises a third register to store a reference to a primary virtual function (VF) associated with a first virtual device driver of the first VM, wherein the primary VF is associated with a working queue referencing a first plurality of DMA descriptors issued by the first VM and a completion queue referencing a second plurality of DMA descriptors issued by the first VM and processed by the DMA descriptor processing circuit, and wherein the VM-to-VM communication accelerator circuit further comprises one or more registers to store a reference to a secondary VF associated with a second virtual device of the second VM, and wherein the second interface device is to perform DMA data transfers issued by the second VM to the first VM.

8. The processing system of claim 2 , wherein the DMA descriptor processing circuit is further to: responsive to receiving a DMA descriptor issued by the first VM, identify the second VM as a destination of the DMA data transfer; determine, based on the ACT, that the first VM has a write permission to the second VM; execute, using the first interface device and the second interface device, the DMA data transfer from the first VM to the second VM; and responsive to determining that the DMA data transfer from the first VM to the second VM is completed, place the DMA descriptor on a completion queue of the primary PF.

9. The processing system of claim 5 , wherein the DMA descriptor processing circuit is further to: responsive to receiving the DMA descriptor posted by the first VM, identify the second VM as a destination of the DMA data transfer; determine that the first VM has a write permission to the second VM based on the ACT; execute, using the first interface device and a second interface device, the DMA data transfer from the first VM to the second VM; and responsive to determining that the DMA data transfer from the first VM to the second VM is completed, place the DMA descriptor on a completion queue of the primary PF.

10. A system, comprising: a first interface device to support direct memory access (DMA) data transfers by a first virtual machine (VM); and a VM-to-VM communication accelerator circuit, communicatively coupled to a processor to execute the first VM, the VM-to-VM communication accelerator circuit comprising: a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM; and a direct memory access (DMA) descriptor processing circuit to: process, using a working queue associated with the primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM; and execute, using the first interface device, the DMA data transfer based on the access permission.

11. The system of claim 10 , wherein the communication accelerator circuit further comprises a second register to store a reference to a secondary PF associated with a second interface device of a remote processing system hosting the second VM.

12. The system of claim 10 , wherein the access permission comprises at least one of a read permission, a write permission, or an execute permission.

13. The system of claim 10 , wherein the DMA descriptor comprises a virtual function identifier associated with a first virtual device of the first VM, a destination data address associated with a memory, and one of a source data address associated with the memory or a data payload.

14. The system of claim 10 , wherein the second VM resides on a remote processing system, and wherein a virtual machine monitor (VMM) controls the first VM and the second VM.

15. The system of claim 11 , wherein the primary PF is further associated with a completion queue referencing a plurality of DMA descriptors processed by the DMA descriptor processing circuit.

16. The system of claim 11 , wherein the VM-to-VM communication accelerator circuit further comprises a third register to store a reference to a primary virtual function (VF) associated with a first virtual device driver of the first VM, wherein the primary VF is associated with a working queue referencing a first plurality of DMA descriptors issued by the first VM and a completion queue referencing a second plurality of DMA descriptors issued by the first VM and processed by the DMA descriptor processing circuit, and wherein the VM-to-VM communication accelerator circuit further comprises one or more registers to store a reference to a secondary VF associated with a second virtual device of the second VM, and wherein the second interface device performs DMA data transfers issued by the second VM to the first VM.

17. The system of claim 11 , wherein the DMA descriptor processing circuit is further to: responsive to receiving a DMA descriptor issued by the first VM, identify the second VM as a destination of the DMA data transfer; determine, based on the ACT, that the first VM has a write permission to the second VM; execute, using the first interface device and the second interface device, the DMA data transfer from the first VM to the second VM; and responsive to determining that the DMA data transfer from the first VM to the second VM is completed, place the DMA descriptor on a completion queue of the primary PF.

18. The system of claim 14 , wherein the DMA descriptor processing circuit is further to: responsive to receiving the DMA descriptor posted by the first VM, identify the second VM as a destination of the DMA data transfer; determine that the first VM has a write permission to the second VM based on the ACT; execute, using the first interface device and a second interface device, the DMA data transfer from the first VM to the second VM; and responsive to determining that the DMA data transfer from the first VM to the second VM is completed, place the DMA descriptor on a completion queue of the primary PF.

19. A method comprising: receiving, by an accelerator circuit communicatively coupled to a processor, a direct memory access (DMA) descriptor issued by a first virtual machine (VM) executing on the processor, the DMA descriptor specifying a DMA data transfer between the first virtual machine and a second virtual machine using a first interface device associated with the processor; determining, based on an access control table (ACT), an access permission from the first VM to the second VM, wherein the accelerator circuit comprises a register to store a reference to a physical function (PF) associated with the first interface device, and wherein the PF is associated with the ACT specifying the access permission; and executing, using the first interface device, the DMA data transfer based on the access permission.

20. The method of claim 19 , wherein the second VM resides on a remote processing system that is communicatively coupled to the processor using a second interface device.