System and Method for Instance Snapping

1. A method for physically implementing a design for an integrated circuit, comprising: identifying a set of tracks in a layer of a plurality of layers of the integrated circuit; and identifying an instance of an electronic component of the design of the integrated circuit, the instance comprising a plurality of shapes; and snapping the instance to the set of tracks by causing the design of the integrated circuit to be updated such that certain of the plurality of shapes in the instance are placed in valid locations in the layer of the integrated circuit with respect to requirements associated with the set of tracks, wherein the requirements are further associated with causing the design of the integrated circuit to be fabricated in a target fabrication process.

2. A method according to claim 1 , further comprising creating a geometric representation of the set of tracks.

3. A method according to claim 2 , wherein snapping includes using the geometric representation to identify a matching track in the set of tracks for one of the plurality of shapes with respect to the requirements.

4. A method according to claim 1 , wherein snapping includes: identifying a widest one of the plurality of shapes; and identifying a matching track in the set of tracks for the widest one of the plurality of shapes with respect to the requirements.

5. A method according to claim 1 , wherein the requirements include an assigned color for one or more of the set of tracks, the assigned color corresponding to a pattern in a multiple patterning process for the integrated circuit, wherein snapping includes matching the assigned color for one of the set of tracks to a color attribute of one of the plurality of shapes of the instance that is placed on the one track.

6. A method according to claim 1 , wherein the requirements include a specified width for one or more of the set of tracks, wherein snapping includes matching the specified width for one of the set of tracks to a width of one of the plurality of shapes of the instance that is placed on the one track.

7. A method according to claim 1 , wherein the requirements include a specified width and spacing for one or more of the set of tracks, wherein snapping includes matching the specified width and spacing for one of the set of tracks to a width and location of one of the plurality of shapes of the instance that is placed on the one track.

8. A method according to claim 7 , wherein the specified width for the one track is different than the specified width for another one of the set of tracks.

9. A method according to claim 7 , wherein the specified spacing for the one track is different than the specified spacing for another one of the set of tracks.

10. A method according to claim 1 , wherein the certain shapes are all of the shapes of the instance in the layer.

11. A method according to claim 1 , wherein the certain shapes are a maximum number of the shapes of the instance in the layer for all possible snapping locations.

12. A method according to claim 1 , wherein the instance is at one level of hierarchy associated with the instance in the design, and wherein the plurality of shapes are configured for the one level of hierarchy.

13. A non-transitory computer readable storage medium having instructions stored thereon which, when executed by a computer, cause the computer to execute a method for physically implementing a design for an integrated circuit, the method comprising: identifying a set of tracks in a layer of a plurality of layers of the integrated circuit; and identifying an instance of an electronic component of the design of the integrated circuit, the instance comprising a plurality of shapes; and snapping the instance to the set of tracks by causing an electronic file containing the design of the integrated circuit to be updated such that the design specifies that certain of the plurality of shapes in the instance are placed in valid locations in the layer of the integrated circuit with respect to requirements associated with the set of tracks, wherein the electronic file is configured for causing the design of the integrated circuit to be fabricated in a target fabrication process.

14. The computer readable storage medium according to claim 13 , the method further comprising creating a geometric representation of the set of tracks, and wherein snapping includes using the geometric representation to identify a matching track in the set of tracks for one of the plurality of shapes with respect to the requirements.

15. The computer readable storage medium according to claim 13 , wherein snapping includes: identifying a widest one of the plurality of shapes; and identifying a matching track in the set of tracks for the widest one of the plurality of shapes with respect to the requirements.

16. The computer readable storage medium according to claim 13 , wherein the requirements include an assigned color for one or more of the set of tracks, the assigned color corresponding to a pattern in a multiple patterning process for the integrated circuit, wherein snapping includes matching the assigned color for one of the set of tracks to a color attribute of one of the plurality of shapes of the instance that is placed on the one track.

17. The computer readable storage medium according to claim 13 , wherein the requirements include a specified width for one or more of the set of tracks, wherein snapping includes matching the specified width for one of the set of tracks to a width of one of the plurality of shapes of the instance that is placed on the one track.

18. The computer readable storage medium according to claim 13 , wherein the requirements include a specified width and spacing for one or more of the set of tracks, wherein snapping includes matching the specified width and spacing for one of the set of tracks to a width and location of one of the plurality of shapes of the instance that is placed on the one track, and wherein the specified width for the one track is different than the specified width for another one of the set of tracks, and wherein the specified spacing for the one track is different than the specified spacing for another one of the set of tracks.

19. A system for physically implementing a design for an integrated circuit, comprising: one or more interactive modules for allowing a user to identify an electronic component of the design and a layer of a plurality of layers of the integrated circuit, the one or more interactive module further identifying an instance of the electronic component, the instance comprising a plurality of shapes; a track module that, in response to the user identifying the layer of the integrated circuit, identifies a set of tracks in a layer of the integrated circuit; and a snapping module that communicates with the track module and snaps the instance to the set of tracks by causing the design of the integrated circuit to be updated such that certain of the plurality of shapes in the instance are placed in valid locations in the layer of the integrated circuit with respect to requirements associated with the set of tracks, wherein the requirements are further associated with causing the design of the integrated circuit to be fabricated in a target fabrication process.

20. The system according to claim 19 , wherein the requirements include a specified width and spacing for one or more of the set of tracks, wherein the snapping module is adapted to match the specified width and spacing for one of the set of tracks to a width and location of one of the plurality of shapes of the instance that is placed on the one track, and wherein the specified width for the one track is different than the specified width for another one of the set of tracks, and wherein the specified spacing for the one track is different than the specified spacing for another one of the set of tracks.