10303504

Systems, Methods, and Apparatuses for Resource Monitoring

PublishedMay 28, 2019
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
17 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A system comprising: a hardware processor core to decode and execute a single resource monitoring identification (RMID) recycling instruction, a RMID to be a software-defined identification for one or more software threads scheduled to run on a logical processor; memory to store the single RMID recycling instruction that when executed by a hardware processor core recycles the RMID RMID; a plurality of logical processors, each logical processor including associated first storage to store a selected least recently used RMID and second storage to store state for the associated logical processor at the hardware processor core swap on.

2

2. The system of claim 1 , wherein the each logical processor is a thread.

3

3. The system of claim 1 , wherein the first storage is a machine state register for the each logical processor in the hardware processor core.

4

4. The system of claim 1 , wherein the hardware processor core further comprises: a plurality of machine state registers to store resource monitoring data; and a plurality of machine state registers to store an event to be associated with an RMID.

5

5. The system of claim 4 , wherein the event is memory bandwidth.

6

6. The system of claim 4 , wherein the event is cache occupancy.

7

7. The system of claim 1 , wherein the RMID recycling instruction, when executed by the hardware processor core is to cause: a selection of the least recently used RMID; at hardware processor core swap on, a write of the selected RMID to the associated storage for the RMID and a write of a logical processor state to the associated storage for the state; and at hardware processor core swap off, a return of the selected RMID to a pool.

8

8. The system of claim 7 , wherein the RMID recycling instruction, when executed by the hardware processor core to further cause a selection of a physical RMID.

9

9. The system of claim 7 , wherein the RMID is to be returned to the pool as a most recently used RMID.

10

10. The system of claim 1 , wherein the RMID recycling instruction, when executed by the hardware processor core to cause: a selection of an RMID from a least recently used end of a first in, first out queue of RMIDs; a determination that the selected RMID's occupancy is below a threshold; at hardware processor core swap on, a write of the selected RMID to the associated storage for the logical processor and a write of the logical processor state to the associated storage for the state; and at hardware processor core swap off, a return of the selected RMID to a pool.

11

11. The system of claim 1 , wherein the RMID recycling instruction, when executed by the hardware processor core are to cause: an establishment of a baseline of cache occupancy for an RMID; select an RMID and measure its cache occupancy at the hardware processor core swap on of the logical processor; measure the cache occupancy of the RMID at hardware processor core swap off of the logical processor; update the baseline with a delta value based on the measured cache occupancy to the baseline.

12

12. A method performed by a system having a hardware processor core and memory, wherein the hardware processor core includes a plurality of logical processors each have associated storage, the method comprising: selecting a least recently used resource monitoring identification (RMID); at hardware processor core swap on, writing the selected RMID to the associated storage for the RMID and writing of a logical processor state to the associated storage for the state; and at hardware processor core swap off, returning of the selected RMID to a pool.

13

13. The method of claim 12 , further comprising: determining that a cache occupancy associated with the selected RMID is below a threshold.

14

14. The method of claim 12 , wherein the logical processor is a thread.

15

15. The method of claim 12 , wherein the storage for the RMID is a machine state register per logical processor in the hardware processor core.

16

16. The method of claim 12 , wherein the hardware core further comprises: a plurality of machine state registers to store resource monitoring data; and a plurality of machine state registers to store an event to be associated with an RMID.

17

17. The method of claim 16 , wherein the event is cache occupancy.

Patent Metadata

Filing Date

Unknown

Publication Date

May 28, 2019

Inventors

Matthew FLEMING
Edwin VERPLANKE
Andrew HERDRICH
Ravishankar IYER

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