Display Device Including Touch Screen and Driving Circuit for Driving Display Device

1. A display device including a touch screen comprising: a display panel including: pixels at intersections of data lines and gate lines, grouped into a plurality of blocks, and dividedly driven, each of the plurality of blocks connected to a different set of the gate lines, each set including at least a first gate line and a last gate line, and a plurality of touch electrodes; a display driving circuit configured to apply data of an input image to the pixels in a plurality of display periods divided from one frame period including at least a first display period and a second display period; a touch sensing unit configured to drive the touch electrodes in a touch sensing period assigned between the first display period and the second display period of the one frame period; and a timing controller configured to generate a multi-start signal including a plurality of pulses at predetermined time intervals in the one frame period, wherein a first block of the plurality of blocks is driven during the first display period, and a second block of the plurality of blocks adjacent to the first block is driven during the second display period following the touch sensing period, wherein the display driving circuit includes an (N−1)th stage configured to drive a last gate line of the first block and an Nth stage configured to drive a first gate line of the second block, wherein the Nth stage includes a charger configured to charge a Q node of the Nth stage in the touch sensing period in response to the multi-start signal before the second display period starts, and wherein another charger is disposed at a corresponding stage driving the first gate line of each block, or disposed at a corresponding stage driving the first gate line of each block except the first block.

2. The display device including the touch screen of claim 1 , wherein the display panel includes a single start line supplying the multi-start signal to a plurality of stages of the display driving circuit.

3. The display device including the touch screen of claim 1 , wherein the multi-start signal includes a number of pulses equal to the number of blocks or the number of blocks minus 1 during the one frame period.

4. The display device including the touch screen of claim 1 , wherein the display driving circuit includes a shift register disposed on a substrate of the display panel and configured to supply a gate pulse to the gate lines of the display panel and shift the gate pulse in response to a gate shift clock, wherein the shift register includes a plurality of stages that are cascade-connected, wherein each stage includes a pull-up transistor configured to charge an output terminal of the corresponding stage when the gate shift clock is input in response to a voltage of a Q node of the corresponding stage and a pull-down transistor configured to discharge the output terminal in response to a voltage of a QB node of the corresponding stage, and wherein the charger includes: a first transistor including a gate supplied with the multi-start signal, a drain supplied with a gate high voltage, and a source connected to an A node of the Nth stage, a second transistor including a gate connected to the A node, a drain supplied with the gate high voltage, and a source connected to the Q node; and a third transistor including a gate connected to a QB node of the Nth stage, a drain connected to the A node, and a source supplied with a gate low voltage less than the gate high voltage.

5. The display device including the touch screen of claim 1 , wherein the display driving circuit includes a shift register disposed on a substrate of the display panel and configured to supply a gate pulse to the gate lines of the display panel and shift the gate pulse in response to a gate shift clock, wherein the shift register includes a plurality of stages that are cascade-connected, wherein each stage includes a pull-up transistor configured to charge an output terminal of the corresponding stage when the gate shift clock is input in response to a voltage of a Q node of the corresponding stage, a first pull-down transistor configured to discharge the output terminal in response to a voltage of a first QB node of the corresponding stage, and a second pull-down transistor configured to discharge the output terminal in response to a voltage of a second QB node of the corresponding stage, and wherein the charger includes: a first transistor including a gate supplied with the multi-start signal, a drain supplied with a gate high voltage, and a source connected to an A node of the Nth stage; a second transistor including a gate connected to the A node, a drain supplied with the gate high voltage, and a source connected to the Q node; a 3a transistor including a gate connected to a first QB node of the Nth stage, a drain connected to the A node, and a source supplied with a gate low voltage less than the gate high voltage; and a 3b transistor including a gate connected to a second QB node of the Nth stage, a drain connected to the A node, and a source supplied with the gate low voltage.

6. A driving circuit of a display device including a touch screen including a display panel including pixels at intersections of data lines and gate lines, grouped into a plurality of blocks, and dividedly driven, each of the plurality of blocks connected to a different set of the gate lines, each set including at least a first gate line and a last gate line, and a plurality of touch electrodes, a first block of the plurality of blocks being driven during a first display period, and a second block of the plurality of blocks adjacent to the first block and being driven during a second display period, the driving circuit comprising: a touch sensing unit configured to drive the touch electrodes during a touch sensing period subsequent to the first display period but prior to the second display period; a timing controller configured to generate a multi-start signal including a plurality of pulses at predetermined time intervals in one frame period; and a shift register including an (N−1)th stage configured to drive a last gate line of the first block and an Nth stage configured to drive a first gate line of the second block, the Nth stage including a charger configured to charge a Q node of the Nth stage in response to the multi-start signal in the touch sensing period before the second display period starts, wherein another charger is disposed at a corresponding stage driving the first gate line of each block, or disposed at a corresponding stage driving the first gate line of each block except the first block.

7. The driving circuit of claim 6 , wherein the multi-start signal is supplied to a plurality of stages of the driving circuit through a single start line.

8. The driving circuit of claim 6 , wherein the multi-start signal includes a number of pulses equal to the number of blocks minus 1 during the one frame period.

9. The driving circuit of claim 6 , wherein the shift register is disposed on a substrate of the display panel and includes a plurality of stages that are cascade-connected, wherein each stage includes a pull-up transistor configured to charge an output terminal of the corresponding stage when a gate shift clock is input in response to a voltage of a Q node of the corresponding stage and a pull-down transistor configured to discharge the output terminal in response to a voltage of a QB node of the corresponding stage, and wherein the charger includes: a first transistor including a gate supplied with the multi-start signal, a drain supplied with a gate high voltage, and a source connected to an A node of the Nth stage; a second transistor including a gate connected to the A node, a drain supplied with the gate high voltage, and a source connected to the Q node; and a third transistor including a gate connected to a QB node of the Nth stage, a drain connected to the A node, and a source supplied with a gate low voltage less than the gate high voltage.

10. The driving circuit of claim 6 , wherein the shift register is disposed on a substrate of the display panel and includes a plurality of stages that are cascade-connected, wherein each stage includes a pull-up transistor configured to charge an output terminal of the corresponding stage when a gate shift clock is input in response to a voltage of a Q node of the corresponding stage, a first pull-down transistor configured to discharge the output terminal in response to a voltage of a first QB node of the corresponding stage, and a second pull-down transistor configured to discharge the output terminal in response to a voltage of a second QB node of the corresponding stage, and wherein the charger includes: a first transistor including a gate supplied with the multi-start signal, a drain supplied with a gate high voltage, and a source connected to an A node of the Nth stage; a second transistor including a gate connected to the A node, a drain supplied with the gate high voltage, and a source connected to the Q node; a 3a transistor including a gate connected to a first QB node of the Nth stage, a drain connected to the A node, and a source supplied with a gate low voltage less than the gate high voltage; and a 3b transistor including a gate connected to a second QB node of the Nth stage, a drain connected to the A node, and a source supplied with the gate low voltage.

11. A display device comprising: a display panel including a plurality of blocks of pixels at intersections of a plurality of gate lines and a plurality of data lines, the plurality of blocks of pixels including at least a first block and a second block adjacent to the first block, each of the plurality of blocks connected to a different set of the plurality of gate lines, each set including at least a first gate line and a last gate line, the first block driven to display during a first display period of a frame and the second block driven to display during a second display period of the frame, the second display period subsequent to and separated in time from the first display period by a predetermined period; and a gate driver circuit to drive gate lines of the display panel, the gate driver circuit including at least a first stage and a second stage to a first gate line of the first block and a second gate line of the second block, respectively, the first gate line and the second gate line being adjacent to each other, the second stage including a charger circuit configured to charge a Q node of the second stage during the predetermined period prior to the second display period, a gate pulse being supplied to the second gate line during at least a portion of the second display period when the Q node is charged to a predetermined level, wherein another charger is disposed at a corresponding stage driving the first gate line of each block, or disposed at a corresponding stage driving the first gate line of each block except the first block.

12. The display device of claim 11 , further comprising a timing controller that generates a plurality of timing signals to control timing of the first display period, the second display period, and the predetermined period between the first display period and the second display period, the timing signals including a start signal responsive to which the charger circuit of the second stage charges the Q node during the predetermined period.

13. The display device of claim 11 , further comprising a plurality of touch electrodes and a touch driver circuit, the touch driver circuit configured to drive the touch electrodes corresponding to at least one of the first block and the second block during the predetermined period.

14. The display device of claim 13 , wherein the touch electrodes function as a common electrode for the pixels to which a common voltage is applied, during the first display period and the second display period.

15. The display device of claim 11 , wherein none of the pixels are driven to display between the first display period and the second display period.

16. The display device of claim 11 , wherein the second stage includes a pull-up transistor configured to charge an output terminal coupled to the second gate line of the second block in response to a voltage of the Q node and a pull-down transistor configured to discharge the output terminal in response to a voltage of a QB node of the second stage, the gate pulse being supplied by the output terminal.

17. The display device of claim 11 , wherein the charger circuit includes: a first transistor including a gate supplied with a timing signal, a drain supplied with a gate high voltage, and a source connected to an A node of the second stage; a second transistor including a gate connected to the A node, a drain supplied with the gate high voltage, and a source connected to the Q node; and a third transistor including a gate connected to a QB node of the second stage, a drain connected to the A node, and a source supplied with a gate low voltage less than the gate high voltage.

18. The display device of claim 11 , wherein the charger circuit of the second stage charges the Q node in response to a timing signal generated outside the gate driver circuit.