Method and Apparatus for Scheduling the Issue of Instructions in a Multithreaded Processor

1. A method for dynamically determining which instructions from a plurality of available instructions to issue in a clock cycle of a multithreaded processor capable of executing a plurality of instructions in each clock cycle, the method comprising the steps of: determining a highest priority non-speculative instruction from the plurality of available instructions comprises determining a highest priority thread that is able to issue an instruction and selecting the instruction from that thread as the highest priority non-speculative instruction, wherein the highest priority non-speculative instruction cannot be an instruction that may not be necessary because an outcome of an earlier program instruction is not yet known; and issuing the highest priority non-speculative instruction together with other compatible available instructions in said clock cycle, to be executed by said multithreaded processor.

2. The method according to claim 1 , further comprising the step of marking speculative instructions, or threads with speculative instructions, as unavailable for the step of determining a highest priority non-speculative instruction.

3. The method of claim 2 , wherein threads with speculative instructions mark themselves as unavailable for determining a highest priority non-speculative instruction.

4. The method according to claim 1 , further comprising the step of determining a priority ranking for the plurality of available instructions, wherein compatible instructions are issued with the highest priority non-speculative instruction in order of priority ranking.

5. The method according to claim 4 , wherein the step of determining a priority ranking for the plurality of available instructions comprises the step of determining a priority ranking for each thread having an available instruction.

6. The method according to claim 1 , further comprising the step of determining a list of compatible or incompatible instructions for each of the available instructions.

7. The method according to claim 6 , wherein an instruction decode unit performs pre-decode of each instruction and determines instruction compatibility as a function of the pre-decode.

8. The method according to claim 7 , wherein the instruction decode unit compares resources needed for each available instruction against resources determined in parallel for all other threads active in the processor.

9. The method according to claim 8 , wherein the instruction decode unit performs said comparison on every clock cycle.

10. The method according to claim 9 , wherein the instruction decode unit performs said comparison for all active threads on every clock cycle.