Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; and circuitry to adjust the first and second PIs in accordance with the first clock phase, and the second or third clock phase.
2. The apparatus of claim 1 , wherein the first PI is an error PI, and wherein the second PI is an even PI.
3. The apparatus of claim 1 , further comprising a third PI coupled to the DLL, wherein the third PI is to provide a fourth clock phase, and further wherein the third PI is an odd PI.
4. The apparatus of claim 3 , wherein the first, second and third PIs are coupled respectively to a first, second and third buffers, wherein the buffers are clock trees, and wherein the buffers are to sample receiver data.
5. The apparatus of claim 3 , wherein the first, second and third PIs are coupled to a PI Finite State Machine (PI-FSM), and wherein the PI-FSM is to provide a setting to generate and control a Voltage or Temperature (VT) trackable clock.
6. The apparatus of claim 3 , further comprising a first clock distribution network and a second clock distribution network, wherein the first distribution network is to receive the second clock phase, wherein the second distribution network is to receive a third clock phase, and wherein the first, second and third PIs are coupled to a second circuitry, and wherein the second circuitry is to provide skew between first and second clock distribution networks.
7. The apparatus of claim 1 , wherein the first, second, and third clock phases are at least one of: substantially 0, 180, and 270 degree clock phases, respectively; or substantially 0, 90, and 270 degree clock phases, respectively.
8. An apparatus comprising: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, wherein the first PI is to provide a substantially zero clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a substantially 180 degree clock phase; and a calibration logic to select the substantially zero clock phase to sample a first edge of a clock, and to record a first sample; wherein the calibration logic is to select the substantially 180 degree clock phase to sample a second edge of the differential clock and to record a second sample; and wherein the calibration logic is to determine a rotated clock phase based on the first and second samples.
9. The apparatus of claim 8 , wherein the calibration logic is to rotate the substantially zero clock phase from the first PI and find a transition of 0 to 1 for the first sample and to record as code value E1, and wherein the calibration logic is to rotate the substantially 180 degree clock phase from the second PI and find a transition of 1 to 0 for the second sample and record as code value E2.
10. The apparatus of claim 9 , wherein the calibration logic is to determine a substantially 90 degree clock phase with (E1+(E1+E2)*0.5), and wherein the calibration logic is to determine a substantially 270 degree clock phase with (E1−(E1+E2)*0.5).
11. The apparatus of claim 8 , wherein the calibration logic is to rotate the substantially zero clock phase from the first PI and is to find a transition of 1 to 0 for the first sample and to record as code value E1, and wherein the calibration logic is to rotate the substantially 180 degree clock phase from the second PI and find a transition of 0 to 1 for the second sample and record as code value E2.
12. The apparatus of claim 8 , further comprising a third PI coupled to the DLL, wherein the third PI is to provide a substantially 270 degree clock phase.
13. The apparatus of claim 12 , wherein the first, second and third PIs are coupled respectively to a first, second and third buffers, wherein the first, second, and third buffers comprise clock trees, and wherein the first, second, and third buffers are used to sample receiver data.
14. The apparatus of claim 12 , wherein the first, second and third PIs are coupled to a PI Finite State Machine (PI-FSM), and wherein the PI-FSM is to provide a setting to generate and control a Voltage or Temperature (VT) trackable clock.
15. The apparatus of claim 12 , wherein the calibration logic is to rotate the substantially 180 degree clock phase from the second PI and find a transition of 1 to 0 for a third sample, and record as code value E3.
16. The apparatus of claim 15 , wherein the calibration logic is to rotate the substantially 270 degree clock phase from the third PI and is to identify a transition of 1 to 0 for a fourth sample, and record as code value E4.
17. The apparatus of claim 16 , wherein the calibration logic is to identify a difference between the code values E3 and E4, wherein the difference is to indicate a skew in the clock.
18. The apparatus of claim 17 , further comprising a PI Offset logic, wherein the PI Offset logic is to apply the E3 and E4 code difference to adjust the clock and to compensate for the skew.
19. A system comprising: a memory; a processor coupled to the memory; and a wireless interface to allow the processor to communicate with another device, wherein the processor comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; and circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.
20. The system of claim 19 , wherein the first PI is an error PI, and wherein the second PI is an even PI.
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July 23, 2019
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