Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An operation method of a memory controller, the method comprising: performing a first decoding operation to a message of an internal region included in a codeword received from a semiconductor memory device by using an internal parity; and performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region, wherein the codeword includes the internal region in a matrix form and the outer parity generated by encoding one or more rows of the internal region, and wherein the performing of the second decoding operation includes: detecting one or more errors of symbols included in the encoded one or more rows of the internal region, to which the first decoding operation is performed, by using the outer parity of the outer region; and flipping values of all symbols included in one or more columns, in which the error-detected symbols are included.
This invention relates to error correction in semiconductor memory systems, specifically improving data reliability by using a two-stage decoding process. The problem addressed is the need for efficient error detection and correction in memory systems where data integrity is critical. The method involves a memory controller that processes a codeword received from a semiconductor memory device. The codeword includes an internal region in matrix form and an outer parity region. The outer parity is generated by encoding one or more rows of the internal region. The first decoding operation corrects errors in the internal region using internal parity. The second decoding operation further refines the corrected internal region by detecting errors in the encoded rows using the outer parity. If errors are found, the method flips the values of all symbols in the columns containing those errors. This two-stage approach enhances error correction accuracy by leveraging both internal and outer parity checks, ensuring higher data reliability in memory operations. The technique is particularly useful in systems where memory errors can lead to significant data corruption, such as in high-density storage or mission-critical applications.
2. The method of claim 1 , further comprising, after the flipping of the values, performing the first decoding operation to the internal region, to which the second decoding operation is performed.
A method for decoding data in a storage system addresses the challenge of efficiently recovering data from storage media, particularly when dealing with error-prone regions. The method involves a two-step decoding process to improve data integrity. First, a second decoding operation is applied to an internal region of the storage medium, which may contain corrupted or unreliable data. After this initial decoding, the values within the internal region are flipped, altering their binary states. Following this inversion, a first decoding operation is performed on the same internal region. This sequential approach—applying a second decoding, flipping values, and then applying a first decoding—enhances error correction by leveraging different decoding techniques or parameters to handle persistent errors. The method is particularly useful in storage systems where data corruption is common, such as in flash memory or other non-volatile storage devices, where traditional single-pass decoding may fail to fully recover data. By combining multiple decoding steps with value inversion, the method improves the likelihood of successful data recovery while maintaining system efficiency.
3. The method of claim 1 , wherein the second decoding operation is performed through a BCH code.
A system and method for error correction in data storage or transmission systems addresses the challenge of efficiently detecting and correcting errors in received data. The method involves a two-stage decoding process to enhance reliability. First, a primary decoding operation is performed using a low-density parity-check (LDPC) code, which is effective for correcting random errors. If the primary decoding fails, a secondary decoding operation is then performed using a Bose-Chaudhuri-Hocquenghem (BCH) code, which is particularly effective for correcting burst errors. The BCH code is applied to the data that failed the initial LDPC decoding, providing an additional layer of error correction. This hybrid approach improves overall system robustness by leveraging the strengths of both LDPC and BCH codes, ensuring accurate data recovery even in the presence of complex error patterns. The method is applicable in various applications, including wireless communication, solid-state storage, and optical transmission, where error resilience is critical.
4. The method of claim 1 , wherein the first decoding operation is performed through a Tensor Product Code.
A system and method for error correction in quantum computing involves encoding and decoding quantum information using a Tensor Product Code (TPC). Quantum computing faces challenges with maintaining coherence and correcting errors due to decoherence and noise. The method addresses this by applying a TPC-based decoding operation to detect and correct errors in quantum states. The TPC structure allows for efficient error correction by leveraging a grid-like arrangement of qubits, where errors are identified and corrected through syndrome measurements and logical operations. The decoding process involves measuring syndrome qubits to identify error locations and applying corrective operations to restore the original quantum state. The method may also include pre-processing steps such as encoding the quantum information into a TPC structure and post-processing steps to verify the corrected state. The use of TPC provides a scalable and robust error correction mechanism, improving the reliability of quantum computations. The system may include quantum hardware components such as qubits, control circuits, and measurement devices to implement the encoding and decoding operations. The method is applicable to various quantum computing architectures, including superconducting qubits, trapped ions, and topological qubits, enhancing their fault tolerance and computational accuracy.
5. The method of claim 4 , wherein the performing of the first decoding operation includes: generating a phantom syndrome message for the internal region using a parity check matrix of a first constituent code of the Tensor Product Code; error correcting the phantom syndrome message by using a parity check matrix of a second constituent code of the Tensor Product Code; and error correcting the internal region by using a difference value between the phantom syndrome message and the error-corrected phantom syndrome message.
This invention relates to error correction in data storage systems, specifically improving the reliability of data encoded using Tensor Product Codes (TPCs). TPCs are a class of error-correcting codes that combine two constituent codes to achieve high error correction capabilities, but existing methods may struggle with certain error patterns, particularly in high-density storage media where errors can cluster. The method addresses this by refining the decoding process for internal regions of the TPC. First, a phantom syndrome message is generated for the internal region using the parity check matrix of the first constituent code. This syndrome represents potential errors without directly correcting them. Next, the phantom syndrome is error-corrected using the parity check matrix of the second constituent code, which helps resolve discrepancies caused by the first decoding step. Finally, the internal region is corrected by applying the difference between the original and error-corrected phantom syndrome messages. This approach enhances error detection and correction by leveraging the interplay between the two constituent codes, improving reliability in systems where traditional TPC decoding may fail. The method is particularly useful in high-error-rate environments, such as solid-state drives or optical storage, where conventional error correction may not suffice. By iteratively refining the syndrome information, it ensures more accurate data recovery without requiring additional redundancy.
6. The method of claim 5 , wherein the first constituent code is a repetition code.
A method for encoding data using error-correcting codes, specifically employing a repetition code as the first constituent code in a concatenated coding scheme. The technique addresses the challenge of improving data reliability in noisy communication channels by combining multiple error-correcting codes to enhance error detection and correction capabilities. The repetition code, which replicates each data bit multiple times to increase redundancy, is used as the inner code in a layered coding structure. This inner code is followed by an outer code, which may be a different type of error-correcting code such as a Reed-Solomon or convolutional code, to further strengthen error correction. The concatenated approach leverages the strengths of both codes, where the repetition code provides robust error detection, and the outer code refines correction. This method is particularly useful in applications requiring high reliability, such as satellite communications, deep-space transmissions, or storage systems where data integrity is critical. The use of a repetition code as the first constituent ensures that even severe noise or interference can be mitigated, as the repeated bits allow for majority voting or other decoding techniques to recover the original data. The outer code then corrects any remaining errors, providing an additional layer of protection. This technique improves overall system performance by reducing the bit error rate and enhancing data transmission accuracy.
7. The method of claim 5 , wherein the second constituent code is a Reed-Solomon code.
A method for encoding data using error-correcting codes, particularly for improving data reliability in storage or transmission systems. The method addresses the challenge of detecting and correcting errors that may occur during data handling, ensuring data integrity. The process involves encoding data using a primary error-correcting code, such as a low-density parity-check (LDPC) code, to generate a first set of encoded data. This encoded data is then further encoded using a secondary error-correcting code, specifically a Reed-Solomon code, to produce a second set of encoded data. Reed-Solomon codes are well-suited for correcting burst errors, making them effective for applications where data corruption occurs in clusters. The combined encoding approach enhances error correction capabilities, allowing the system to detect and correct a broader range of errors, including both random and burst errors. This dual-layer encoding method is particularly useful in high-reliability systems, such as data storage devices, communication networks, and digital broadcasting, where maintaining data integrity is critical. The use of Reed-Solomon codes in the secondary encoding step ensures robust error correction, complementing the primary encoding method.
8. A memory controller comprising: a first decoder suitable for performing a first decoding operation to a message of an internal region by using an internal parity; and a second decoder suitable for performing a second decoding operation to the internal region, to which the first decoding operation is performed, by using an outer parity of an outer region, wherein the internal region and the outer region are included in a codeword received from a semiconductor memory device, wherein the codeword includes the internal region in a matrix form and the outer parity generated by encoding one or more rows of the internal region, wherein the second decoder detects one or more errors of symbols included in the encoded one or more rows of the internal region, to which the first decoding operation is performed, by using the outer parity of the outer region, and wherein the second decoder flips values of all symbols included in one or more columns, in which the error-detected symbols are included.
This invention relates to error correction in memory systems, specifically a memory controller designed to improve data integrity in semiconductor memory devices. The problem addressed is the detection and correction of errors in data stored in memory, particularly in systems where data is organized into codewords comprising internal and outer regions. The internal region is structured as a matrix, and the outer region contains parity information generated by encoding one or more rows of the internal region. The memory controller includes a first decoder that performs an initial decoding operation on the internal region using internal parity. A second decoder then performs a subsequent decoding operation on the internal region, which has already undergone the first decoding, using the outer parity from the outer region. The second decoder detects errors in symbols within the encoded rows of the internal region by leveraging the outer parity. Upon detecting errors, the second decoder corrects them by flipping the values of all symbols in the columns containing the error-detected symbols. This two-stage decoding process enhances error correction efficiency by combining internal and outer parity checks, ensuring higher data reliability in memory operations. The system is particularly useful in memory devices where data integrity is critical, such as in high-performance computing or storage applications.
9. The memory controller of claim 8 , wherein, after the second decoder flips the values, the first decoder further performs the first decoding operation to the internal region, to which the second decoding operation is performed.
Technical Summary: This invention relates to memory controllers designed to improve data reliability and error correction in memory systems. The problem addressed is the need for efficient error correction in memory storage, particularly when dealing with multi-level cell (MLC) or other advanced memory technologies where data integrity is critical. The memory controller includes a first decoder and a second decoder. The first decoder performs a first decoding operation on an internal region of memory to detect and correct errors. The second decoder performs a second decoding operation on the same internal region, flipping the values of the data before the first decoder performs the decoding operation again. This iterative process enhances error correction by leveraging different decoding strategies. The second decoder may use a different error correction algorithm or parameter set than the first decoder, allowing for more robust error handling. The repeated application of the first decoder after value flipping improves the likelihood of successful error correction, particularly in cases where initial decoding attempts fail. The invention is particularly useful in memory systems where data integrity is paramount, such as in solid-state drives (SSDs), enterprise storage, or other high-reliability applications. By combining multiple decoding operations with value flipping, the memory controller achieves higher error correction rates while maintaining efficient operation.
10. The memory controller of claim 8 , wherein the second decoding operation is performed through a BCH code.
A memory controller is designed to improve error detection and correction in memory systems, particularly for non-volatile memory such as flash storage. The controller includes a decoding system that performs a first decoding operation to detect and correct errors in data read from memory. If the first operation fails to fully correct the errors, a second decoding operation is performed using a different error correction code (ECC) to further refine the data. The second decoding operation employs a BCH (Bose-Chaudhuri-Hocquenghem) code, which is a type of ECC known for its ability to detect and correct multiple-bit errors. The BCH code is applied to the data that was partially corrected by the first decoding operation, ensuring higher reliability and data integrity. This dual-decoding approach enhances error correction efficiency, reducing the likelihood of uncorrectable errors and improving overall system performance. The memory controller is particularly useful in applications where data integrity is critical, such as enterprise storage systems, automotive memory, and industrial embedded systems. The use of BCH coding in the second decoding stage provides a robust solution for handling complex error patterns that may arise in memory storage.
11. The memory controller of claim 8 , wherein the first decoding operation is performed through a Tensor Product Code.
A memory controller is designed to improve error correction in memory systems, particularly for high-density storage media where data integrity is critical. The controller includes a decoding module that performs error correction using a Tensor Product Code (TPC), a type of error-correcting code that combines two or more simpler codes to enhance reliability. The TPC decoding operation is applied to data read from memory to detect and correct errors, ensuring accurate data retrieval even in the presence of noise or defects. The controller may also include additional decoding operations, such as low-density parity-check (LDPC) decoding, to further improve error correction performance. The system is particularly useful in storage applications where traditional error correction methods may fail due to increasing error rates in advanced memory technologies. The use of TPC decoding allows for efficient error correction with reduced computational overhead, making it suitable for high-speed memory systems. The controller may be integrated into solid-state drives, DRAM, or other memory devices to enhance data reliability.
12. The memory controller of claim 11 , wherein the first decoder generates a phantom syndrome message for the internal region using a parity check matrix of a first constituent code of the Tensor Product Code, wherein the first decoder error-corrects the phantom syndrome message by using a parity check matrix of a second constituent code of the Tensor Product Code, and wherein the first decoder error-corrects the internal region by using a difference value between the phantom syndrome message and the error-corrected phantom syndrome message.
This invention relates to memory controllers that implement error correction using Tensor Product Codes (TPCs). TPCs are a class of error-correcting codes that combine two or more simpler constituent codes to achieve high error correction capabilities. The problem addressed is improving error correction efficiency in memory systems, particularly for internal regions of memory where errors may occur. The memory controller includes a first decoder that processes an internal region of memory data. The decoder generates a phantom syndrome message for this internal region using a parity check matrix of a first constituent code of the TPC. The phantom syndrome message is an intermediate representation that helps identify errors. The decoder then error-corrects this phantom syndrome message by applying a parity check matrix of a second constituent code of the TPC. Finally, the decoder corrects errors in the internal region itself by computing the difference between the original phantom syndrome message and the error-corrected version. This approach leverages the structure of TPCs to efficiently isolate and correct errors in memory data. The method improves error correction by decoupling the error detection and correction steps, allowing for more efficient processing of memory errors. The use of TPCs provides robust error correction while minimizing computational overhead, making it suitable for high-reliability memory systems.
13. The memory controller of claim 12 , wherein the first constituent code is a repetition code.
A memory controller is designed to improve data reliability in memory systems, particularly in environments prone to errors such as radiation-induced bit flips. The controller encodes data using error-correcting codes (ECC) to detect and correct errors during read and write operations. The encoding process involves generating a first constituent code and a second constituent code from the original data. The first constituent code is a repetition code, which replicates data bits multiple times to enhance error detection. The second constituent code is a parity code, which generates parity bits based on the original data and the first constituent code. The combined codes are stored in memory, and during retrieval, the controller decodes the data by cross-checking the repetition and parity codes to identify and correct errors. This dual-code approach improves fault tolerance, making the system suitable for applications requiring high reliability, such as aerospace, automotive, and industrial systems. The controller dynamically adjusts the encoding strength based on error rates, optimizing performance and storage efficiency. The system ensures data integrity without requiring redundant memory storage, reducing cost and complexity.
14. The memory controller of claim 12 , wherein the second constituent code is a Reed-Solomon code.
A memory controller is designed to enhance data integrity in storage systems by implementing error correction techniques. The controller includes a first constituent code for initial error detection and correction, and a second constituent code for additional error correction. The second constituent code is specifically a Reed-Solomon code, which is a well-known error-correcting code capable of detecting and correcting multiple random errors and burst errors in data. The memory controller processes data by encoding it with the first constituent code and then applying the Reed-Solomon code as the second layer of protection. During data retrieval, the controller decodes the data using the Reed-Solomon code first to correct errors, followed by the first constituent code for further refinement. This layered approach improves overall data reliability, particularly in systems where data corruption is a concern, such as in solid-state drives or other high-density storage devices. The use of Reed-Solomon coding ensures robust error correction, making the system more resilient to data degradation over time.
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August 27, 2019
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