Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A computer program product for facilitating processing in a computing environment, said computer program product comprising: a computer readable storage medium readable by a processing circuit and storing instructions to perform a method comprising: obtaining a clock comparator sign control to be used to determine whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation; using the clock comparator sign control in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized, wherein the using the clock comparator sign control in the comparison results in correctly indicating whether the selected action is to be recognized, regardless of whether the time-of-day clock has overflowed; and performing, by a processor, based on the comparison, the selected action.
This invention relates to computer systems and addresses the problem of accurately determining whether a specific action should be recognized, even when a time-of-day clock experiences an overflow. The computer program product includes instructions stored on a computer-readable medium. These instructions guide a processing circuit to perform a method. The method begins by obtaining a "clock comparator sign control." This control dictates whether unsigned or signed arithmetic should be used for comparisons. The core of the invention involves using this clock comparator sign control during a comparison. This comparison involves a value from a clock comparator and at least a portion of a value from a time-of-day clock. The purpose of this comparison is to determine if a "selected action" should be recognized. Crucially, the use of the clock comparator sign control ensures that the comparison correctly indicates whether the selected action should be recognized, irrespective of whether the time-of-day clock has overflowed. Finally, a processor performs the selected action based on the outcome of this comparison.
2. The computer program product of claim 1 , wherein based on the clock comparator sign control being set to a first value, unsigned binary arithmetic is to be used in the comparison, the first value being a default value to provide compatibility for operating systems at various levels.
This invention relates to a computer program product for performing clock comparisons in computing systems, particularly addressing compatibility issues across different operating systems. The system includes a clock comparator with a sign control feature that determines whether signed or unsigned binary arithmetic is used during comparisons. When the sign control is set to a first (default) value, the comparator performs unsigned binary arithmetic, ensuring compatibility with operating systems at various levels. This default setting prevents errors that may arise from signed arithmetic operations, which can produce incorrect results when handling certain clock values. The comparator may also include additional logic to handle overflow conditions, ensuring accurate comparisons even when clock values exceed expected ranges. The system is designed to integrate seamlessly into existing computing architectures, providing reliable time-based operations without requiring modifications to the underlying operating system. This approach simplifies system design and reduces the risk of compatibility issues across different software environments.
3. The computer program product of claim 2 , wherein based on the clock comparator sign control being set to a second value, signed binary arithmetic is to be used in the comparison.
This invention relates to a computer program product for performing arithmetic comparisons in digital systems, specifically addressing the need for efficient and flexible signed binary arithmetic operations. The system includes a clock comparator with a sign control mechanism that dynamically selects between signed and unsigned arithmetic modes. When the sign control is set to a second value, the comparator performs signed binary arithmetic, enabling accurate comparisons of negative and positive numbers. The comparator includes a clock signal input, a reference signal input, and a sign control input that determines the arithmetic mode. The system also includes a phase detector that generates an output based on the comparison, which can be used for synchronization or error detection. The invention improves computational efficiency by avoiding redundant operations and ensures accurate results in applications requiring signed arithmetic, such as digital signal processing and microcontroller operations. The dynamic selection of arithmetic modes allows the system to adapt to different computational requirements without hardware modifications.
4. The computer program product of claim 1 , wherein the selected action is an interruption of processing within the computing environment.
A system and method for managing processing interruptions in a computing environment. The computing environment includes multiple processing units that execute tasks, and a monitoring system tracks the performance and resource usage of these tasks. The system identifies when a task is consuming excessive resources or causing performance degradation, then selects an appropriate action to mitigate the issue. One such action is interrupting the processing of the task to prevent further resource depletion or system instability. The interruption can be temporary or permanent, depending on the severity of the detected problem. The system may also log the interruption event for further analysis and adjust future processing strategies to avoid similar issues. This approach ensures efficient resource allocation and maintains system stability by dynamically responding to processing anomalies. The interruption mechanism can be integrated with other system management functions, such as task scheduling or load balancing, to optimize overall performance. The solution is particularly useful in high-performance computing environments where resource contention and task prioritization are critical.
5. The computer program product of claim 1 , wherein the clock comparator is one size and the time-of-day clock is an extended time-of-day clock of a different size than the clock comparator, and wherein the time-of-day clock may overflow.
This invention relates to a computer program product for managing clock synchronization in computing systems, particularly addressing discrepancies between clock sizes in different components. The system includes a clock comparator and a time-of-day clock, where the comparator is of one size (e.g., a smaller bit width) and the time-of-day clock is an extended time-of-day clock of a different size (e.g., a larger bit width). The time-of-day clock may overflow due to its extended size, which could lead to synchronization errors if not properly handled. The system ensures accurate timekeeping by comparing the time-of-day clock with the clock comparator, accounting for potential overflow conditions. This allows the system to maintain precise time synchronization even when the clocks have different bit widths and the larger clock may exceed its maximum value. The invention is particularly useful in systems where different clock components have varying sizes, ensuring reliable time management without data loss or synchronization failures. The solution prevents errors that could arise from overflow in the extended time-of-day clock by implementing a robust comparison mechanism that adapts to the differing clock sizes.
6. The computer program product of claim 1 , wherein the clock comparator sign control is located in a control register.
A system for managing clock signals in digital circuits includes a clock comparator that generates a control signal based on a comparison between two clock signals. The control signal determines the direction of data flow in a bidirectional data bus. The system also includes a control register that stores configuration settings for the clock comparator, including a sign control bit that determines whether the comparator output is inverted or non-inverted. This allows dynamic adjustment of the comparator's behavior without modifying the comparator's hardware design. The control register may also include additional configuration settings, such as enable/disable flags or threshold values, to further customize the comparator's operation. The system ensures proper synchronization between clock domains by dynamically adjusting the comparator's output based on the stored configuration in the control register, improving reliability in mixed-signal or multi-clock environments. The invention addresses synchronization issues in digital circuits where multiple clock domains interact, ensuring correct data transfer and reducing timing errors.
7. The computer program product of claim 1 , wherein the clock comparator is implemented as a clock comparator register and the time-of-day clock is implemented as a time-of-day clock register.
This invention relates to computer systems and specifically addresses the synchronization and comparison of clock signals within a computing environment. The problem being solved involves accurately tracking and comparing time across different components or processes in a computer system, which is critical for tasks such as scheduling, synchronization, and debugging. The invention describes a system where a clock comparator and a time-of-day clock are implemented as registers within a computer system. The clock comparator register is used to compare time values, while the time-of-day clock register provides a reference time. These registers enable precise timekeeping and synchronization by allowing the system to compare current time values against stored or reference times. The use of registers ensures low-latency access to time data, which is essential for real-time applications. The system may also include additional registers or logic to support time adjustments, such as compensating for clock drift or aligning clocks across distributed systems. The invention improves time accuracy and reliability in computing environments where precise timing is required.
8. The computer program product of claim 1 , wherein the method further comprises using the clock comparator sign control to specify what constitutes a discontinuity in a compared portion of the time-of-day clock.
This invention relates to computer systems and methods for managing time-of-day clock synchronization, particularly in environments where clock discontinuities must be detected and handled. The problem addressed is ensuring accurate time synchronization in distributed systems where clock signals may experience disruptions or irregularities, which can lead to errors in time-dependent operations. The invention involves a computer program product that includes a clock comparator sign control mechanism. This mechanism is used to define and detect discontinuities in a time-of-day clock signal. The system compares portions of the clock signal to identify deviations or irregularities that exceed predefined thresholds, which are then classified as discontinuities. The clock comparator sign control allows for customization of what constitutes a discontinuity, enabling adaptive detection based on system requirements or environmental conditions. The method further includes steps for analyzing the clock signal, comparing it against reference values, and applying the sign control to determine whether a discontinuity has occurred. This ensures that time synchronization remains reliable even in the presence of noise, drift, or other disturbances. The invention is particularly useful in high-precision applications where accurate timekeeping is critical, such as financial transactions, scientific measurements, or distributed computing systems. By dynamically adjusting the criteria for discontinuity detection, the system can maintain synchronization without false positives or missed errors.
9. A computer system for facilitating processing in a computing environment, said computer system comprising: a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising: obtaining a clock comparator sign control to be used to determine whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation; using the clock comparator sign control in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized, wherein the using the clock comparator sign control in the comparison results in correctly indicating whether the selected action is to be recognized, regardless of whether the time-of-day clock has overflowed; and performing, by the processor, based on the comparison, the selected action.
This invention relates to a computer system designed to handle time-based comparisons in computing environments, particularly addressing challenges related to clock overflow in time-of-day clocks. The system includes a memory and a processor that work together to perform time-based comparisons while accounting for potential overflow conditions in the time-of-day clock. The key innovation involves using a clock comparator sign control to determine whether unsigned or signed arithmetic should be applied during the comparison of a clock comparator value and a portion of the time-of-day clock value. This approach ensures accurate recognition of whether a selected action should be triggered, even if the time-of-day clock has overflowed. The system dynamically adjusts the comparison method based on the sign control, preventing errors that could arise from overflow conditions. Once the comparison is made, the processor executes the selected action if the comparison meets the predefined criteria. This solution enhances reliability in time-sensitive operations by mitigating issues caused by clock overflow, ensuring consistent and correct action recognition in computing environments.
10. The computer system of claim 9 , wherein based on the clock comparator sign control being set to a first value, unsigned binary arithmetic is to be used in the comparison, the first value being a default value to provide compatibility for operating systems at various levels.
This invention relates to a computer system with a clock comparator that supports both signed and unsigned binary arithmetic for time comparisons. The system includes a clock comparator circuit that compares two time values, such as timestamps, to determine their relative order. The comparator has a sign control input that determines whether the comparison is performed using signed or unsigned arithmetic. When the sign control is set to a default first value, the comparator defaults to unsigned binary arithmetic, ensuring compatibility with operating systems at different levels. This default setting avoids potential errors in time comparisons when the operating system does not explicitly specify the arithmetic mode. The system may also include additional logic to handle overflow conditions and ensure accurate time comparisons. The invention improves reliability in time-based operations by providing a configurable yet backward-compatible comparison mechanism.
11. The computer system of claim 10 , wherein based on the clock comparator sign control being set to a second value, signed binary arithmetic is to be used in the comparison.
A computer system performs arithmetic comparisons between two binary numbers, supporting both signed and unsigned arithmetic operations. The system includes a clock comparator circuit that generates a sign control signal to determine whether the comparison should be performed using signed or unsigned arithmetic. When the sign control signal is set to a first value, the system performs an unsigned binary comparison, treating the binary numbers as positive values. When the sign control signal is set to a second value, the system performs a signed binary comparison, accounting for negative values represented in two's complement or another signed binary format. The system may include additional logic to handle carry and borrow signals during arithmetic operations, ensuring accurate comparison results. The clock comparator circuit dynamically adjusts the comparison mode based on the sign control signal, allowing flexible use in applications requiring both signed and unsigned arithmetic. This approach optimizes performance by avoiding redundant computations and ensuring correct interpretation of binary numbers in different arithmetic contexts.
12. The computer system of claim 9 , wherein the selected action is an interruption of processing within the computing environment.
Technical Summary: This invention relates to computer systems designed to manage and control processing within a computing environment. The system is particularly concerned with handling situations where certain processing activities need to be interrupted or modified to maintain system stability, security, or performance. The core functionality involves monitoring the computing environment for specific conditions or events that trigger predefined actions. One such action is the interruption of processing, which can be necessary to prevent unauthorized access, mitigate security threats, or resolve system conflicts. The system includes components for detecting anomalies, evaluating their impact, and executing appropriate responses. These responses may include halting specific processes, redirecting computational resources, or enforcing security protocols. The interruption of processing is a critical feature, ensuring that the system can quickly respond to critical events without requiring manual intervention. This automated response mechanism enhances system resilience and reduces downtime. The invention is applicable in environments where real-time processing adjustments are essential, such as cloud computing, enterprise networks, or cybersecurity systems. By proactively managing processing interruptions, the system helps maintain operational continuity and protects against potential disruptions. The overall goal is to provide a robust framework for dynamic processing control in complex computing environments.
13. The computer system of claim 9 , wherein the clock comparator is one size and the time-of-day clock is an extended time-of-day clock of a different size than the clock comparator, and wherein the time-of-day clock may overflow.
A computer system includes a clock comparator and a time-of-day clock, where the clock comparator is of one size and the time-of-day clock is an extended time-of-day clock of a different size. The time-of-day clock is capable of overflowing, allowing it to handle larger time values than the clock comparator. The system is designed to manage timekeeping in computing environments where precise time measurement is required, particularly in scenarios where the time-of-day clock may exceed the capacity of the clock comparator. The extended time-of-day clock ensures accurate time tracking even when the clock comparator cannot represent the full range of time values, preventing errors in time-based operations. This design is useful in systems where time synchronization, event scheduling, or time-based security mechanisms rely on accurate and extended time representations. The system may include additional components to handle overflow conditions and ensure seamless timekeeping across different clock sizes.
14. The computer system of claim 9 , wherein the method further comprises using the clock comparator sign control to specify what constitutes a discontinuity in a compared portion of the time-of-day clock.
A computer system is described that includes a clock comparator for comparing a time-of-day clock with a reference clock to detect discontinuities. The system uses a clock comparator sign control to define what constitutes a discontinuity in the compared portion of the time-of-day clock. The clock comparator generates a comparison result indicating whether the time-of-day clock is ahead or behind the reference clock. The system also includes a clock comparator control that enables or disables the clock comparator based on a comparison enable signal. The clock comparator sign control allows the system to customize the criteria for identifying discontinuities, such as detecting when the time-of-day clock deviates from the reference clock by a specified threshold. This ensures accurate time synchronization and error detection in computing environments where precise timing is critical, such as in distributed systems, financial transactions, or real-time applications. The system may also include a clock comparator output that provides the comparison result to other components for further processing or error handling. The clock comparator control ensures that the comparison process can be selectively activated or deactivated as needed, improving efficiency and reducing unnecessary computations.
15. A computer-implemented method of facilitating processing in a computing environment, said computer-implemented method comprising: obtaining, by a processor, a clock comparator sign control to be used to determine whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation; using the clock comparator sign control in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized, wherein the using the clock comparator sign control in the comparison results in correctly indicating whether the selected action is to be recognized, regardless of whether the time-of-day clock has overflowed; and performing, by the processor, based on the comparison, the selected action.
This invention relates to a computer-implemented method for processing time-based comparisons in a computing environment, particularly addressing challenges in accurately comparing time values when a time-of-day clock overflows. The method involves obtaining a clock comparator sign control that determines whether unsigned or signed arithmetic should be used in a comparison operation. This control is applied when comparing a clock comparator value with at least a portion of a time-of-day clock value to determine whether a selected action should be recognized. The use of the clock comparator sign control ensures correct recognition of the action, even if the time-of-day clock has overflowed. The method then performs the selected action based on the comparison result. This approach prevents errors in time-based decision-making that can occur due to clock overflow, ensuring reliable operation in systems where precise time comparisons are critical. The method is particularly useful in environments where time-based triggers or events must be accurately detected, such as in real-time systems or scheduling applications.
16. The computer-implemented method of claim 15 , wherein based on the clock comparator sign control being set to a first value, unsigned binary arithmetic is to be used in the comparison, the first value being a default value to provide compatibility for operating systems at various levels.
This invention relates to a computer-implemented method for performing clock comparisons in a computing system, particularly addressing compatibility issues across different operating systems. The method involves a clock comparator sign control mechanism that determines the arithmetic mode used for time comparisons. When the sign control is set to a default first value, the system defaults to unsigned binary arithmetic, ensuring compatibility with operating systems at various levels. This approach prevents errors that may arise from signed arithmetic operations when comparing clock values, which can lead to incorrect time calculations or system malfunctions. The method dynamically adjusts the arithmetic mode based on the sign control value, allowing seamless integration with different operating system versions. The system includes a clock comparator circuit that evaluates time values and a control module that sets the arithmetic mode, ensuring accurate and reliable time comparisons regardless of the operating system environment. This solution is particularly useful in embedded systems, real-time operating systems, and other applications where precise timekeeping and compatibility are critical.
17. The computer-implemented method of claim 16 , wherein based on the clock comparator sign control being set to a second value, signed binary arithmetic is to be used in the comparison.
This invention relates to a computer-implemented method for performing comparisons in digital systems, particularly focusing on signed binary arithmetic operations. The method addresses the challenge of efficiently handling signed numerical comparisons in digital circuits, where traditional comparators may not inherently support signed arithmetic without additional logic or processing steps. The method involves a clock comparator sign control mechanism that dynamically adjusts the comparison operation based on a configurable setting. When the sign control is set to a second value, the system is configured to perform signed binary arithmetic during the comparison process. This ensures accurate evaluation of signed numbers, including negative values, by applying the appropriate arithmetic rules for signed binary representations. The method integrates with a broader system that may include clock synchronization or timing-related operations, where precise signed comparisons are necessary for correct functionality. The invention improves upon prior art by providing a flexible, software-configurable approach to signed comparisons, reducing the need for dedicated hardware modifications or complex pre-processing steps. This enhances efficiency and adaptability in digital systems requiring both signed and unsigned arithmetic operations. The method is particularly useful in applications such as digital signal processing, real-time control systems, and other domains where signed numerical comparisons are critical.
18. The computer-implemented method of claim 15 , wherein the clock comparator is one size and the time-of-day clock is an extended time-of-day clock of a different size than the clock comparator, and wherein the time-of-day clock may overflow.
The invention relates to a computer-implemented method for managing clock synchronization in systems where a time-of-day clock and a clock comparator have different sizes. The problem addressed is ensuring accurate timekeeping and comparison operations when the time-of-day clock is an extended clock that can overflow, while the clock comparator is of a different size. The method involves handling the overflow of the time-of-day clock to maintain correct time comparisons. The time-of-day clock is designed to track time over longer periods, potentially exceeding the maximum value of the clock comparator. The system ensures that time comparisons remain valid despite the size mismatch and overflow conditions. The method may include steps to adjust or normalize time values between the two clocks to prevent errors in time-based operations. This approach is particularly useful in embedded systems or real-time applications where precise timekeeping and synchronization are critical, and hardware constraints limit the size of the clock comparator. The invention ensures reliable time comparisons even when the time-of-day clock exceeds the comparator's capacity.
19. The computer-implemented method of claim 15 , wherein the selected action is an interruption of processing within the computing environment.
This invention relates to managing processing interruptions in a computing environment. The problem addressed is the need to efficiently handle and mitigate disruptions in computing systems, such as those caused by software errors, hardware failures, or external events, to maintain system stability and performance. The method involves monitoring the computing environment for conditions that may require an interruption of processing. When such a condition is detected, the system evaluates the current state of the environment to determine the appropriate action. The selected action is an interruption of processing, which may include halting specific processes, pausing operations, or redirecting computational resources to mitigate the disruption. The interruption is designed to prevent further degradation of system performance or data integrity. The method also includes analyzing the cause of the interruption to identify potential improvements in system resilience. This may involve adjusting system parameters, updating software, or implementing additional safeguards to reduce the likelihood of similar interruptions in the future. The system may also log the interruption event for further analysis and reporting. The interruption process is integrated with the broader computing environment, ensuring that it does not inadvertently cause additional disruptions. The method may also include notifying system administrators or automated recovery systems to facilitate a swift response to the interruption. The goal is to minimize downtime and maintain system reliability while addressing the underlying issue.
20. The computer-implemented method of claim 15 , further comprising using the clock comparator sign control to specify what constitutes a discontinuity in a compared portion of the time-of-day clock.
This invention relates to time synchronization in computer systems, specifically addressing the challenge of detecting and managing discontinuities in time-of-day clocks. The method involves comparing two time-of-day clocks to identify discrepancies, such as jumps or resets, which can disrupt system operations. A clock comparator generates a sign control signal that determines whether a detected difference between the clocks qualifies as a discontinuity. This sign control can be configured to define thresholds or conditions under which a discontinuity is flagged, ensuring accurate time synchronization. The system may also include a clock comparator that outputs a comparison result indicating the relationship between the two clocks, such as whether one is ahead or behind the other. The method further allows for adjusting the time-of-day clock based on the comparison to correct discrepancies. This approach helps maintain precise timekeeping in distributed systems, preventing errors in time-sensitive applications. The invention is particularly useful in environments where time synchronization is critical, such as financial transactions, network protocols, or real-time data processing.
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September 24, 2019
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