Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An error detection device, comprising: circuitry configured to: generate error detection information when writing write-data which is targeted to write in a storage unit, the storage unit being configured to store data including pieces of division-data which has a read-data size smaller than a write-data size, the error detection information being information which is associated with each piece of division-data and available in determining whether there is a bit error in the division-data, pieces of the error detection information associated with each piece of division-data in the write-data being collectively used in detecting a position of the bit error; when reading the division-data from the storage unit, determine whether there is the bit error in the division-data by using the error detection information associated with the division-data being a target to read; and when determining that there is the bit error, detect the position of the bit error by collectively using the pieces of the error detection information associated with each piece of division-data of the write-data including the division-data having the bit error, and correct the bit error based on information on the position of the bit error so that the storage unit restrains deterioration in storage density that is caused by using the error detection information when the read-data size and the write-data size are different from each other, wherein the error detection information includes first error detection information associated with first division-data among the division-data and second error detection information associated with second division-data immediately preceded by the first division-data among the division-data, the first error detection information is generated by calculating exclusive OR of an odd number of bits of the first error detection information and an even number of bits of the second error detection information, and the second error detection information is generated by calculating exclusive OR of an even number of bits of the first error detection information and an odd number of bits of the second error detection information.
This invention relates to an error detection device for storage systems where write-data is divided into smaller read-data units. The problem addressed is maintaining high storage density while detecting and correcting bit errors in systems where the read-data size differs from the write-data size. The device generates error detection information for each division-data unit within the write-data, allowing bit error detection and correction without reducing storage density. The circuitry generates error detection information during write operations, associating it with each division-data piece. This information enables bit error detection when reading data. If an error is found, the device uses the collective error detection information from the entire write-data to locate the error position and correct it. The error detection information is structured with first and second types: the first is generated by XORing an odd number of bits from the first error detection information with an even number of bits from the second, and the second is generated by XORing an even number of bits from the first with an odd number of bits from the second. This approach ensures efficient error detection and correction while preserving storage density.
2. The error detection device according to claim 1 , wherein the error detection information is a code which is generated based on an Error Correcting Code (ECC) method.
The invention relates to an error detection device designed to identify errors in data transmission or storage systems. The device generates error detection information, specifically a code, using an Error Correcting Code (ECC) method. ECC is a technique that not only detects errors in transmitted or stored data but also allows for the correction of certain types of errors. The device applies this method to ensure data integrity by generating a code that can be used to verify the accuracy of the data. When data is transmitted or retrieved, the device compares the generated code with a reference code to detect discrepancies, indicating potential errors. If an error is detected, the ECC method may also correct the error, depending on the severity and type of corruption. This approach enhances reliability in systems where data accuracy is critical, such as in communication networks, storage devices, and memory systems. The use of ECC ensures that even if errors occur during transmission or storage, they can be identified and, in many cases, corrected, thereby maintaining data integrity.
3. A storage apparatus, comprising: a storage unit that stores data including pieces of division-data which has a read-data size smaller than a write-data size; and an error detection device including circuitry, the circuitry being configured to: generate error detection information when writing write-data which is targeted to write in the storage unit, the error detection information being information which is associated with each piece of division-data and available in determining whether there is a bit error in the division-data, pieces of the error detection information associated with each piece of division-data in the write-data being collectively used in detecting a position of the bit error, when reading the division-data from the storage unit, determine whether there is the bit error in the division-data by using the error detection information associated with the division-data being targeted to read, and when determining that there is the bit error, detect the position of the bit error by collectively using the pieces of the error detection information associated with each piece of division-data of the write-data including the division-data having the bit error, and correct the bit error based on information on the position of the bit error so that the storage apparatus restrains deterioration in storage density that is caused by using the error detection information when the read-data size and the write-data size are different from each other, wherein the error detection information includes first error detection information associated with first division-data among the division-data and second error detection information associated with second division-data immediately preceded by the first division-data among the division-data, the first error detection information is generated by calculating exclusive OR of an odd number of bits of the first error detection information and an even number of bits of the second error detection information, and the second error detection information is generated by calculating exclusive OR of an even number of bits of the first error detection information and an odd number of bits of the second error detection information.
The invention relates to a storage apparatus designed to improve data integrity and storage efficiency when handling data with different read and write sizes. The apparatus includes a storage unit that stores data divided into smaller pieces, where each piece has a read-data size smaller than the write-data size. An error detection device with specialized circuitry generates error detection information during write operations. This information is associated with each piece of division-data and helps determine bit errors. When reading data, the device checks for bit errors using the associated error detection information. If an error is found, the device detects the exact bit position by analyzing the error detection information from multiple pieces of division-data and corrects the error accordingly. This approach prevents storage density loss that would otherwise occur due to mismatched read and write sizes. The error detection information is structured using a unique method: first error detection information for a given piece of data is generated by XORing an odd number of bits from its own data with an even number of bits from the preceding piece's data. Conversely, the second error detection information for the preceding piece is generated by XORing an even number of bits from its own data with an odd number of bits from the following piece's data. This interleaved approach enhances error detection accuracy while maintaining storage efficiency.
4. An error correction method, comprising: generating error detection information when writing write-data which is targeted to write in a storage unit, the storage unit being configured to store data including pieces of division-data which has a read-data size smaller than a write-data size, the error detection information being information which is associated with each piece of division-data and available in determining whether there is a bit error in the division-data, pieces of the error detection information associated with each piece of division-data in the write-data being collectively used in detecting a position of the bit error; when reading the division-data from the storage unit, determining whether there is the bit error in the division-data by using the error detection information associated with the division-data being a target to read; and when determining that there is the bit error, detecting the position of the bit error by collectively using the pieces of the error detection information associated with each piece of division-data of the write-data including the division-data having the bit error, and correct the bit error based on information on the position of the bit error so that the storage unit restrains deterioration in storage density that is caused by using the error detection information when the read-data size and the write-data size are different from each other, wherein the error detection information includes first error detection information associated with first division-data among the division-data and second error detection information associated with second division-data immediately preceded by the first division-data among the division-data, the first error detection information is generated by calculating exclusive OR of an odd number of bits of the first error detection information and an even number of bits of the second error detection information, and the second error detection information is generated by calculating exclusive OR of an even number of bits of the first error detection information and an odd number of bits of the second error detection information.
This invention relates to error correction in storage systems where write-data is divided into smaller division-data units for storage, and the read-data size differs from the write-data size. The problem addressed is the deterioration in storage density caused by error detection information when read and write sizes are mismatched. The method generates error detection information for each division-data piece, allowing bit error detection and correction. When reading, the system checks for errors using the associated error detection information. If an error is found, the position is detected by collectively analyzing the error detection information of all division-data pieces from the original write-data. The error is then corrected based on the detected position. The error detection information is structured such that first and second division-data pieces share overlapping bits in their error detection codes. The first error detection information is generated by XORing an odd number of bits from the first division-data with an even number of bits from the second division-data. Similarly, the second error detection information is generated by XORing an even number of bits from the first division-data with an odd number of bits from the second division-data. This approach ensures efficient error correction while minimizing storage overhead.
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September 24, 2019
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