Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A processor system comprising: a first processor configured to generate a first output signal; a second processor configured to perform an identical task to the first processor, and configured to generate a second output signal; and a defect detector configured to compare the first output signal with the second output signal to generate a fault detection signal, wherein the defect detector comprises: a first FIFO buffer configured to receive the first output signal in synchronization with a first driving voltage and a first driving clock, and store the received first output signal; a second FIFO buffer configured to receive the second output signal in synchronization with a second driving voltage and a second driving clock, and store the received second output signal; a level shifter configured to shift, to a level of the first driving voltage, an output from the second FIFO buffer in synchronization with the second driving clock; and an actuator interface configured to provide an actuator driving signal to an actuator; and wherein the defect detector is configured to perform level synchronization or clock domain synchronization on the first output signal and the second output signal.
The invention relates to a processor system designed to detect defects by comparing outputs from redundant processors. The system addresses the need for reliable fault detection in critical applications where processor errors could lead to system failures. The system includes two processors performing identical tasks, generating output signals that are compared to detect discrepancies. A defect detector synchronizes and compares these signals to generate a fault detection signal. The defect detector includes two FIFO buffers that store the output signals from each processor, synchronized with their respective driving voltages and clocks. A level shifter adjusts the output from the second FIFO buffer to match the voltage level of the first processor's driving voltage. The system also includes an actuator interface to provide driving signals to an actuator based on the comparison results. The defect detector ensures proper synchronization between the signals, handling both level and clock domain synchronization to accurately detect faults. This redundancy and synchronization mechanism enhances system reliability by identifying and responding to processor errors in real time.
2. The processor system of claim 1 , wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
A processor system is designed to enhance performance and reliability by utilizing independent power and clock sources for different components. The system includes a first processing unit and a second processing unit, each driven by separate power supply sources and clock generators. The first processing unit operates using a first driving voltage from a first power supply and a first driving clock from a first clock generator. Similarly, the second processing unit operates using a second driving voltage from a second power supply and a second driving clock from a second clock generator. By isolating the power and clock sources, the system reduces interference and improves fault tolerance. This design ensures that disruptions in one power or clock source do not affect the other, enhancing overall system stability and performance. The independent sources allow for optimized power management and clock synchronization, which is particularly useful in high-reliability applications such as data centers, embedded systems, or safety-critical environments. The system may also include additional components like memory controllers or communication interfaces, which may also be powered and clocked independently for further isolation and efficiency.
3. The processor system of claim 1 , wherein the first and second driving clocks are respectively provided from different phase locked loops (PLLs) or different delay locked loops (DLLs).
This invention relates to a processor system designed to mitigate timing skew between clock signals in high-performance computing environments. The problem addressed is the synchronization issues that arise when multiple clock signals are used to drive different components of a processor, leading to timing errors and reduced system reliability. The invention provides a processor system with a first and second driving clock, each generated by separate phase-locked loops (PLLs) or delay-locked loops (DLLs). By using distinct PLLs or DLLs for each clock, the system ensures that phase noise and jitter from one clock source do not affect the other, improving synchronization accuracy. The processor system includes a clock distribution network that delivers these clocks to different components, such as cores, caches, or memory interfaces, while maintaining precise timing relationships. This approach reduces skew between clocks, enhances data integrity, and supports higher operating frequencies. The invention is particularly useful in multi-core processors, high-speed data processing units, and systems requiring low-latency synchronization. The use of independent PLLs or DLLs for each clock allows for dynamic adjustment of clock phases, further optimizing performance and power efficiency.
4. The processor system of claim 1 , wherein, when the first and second output signals are determined to be identical, the defect detector outputs any one of the first and second output signals as the actuator driving signal.
A processor system is designed for defect detection in manufacturing processes, particularly for identifying defects in products or components during production. The system addresses the challenge of accurately detecting defects while minimizing false positives and ensuring reliable operation of downstream actuators. The system includes a defect detector that receives first and second output signals from separate processing paths, each analyzing the same input data to detect defects. The first and second output signals are compared to determine if they are identical. If they are identical, the defect detector outputs one of the first or second output signals as an actuator driving signal to control an actuator, such as a sorting mechanism or rejection system. This ensures that only consistent defect detections trigger the actuator, improving reliability. The system may also include preprocessing steps to enhance the input data before defect detection, such as noise reduction or feature extraction. The comparison of multiple output signals helps mitigate errors from individual processing paths, ensuring higher accuracy in defect detection and actuator control. The actuator driving signal is used to perform actions like rejecting defective products or adjusting production parameters. This approach enhances manufacturing quality control by reducing false activations and ensuring consistent defect detection.
5. The processor system of claim 4 , wherein, when the first and second output signals are determined not to be identical, the defect detector outputs the fault detection signal.
A processor system is designed to detect defects in integrated circuits by comparing output signals from redundant processing units. The system includes at least two processing units configured to perform identical operations on the same input data, generating first and second output signals. A defect detector compares these signals to determine if they match. If the signals are not identical, the defect detector generates a fault detection signal, indicating a potential defect in one of the processing units. This redundancy-based approach enhances reliability by cross-verifying results, which is critical for applications requiring high fault tolerance, such as aerospace, automotive, or medical devices. The system may also include additional processing units to further improve defect detection accuracy. The fault detection signal can trigger corrective actions, such as switching to a backup unit or initiating diagnostic procedures. This method ensures continuous operation even if one processing unit fails, making it suitable for safety-critical systems where unnoticed errors could have severe consequences. The comparison process may involve bitwise or logical checks to ensure precise detection of discrepancies.
6. The processor system of claim 1 , wherein the defect detector comprises a clock domain signal deliverer configured to convert an output of the level shifter to a clock domain of the first driving clock.
A processor system includes a defect detector that identifies defects in a level shifter circuit, which converts signals between different voltage domains. The defect detector monitors the level shifter's output and checks for timing or voltage-related failures. To ensure accurate defect detection, the defect detector includes a clock domain signal deliverer. This component synchronizes the level shifter's output signal to the clock domain of a first driving clock, which is used to control the level shifter's operation. By aligning the signals to the same clock domain, the defect detector can reliably compare the level shifter's output against expected behavior, detecting defects such as signal delays, voltage drops, or incorrect transitions. The system is designed to operate in high-speed or low-power environments where level shifter failures could disrupt processor functionality. The defect detector's synchronization mechanism ensures that timing-related defects are accurately identified, even if the level shifter operates at different voltage levels or frequencies. This improves system reliability by preventing undetected signal integrity issues in voltage domain transitions.
7. The processor system of claim 6 , wherein the defect detector comprises a comparator configured to compare an output from the first FIFO buffer and an output from the clock domain signal deliverer.
This invention relates to processor systems with defect detection mechanisms for clock domain crossing (CDC) circuits. The problem addressed is ensuring reliable data transfer between different clock domains in digital circuits, where mismatched timing can cause data corruption or metastability. The system includes a first-in-first-out (FIFO) buffer to synchronize data between clock domains and a defect detector to identify errors in the transferred data. The defect detector uses a comparator to compare the output from the FIFO buffer with the output from a clock domain signal deliverer, which provides the original or expected signal. If the comparator detects a mismatch, it indicates a defect in the data transfer process. The FIFO buffer temporarily stores data to align it with the receiving clock domain, preventing timing violations. The clock domain signal deliverer ensures the correct signal is available for comparison. This defect detection mechanism enhances reliability in systems where multiple clock domains interact, such as in high-speed digital processors or communication interfaces. The comparator-based approach provides a straightforward method to verify data integrity during clock domain crossings.
8. The processor system of claim 7 , wherein the comparator compares the output from the first FIFO buffer and the output from the clock domain signal deliverer using the first driving clock and the first driving voltage.
This invention relates to a processor system designed to improve signal synchronization and power efficiency in integrated circuits. The system addresses the challenge of accurately comparing signals from different clock domains while minimizing power consumption. A key component is a comparator that evaluates outputs from a first FIFO buffer and a clock domain signal deliverer. The comparator operates using a first driving clock and a first driving voltage, ensuring precise timing alignment between asynchronous signals. The FIFO buffer temporarily stores data to bridge clock domain transitions, while the clock domain signal deliverer generates synchronized signals for comparison. The comparator's operation under specific clock and voltage conditions enhances reliability and reduces power dissipation. This design is particularly useful in high-speed digital circuits where signal integrity and energy efficiency are critical. The system ensures that data transfers between clock domains are accurate and power-efficient, addressing common issues in mixed-signal and multi-domain processor architectures.
9. The processor system of claim 1 , further comprising: an automotive electronic system configured to drive the actuator with reference to a result of comparing the first and second output signals.
10. A fault detecting method for a processor system, which comprises a plurality of processors, the method comprising: receiving a first output signal from a first processor driven by a first driving voltage and a first driving clock; receiving a second output signal from a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor; level-synchronizing the second output signal by converting a voltage level of the second output signal to a voltage level identical to a voltage level of the first driving voltage; clock-synchronizing the second output signal by converting a clock domain of the level-synchronized second output signal to be identical to a clock domain of the first driving clock; and comparing the second output signal with the first output signal to generate a fault detection signal.
This technical summary describes a fault detection method for a processor system comprising multiple processors. The method addresses the challenge of detecting faults in a processor system where multiple processors perform identical tasks but may operate under different voltage and clock conditions. The system includes at least two processors: a first processor driven by a first voltage and clock, and a second processor driven by a second voltage and clock, performing the same task. The method involves receiving output signals from both processors. The second processor's output signal is first level-synchronized by converting its voltage level to match the first processor's driving voltage. The signal is then clock-synchronized by converting its clock domain to match the first processor's driving clock. After synchronization, the second output signal is compared with the first output signal. If discrepancies are detected, a fault detection signal is generated, indicating a potential fault in one of the processors. This method ensures accurate fault detection by aligning the output signals in both voltage and clock domains before comparison, enabling reliable identification of processing errors.
11. The fault detecting method of claim 10 , further comprising: generating the fault detection signal when the first output signal and the level-synchronized and clock-synchronized second output signal are different from each other.
This invention relates to fault detection in electronic systems, specifically for identifying discrepancies between two output signals. The method involves comparing a first output signal with a second output signal that has been synchronized in both level and clock timing. If the two signals differ, a fault detection signal is generated, indicating a potential fault in the system. The synchronization process ensures that any detected differences are due to actual faults rather than timing or level mismatches. This approach is useful in systems where signal integrity is critical, such as in communication networks, control systems, or digital circuits, where accurate fault detection is necessary for maintaining reliability and performance. The method enhances fault detection accuracy by eliminating false positives caused by synchronization issues, thereby improving system diagnostics and maintenance.
12. The fault detecting method of claim 10 , wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.
This invention relates to fault detection in electronic systems, particularly for identifying faults in circuits driven by multiple power supplies and clock sources. The method detects faults by comparing the operational states of a circuit driven by a first power supply and clock with a redundant circuit driven by a second, independent power supply and clock. The independent power and clock sources ensure that a fault in one supply or clock does not affect the other, improving fault detection reliability. The method involves monitoring the outputs of both circuits and comparing them to identify discrepancies, which indicate potential faults in either the circuit, power supply, or clock generator. This approach enhances system robustness by isolating faults to specific components, allowing for targeted maintenance or redundancy activation. The use of independent power and clock sources ensures that a single-point failure in one supply or clock does not compromise the entire fault detection mechanism. This method is particularly useful in safety-critical applications where reliable fault detection is essential.
Unknown
October 1, 2019
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.