Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated circuit comprising: a logic block including logic circuitry and multiple retention-relevant storage devices, the multiple retention-relevant storage devices configured to store first data and second data, the multiple retention-relevant storage devices including: a first group of retention-relevant storage devices, the first group of the retention-relevant storage devices including retention storage devices configured to store the first data and to retain the first data at the retention storage devices during a retention operational mode; and a second group of retention-relevant storage devices configured to store the second data while the logic block is powered for a regular operational mode; a memory block including memory circuitry and configured to maintain memory data in the memory block during the retention operational mode; and retention control circuitry coupled to the logic block and the memory block, the retention control circuitry configured to: migrate, using at least one scan chain formed from the second group of the retention-relevant storage devices, the second data from the second group of the retention-relevant storage devices of the logic block to the memory block for the retention operational mode; and migrate, using the at least one scan chain formed from the second group of the retention-relevant storage devices, the second data from the memory block to the second group of the retention-relevant storage devices for the regular operational mode.
This invention relates to integrated circuits with power management features, specifically addressing data retention during low-power states. The problem solved is maintaining critical data in logic circuitry while minimizing power consumption during inactive periods, such as standby or sleep modes. The integrated circuit includes a logic block with logic circuitry and multiple retention-relevant storage devices. These storage devices are divided into two groups: a first group retains critical first data during a retention operational mode (e.g., when the circuit is in a low-power state), while a second group stores second data during normal operation. The logic block also interfaces with a memory block, which maintains memory data during retention mode. Retention control circuitry manages data migration between the logic block and memory block. When transitioning to retention mode, the control circuitry uses scan chains formed from the second group of storage devices to transfer second data from the logic block to the memory block. Conversely, during a return to regular operation, the control circuitry migrates the second data back from the memory block to the second group of storage devices using the same scan chains. This ensures data integrity while optimizing power efficiency by selectively retaining only essential data in the logic block during low-power states.
2. The integrated circuit of claim 1 , further comprising: a collapsible power domain configured to be powered during the regular operational mode and unpowered during the retention operational mode, the collapsible power domain including the logic block; and an always-on power domain configured to be powered during the regular operational mode and during the retention operational mode, the always-on power domain including the memory block.
This invention relates to integrated circuits designed to manage power consumption in electronic devices, particularly those requiring low-power retention states. The problem addressed is the need to reduce power consumption while maintaining critical data in memory during inactive periods, such as in battery-powered or energy-efficient systems. The integrated circuit includes a collapsible power domain and an always-on power domain. The collapsible power domain contains a logic block and is powered only during regular operation, shutting down during retention mode to conserve energy. The always-on power domain includes a memory block and remains powered in both operational modes, ensuring data retention without active processing. This separation allows the circuit to minimize power usage while preserving essential data, improving efficiency in devices like mobile processors or embedded systems. The design ensures that only necessary components remain active, reducing standby power consumption while maintaining functionality.
3. The integrated circuit of claim 2 , further comprising: power management circuitry configured to power down the collapsible power domain, including the logic block, to cause a power collapse event for the retention operational mode after migration of the second data from the second group of the retention-relevant storage devices of the logic block to the memory block.
This invention relates to integrated circuits with power management features for reducing energy consumption in retention operational modes. The problem addressed is the need to minimize power usage while preserving critical data in storage devices during low-power states. The integrated circuit includes a logic block with retention-relevant storage devices that store data during active operation. A memory block is provided to temporarily store data from these storage devices when the logic block enters a retention mode. The system also includes power management circuitry that initiates a power collapse event, shutting down the collapsible power domain containing the logic block after data migration to the memory block. This ensures data integrity while reducing power consumption. The logic block contains storage devices that retain data during active operation, while the memory block serves as a temporary storage during retention mode. The power management circuitry controls the power-down sequence, ensuring data is safely transferred before the logic block is powered down. This approach allows the integrated circuit to enter a low-power state while preserving critical data, improving energy efficiency without compromising functionality. The invention is particularly useful in battery-powered or energy-sensitive applications where minimizing power consumption is essential.
4. The integrated circuit of claim 1 , further comprising: a collapsible power domain configured to be powered during the regular operational mode and unpowered during the retention operational mode, the collapsible power domain including the logic block, wherein the memory block comprises a non-volatile memory.
This invention relates to integrated circuits with power management features for reducing energy consumption. The circuit includes a logic block and a memory block, where the memory block stores data during both regular operation and a low-power retention mode. The logic block operates during regular operation but is powered down in retention mode to conserve energy. A collapsible power domain encompasses the logic block, allowing it to be selectively powered or unpowered based on the operational mode. The memory block uses non-volatile memory to retain data even when power is removed from the logic block, ensuring data integrity during retention mode. This design enables efficient power management by isolating the logic block from power while preserving critical data in the non-volatile memory, reducing overall energy consumption without data loss. The collapsible power domain dynamically adjusts power distribution to optimize performance and energy efficiency, making the circuit suitable for applications requiring low-power operation while maintaining data retention.
5. The integrated circuit of claim 1 , wherein: the multiple retention-relevant storage devices comprise multiple retention-relevant flip-flops including the second group and the first group; and the first group of the retention-relevant flip-flops includes retention flip-flops configured to retain the first data using a retention mechanism that is local to the retention flip-flops.
This invention relates to integrated circuits with improved data retention capabilities, particularly for flip-flops in low-power or standby modes. The problem addressed is maintaining data integrity in storage devices during power-saving states without relying on external retention mechanisms. The solution involves an integrated circuit with multiple retention-relevant storage devices, specifically flip-flops, divided into at least two groups. The first group consists of retention flip-flops that retain data using a local retention mechanism, meaning the retention functionality is integrated directly within the flip-flops themselves rather than depending on external circuitry. This local retention mechanism ensures data is preserved even when the circuit is in a low-power state, reducing the need for additional power-consuming retention logic. The second group of flip-flops may handle other functions or operate under different retention strategies. The overall design aims to minimize power consumption while maintaining data integrity during standby or sleep modes, making it suitable for energy-efficient electronic devices.
6. The integrated circuit of claim 5 , wherein the first group of the retention flip-flops includes at least one of a live-slave retention flip-flop, a live-master retention flip-flop, or a balloon-latch retention flip-flop.
The invention relates to integrated circuits with retention flip-flops designed to preserve data during power-down states. The technology addresses the challenge of maintaining data integrity in electronic systems when power is interrupted, such as in low-power or standby modes. Retention flip-flops are specialized storage elements that retain their state even when the main power supply is turned off, ensuring critical data is not lost. The integrated circuit includes multiple retention flip-flops organized into distinct groups. The first group of retention flip-flops comprises at least one of three types: a live-slave retention flip-flop, a live-master retention flip-flop, or a balloon-latch retention flip-flop. A live-slave retention flip-flop typically uses a master-slave configuration where the master stage remains active while the slave stage retains data during power-down. A live-master retention flip-flop keeps the master stage active while the slave stage is powered down, ensuring data retention. A balloon-latch retention flip-flop employs a capacitive storage element to hold data when power is off. These designs allow for flexible implementation based on power, area, and performance constraints. The circuit ensures reliable data retention while optimizing power efficiency and circuit complexity.
7. The integrated circuit of claim 5 , wherein the second group of the retention-relevant flip-flops includes flip-flops configured to retain the second data using a retention mechanism that is at least partially remote from the flip-flops and that is based on data migration.
This invention relates to integrated circuits with improved data retention mechanisms, particularly for flip-flops in low-power or standby modes. The problem addressed is maintaining data integrity in flip-flops during power-saving states without excessive power consumption or area overhead. Traditional retention methods often rely on local storage within each flip-flop, which can be inefficient. The integrated circuit includes a first group of flip-flops that retain data locally using conventional methods, and a second group of flip-flops that use a remote retention mechanism based on data migration. In the second group, data is temporarily moved to a remote storage location during low-power states, rather than being stored locally within each flip-flop. This remote storage could be a dedicated retention register, a shared memory, or another storage element outside the flip-flops. The migration process ensures data is preserved when the flip-flops are powered down, reducing leakage current and power consumption. The remote retention mechanism is activated in response to a power-saving signal, and data is restored to the flip-flops when normal operation resumes. This approach minimizes the need for local retention circuitry in each flip-flop, saving area and power while maintaining data integrity. The invention is particularly useful in energy-efficient processors, IoT devices, and other low-power applications where retention power is a critical concern.
8. The integrated circuit of claim 1 , wherein: the retention-relevant storage devices of the first group are configured to implement at least one first functionality for the logic block, with the at least one first functionality having a relatively higher latency sensitivity with respect to transitioning from the retention operational mode to the regular operational mode; and the retention-relevant storage devices of the second group are configured to implement at least one second functionality for the logic block, with the at least one second functionality having a relatively lower latency sensitivity with respect to transitioning from the retention operational mode to the regular operational mode.
An integrated circuit includes multiple retention-relevant storage devices grouped into at least two categories based on their latency sensitivity during mode transitions. The first group of storage devices implements functionalities with higher latency sensitivity, meaning these devices require faster transitions from a retention operational mode to a regular operational mode to avoid performance degradation. The second group implements functionalities with lower latency sensitivity, allowing for slower transitions without significant impact on performance. This grouping enables optimized power management by tailoring transition speeds to the specific needs of different functionalities within the logic block. The retention operational mode conserves power by maintaining data while reducing active power consumption, while the regular operational mode enables full functionality. By differentiating between high and low latency-sensitive storage devices, the circuit balances power efficiency with performance requirements, ensuring critical operations resume quickly while less time-sensitive functions can transition more gradually. This approach is particularly useful in low-power applications where minimizing energy consumption is critical without compromising essential performance metrics.
9. The integrated circuit of claim 8 , wherein: each retention-relevant storage device of the multiple retention-relevant storage devices comprises a storage device configured to store data that is to survive a power collapse by the logic block during the retention operational mode using at least one of a local retention mechanism or a remote retention mechanism; and the at least one first functionality includes at least one of boot functionality for the logic block or phase-locked loop (PLL) functionality for the logic block.
This invention relates to integrated circuits with enhanced power management, specifically addressing the challenge of maintaining critical functionality during power collapse events. The integrated circuit includes a logic block and multiple retention-relevant storage devices designed to preserve data integrity when power is lost. These storage devices employ either local or remote retention mechanisms to ensure data survival during power collapse, allowing the logic block to resume operations without data loss. The retention mechanisms may include on-chip memory buffers, backup power supplies, or external storage interfaces. The invention further specifies that the retained data supports essential functionalities such as boot operations or phase-locked loop (PLL) synchronization for the logic block. By maintaining these critical functions during power interruptions, the integrated circuit ensures reliable system operation and quick recovery. The solution is particularly useful in applications requiring high availability, such as embedded systems, IoT devices, and automotive electronics, where uninterrupted operation is crucial. The retention mechanisms are optimized to minimize power consumption while ensuring data integrity, providing a robust solution for power management in integrated circuits.
10. The integrated circuit of claim 1 , wherein: the retention-relevant storage devices of the second group are configured to be activated into multiple scan chains, including the at least one scan chain; and the retention control circuitry is configured to migrate the second data using the multiple scan chains.
The invention relates to integrated circuits with enhanced data retention capabilities, particularly for systems that must preserve critical data during power-down states. The problem addressed is ensuring reliable data retention in storage devices while minimizing power consumption and maintaining system integrity during low-power or standby modes. The integrated circuit includes a plurality of retention-relevant storage devices divided into at least two groups. The first group is configured to retain data during power-down states, while the second group is used for migrating data between the first group and external storage. The retention control circuitry manages this migration process to ensure data integrity. In this specific embodiment, the storage devices in the second group are configured to form multiple scan chains, including at least one scan chain used for data migration. The retention control circuitry utilizes these multiple scan chains to efficiently transfer data, improving reliability and reducing the risk of data corruption during migration. This approach allows for flexible and scalable data handling, ensuring that critical information is preserved even in low-power conditions. The use of scan chains enables parallel data transfer, enhancing performance and reducing the time required for migration. This solution is particularly useful in applications where power efficiency and data retention are critical, such as in embedded systems, IoT devices, and low-power computing environments.
11. The integrated circuit of claim 10 , wherein the retention control circuitry is configured to organize the retention-relevant storage devices of the second group into a logical grid having multiple rows and multiple columns, each scan chain of the multiple scan chains corresponding to a row of the multiple rows, a scan chain of the multiple scan chains configured to pass second data sequentially from one retention-relevant storage device to a consecutive retention-relevant storage device along the scan chain.
This invention relates to integrated circuits with retention control circuitry for managing storage devices during low-power states. The problem addressed is ensuring data integrity in storage devices when the circuit operates in a low-power mode, where power is reduced to conserve energy but must be restored without data loss. The integrated circuit includes retention control circuitry that organizes retention-relevant storage devices into a logical grid with multiple rows and columns. Each row of the grid corresponds to a scan chain, which is a sequential data path. The scan chains are used to pass data between storage devices in a controlled manner. Specifically, a scan chain passes second data sequentially from one retention-relevant storage device to the next consecutive device along the chain. This organization allows efficient data retention and retrieval during power transitions, ensuring that critical data remains intact when the circuit resumes normal operation. The retention control circuitry may also include additional features, such as grouping storage devices into multiple groups, where a first group is powered during low-power states while a second group is powered down. The second group's data is transferred to the first group before powering down, and restored when power is resumed. This hierarchical approach optimizes power efficiency while maintaining data integrity.
12. The integrated circuit of claim 10 , wherein the retention control circuitry is configured to pump shift pulses into the multiple scan chains to shift the second data out of the multiple scan chains.
The invention relates to integrated circuits with scan testing capabilities, specifically addressing the challenge of efficiently retaining and shifting test data within scan chains during testing operations. Scan testing involves capturing internal states of an integrated circuit by shifting test data through scan chains, but retaining data in the chains while shifting new data can be problematic, particularly in power-constrained or high-speed environments. The integrated circuit includes multiple scan chains and retention control circuitry. The retention control circuitry is designed to pump shift pulses into the scan chains to shift data out of them. This allows for controlled movement of test data through the scan chains while ensuring data integrity and minimizing power consumption. The circuitry may also include features to retain data in the scan chains during idle periods or when shifting is not required, improving test efficiency and reducing test time. The invention enhances scan testing by providing precise control over data retention and shifting, addressing issues like data corruption, power inefficiency, and test time optimization in integrated circuit testing.
13. The integrated circuit of claim 12 , wherein, for a power-down phase to transition from the regular operational mode to the retention operational mode, the retention control circuitry is configured to: collect a portion of the second data from each scan chain of the multiple scan chains; combine the portion of the second data from each scan chain into a data word; and write the data word into the memory block.
The invention relates to integrated circuits with power management features, specifically for transitioning between regular operational and retention modes to conserve power while preserving critical data. The problem addressed is efficiently storing and retrieving data during power-down phases to minimize energy consumption without losing essential information. The integrated circuit includes multiple scan chains for capturing data and a memory block for storing data during retention mode. Retention control circuitry manages the transition process. During power-down, the circuitry collects a portion of data from each scan chain, combines these portions into a single data word, and writes the word into the memory block. This ensures only critical data is retained, reducing storage requirements and power usage. The system also includes a clock control circuit to manage clock signals during transitions, ensuring stable operation. The memory block is designed to retain data with minimal power, and the scan chains can be selectively enabled or disabled to optimize performance. The invention enables efficient power management in integrated circuits by selectively storing and retrieving data during operational mode changes.
14. The integrated circuit of claim 13 , wherein, for a power-up phase to transition from the retention operational mode to the regular operational mode, the retention control circuitry is configured to: read the data word from the memory block, the data word including the portion of the second data collected from each scan chain of the multiple scan chains; and distribute across the multiple scan chains the portion of the second data as read from the memory block.
This invention relates to integrated circuits with scan chain functionality, specifically addressing the challenge of efficiently transitioning between operational modes during power-up. The system includes retention control circuitry that manages data retention and retrieval during transitions between a retention operational mode and a regular operational mode. In the retention mode, data from multiple scan chains is collected and stored in a memory block. During power-up, the retention control circuitry reads the stored data word, which contains portions of the collected data from each scan chain, and redistributes this data across the original scan chains. This ensures that the scan chain data is preserved and accurately restored when transitioning back to the regular operational mode, maintaining system integrity during power state changes. The invention optimizes power management by minimizing data loss and ensuring seamless transitions between operational states.
15. The integrated circuit of claim 13 , wherein the retention control circuitry is configured to: combine the portion of the second data from each scan chain into a data word by incorporating data padding into the data word based on relative lengths of one or more scan chains of the multiple scan chains.
The invention relates to integrated circuits with scan chain testing capabilities, specifically addressing the challenge of efficiently combining test data from multiple scan chains of varying lengths. During integrated circuit testing, scan chains capture test data, but their lengths may differ, leading to misalignment when combining the data. The invention includes retention control circuitry that resolves this by incorporating data padding into a combined data word based on the relative lengths of the scan chains. This ensures proper alignment and integrity of the test data, enabling accurate analysis. The retention control circuitry operates by processing a portion of the second data from each scan chain, adjusting for length discrepancies through padding, and forming a coherent data word. This approach improves test data handling in integrated circuits with heterogeneous scan chain configurations, enhancing diagnostic accuracy and reducing errors in fault detection. The solution is particularly useful in complex integrated circuits where scan chain lengths vary, ensuring reliable test data consolidation for effective testing and debugging.
16. The integrated circuit of claim 1 , wherein the integrated circuit comprises a system on a chip (SOC).
The integrated circuit is designed for use in system-on-chip (SOC) architectures, addressing the need for efficient and compact integration of multiple functional components within a single chip. The SOC includes a processing unit, memory, and peripheral interfaces, all fabricated on a unified substrate to minimize power consumption, reduce latency, and enhance performance. The processing unit may include a central processing unit (CPU), graphics processing unit (GPU), or specialized accelerators tailored for specific tasks such as machine learning or signal processing. The memory subsystem integrates high-speed cache, on-chip SRAM, and interfaces to external DRAM, ensuring low-latency data access. Peripheral interfaces support connectivity with external devices, including high-speed serial links, general-purpose I/O, and specialized interfaces like PCIe or USB. The SOC may also incorporate power management circuits to dynamically adjust voltage and clock frequencies, optimizing energy efficiency. By consolidating these components, the SOC reduces board space, simplifies system design, and improves overall performance while maintaining scalability for various applications, including mobile devices, embedded systems, and data centers.
17. The integrated circuit of claim 16 , wherein the logic block comprises at least one of a microprocessor, a graphics processing unit (GPU), or a modem.
The invention relates to integrated circuits designed for efficient power management in electronic devices. The core problem addressed is optimizing power consumption in integrated circuits that include multiple functional blocks, such as processors, graphics units, or communication modules, to extend battery life and improve performance. The integrated circuit includes a power management system that dynamically adjusts power delivery to different logic blocks based on their operational demands. The logic block, which is a key component of the circuit, may include at least one of a microprocessor, a graphics processing unit (GPU), or a modem. These components are responsible for executing computational tasks, rendering graphics, or handling wireless communication, respectively. The power management system monitors the activity levels of these blocks and allocates power accordingly, ensuring that each block receives sufficient power for its current workload while minimizing unnecessary energy use. By integrating these diverse functional units into a single circuit and employing adaptive power management, the invention enhances energy efficiency and performance in devices such as smartphones, tablets, and wearable electronics. The system ensures that power is distributed intelligently, reducing waste and extending the operational time of battery-powered devices. This approach is particularly beneficial in portable and mobile applications where power conservation is critical.
18. The integrated circuit of claim 1 , wherein the retention storage devices of the first group of the retention-relevant storage devices are configured to store the first data at the retention storage devices during the regular operational mode.
The invention relates to integrated circuits with retention storage devices designed to preserve data during power-saving modes. The problem addressed is maintaining data integrity in low-power states without requiring full system power. The integrated circuit includes multiple retention-relevant storage devices divided into at least two groups. The first group of retention storage devices is specifically configured to store data during regular operational mode, ensuring that critical information remains accessible when the system transitions to a low-power state. The second group of retention storage devices may handle additional data storage or other functions. The circuit also includes a control unit that manages power states and data retention, ensuring seamless transitions between active and low-power modes. The retention storage devices in the first group are optimized to retain data reliably during power-saving operations, preventing data loss while minimizing energy consumption. This design allows the integrated circuit to efficiently balance performance and power efficiency, particularly in battery-powered or energy-sensitive applications. The invention ensures data persistence during power transitions, enhancing reliability in systems requiring frequent power state changes.
19. An integrated circuit comprising: a logic block including logic circuitry and multiple retention-relevant storage devices, the multiple retention-relevant storage devices configured to store first data and second data, the multiple retention-relevant storage devices including: a first group of retention-relevant storage devices, the first group of the retention-relevant storage devices including retention storage devices configured to store the first data during a regular operational mode and to retain the first data at the retention storage devices during a retention operational mode; and a second group of retention-relevant storage devices configured to store the second data while the logic block is powered for the regular operational mode; a memory block including memory circuitry and configured to maintain memory data in the memory block during the retention operational mode; and retention control means for migrating, using at least one scan chain activated from the second group of the retention-relevant storage devices, the second data from the second group of the retention-relevant storage devices of the logic block to the memory block to accommodate a transition from the regular operational mode to the retention operational mode and for migrating, using the at least one scan chain activated from the second group of the retention-relevant storage devices, the second data from the memory block to the second group of the retention-relevant storage devices of the logic block to accommodate a transition from the retention operational mode to the regular operational mode.
This invention relates to integrated circuits designed to manage data retention during power transitions, particularly in systems requiring low-power or standby modes. The problem addressed is the need to preserve critical data in logic blocks when transitioning between active and retention operational modes, ensuring seamless operation without data loss. The integrated circuit includes a logic block with logic circuitry and multiple retention-relevant storage devices. These storage devices are divided into two groups: a first group retains critical first data during both regular and retention modes, while a second group stores second data only during regular operation. A separate memory block maintains memory data during retention mode. The system uses retention control means to migrate second data between the logic block and memory block via at least one scan chain activated from the second group of storage devices. This migration occurs during transitions between operational modes, ensuring data integrity. The scan chain facilitates efficient data transfer, allowing the circuit to switch between active and retention states while preserving all necessary data. This approach minimizes power consumption during standby while maintaining operational continuity.
20. The integrated circuit of claim 19 , wherein: each respective retention storage device of the first group of the retention-relevant storage devices comprises means for retaining a bit of the first data at the respective retention storage device; and each respective retention-relevant storage device of the second group of the retention-relevant storage devices comprises means for storing a bit of the second data at the respective retention-relevant storage device.
This invention relates to integrated circuits with improved data retention capabilities, particularly for systems requiring reliable storage of critical data during power loss or low-power states. The problem addressed is ensuring data integrity in volatile memory systems where power interruptions can lead to data loss. The solution involves an integrated circuit with multiple retention-relevant storage devices divided into two groups. The first group retains critical data bits during power loss or low-power conditions, while the second group stores non-critical data. Each storage device in the first group includes a retention mechanism to preserve its assigned bit of critical data, ensuring it remains intact even when power is reduced or interrupted. The second group of storage devices stores non-critical data without retention mechanisms, allowing for more efficient use of circuit resources. This selective retention approach optimizes power consumption and circuit complexity while maintaining data integrity for essential information. The invention is particularly useful in applications such as embedded systems, IoT devices, and other low-power electronic systems where reliable data retention is crucial.
21. The integrated circuit of claim 19 , further comprising: scan chain means for activating the second group of the retention-relevant storage devices into multiple scan chains configured to be accessed serially, the multiple scan chains including the at least one scan chain.
This invention relates to integrated circuits with enhanced retention and testing capabilities for storage devices. The technology addresses the challenge of ensuring data retention in storage devices during power-down states while also enabling efficient testing of these devices. The integrated circuit includes a first group of storage devices that retain data during power-down and a second group of retention-relevant storage devices that also retain data during power-down. The second group is selectively activated to enter a retention mode, ensuring data integrity when power is restored. The circuit further includes scan chain functionality for the second group of storage devices, allowing them to be organized into multiple scan chains. These scan chains enable serial access to the storage devices, facilitating testing and verification of their functionality. The scan chains are configurable, meaning they can be adjusted to meet specific testing requirements. This combination of retention and testing features ensures reliable operation and simplifies the verification process for integrated circuits with retention-critical storage devices.
22. The integrated circuit of claim 19 , wherein the retention control means comprises data egress means for migrating the second data from the second group of the retention-relevant storage devices of the logic block to the memory block to accommodate the transition from the regular operational mode to the retention operational mode.
This invention relates to integrated circuits designed to manage data retention during transitions between operational modes, particularly in systems where power consumption or performance must be optimized. The problem addressed is ensuring data integrity and availability when switching between a regular operational mode and a retention operational mode, where certain storage devices may be powered down or otherwise altered in functionality. The integrated circuit includes a logic block with multiple retention-relevant storage devices divided into at least two groups. During a transition to retention mode, a retention control mechanism migrates data from a second group of these storage devices to a memory block. This migration ensures that data remains accessible even if the second group of storage devices is deactivated or otherwise altered in retention mode. The memory block serves as a temporary or permanent storage location for the migrated data, preserving it until the system returns to regular operational mode. The retention control mechanism may include specific data egress functionality to facilitate this migration, ensuring efficient and reliable data transfer. This approach allows the integrated circuit to maintain data integrity while optimizing power consumption or performance during mode transitions. The invention is particularly useful in low-power or energy-efficient systems where retention of critical data is essential during operational state changes.
23. The integrated circuit of claim 22 , wherein the data egress means comprises: extraction means for scanning the second data out of the at least one scan chain activated from the second group of the retention-relevant storage devices; and storage means for writing the second data into the memory block.
This invention relates to integrated circuits with retention-relevant storage devices and methods for managing data during power-down and power-up sequences. The problem addressed is ensuring data integrity in storage devices that retain their state during power-down, particularly when transitioning between active and retention modes. The integrated circuit includes a plurality of retention-relevant storage devices organized into at least two groups. A first group is activated during normal operation, while a second group is activated during power-down or power-up sequences. The circuit also includes a memory block for storing data and a data egress mechanism for transferring data from the second group of storage devices to the memory block. The data egress mechanism includes an extraction component that scans data out of the second group of storage devices, which are activated from the retention-relevant storage devices. A storage component then writes this scanned data into the memory block. This ensures that data from the retention-relevant storage devices is preserved and transferred efficiently during power transitions. The invention improves reliability and performance in integrated circuits by managing data flow between storage devices and memory during power state changes.
24. The integrated circuit of claim 19 , wherein the retention control means comprises data ingress means for migrating the second data from the memory block to the second group of the retention-relevant storage devices of the logic block to accommodate the transition from the retention operational mode to the regular operational mode.
This invention relates to integrated circuits with configurable retention control mechanisms for managing data retention during operational mode transitions. The problem addressed is ensuring data integrity and efficient storage utilization when transitioning between retention and regular operational modes in integrated circuits. The integrated circuit includes a logic block with retention-relevant storage devices and a memory block. The retention control mechanism is designed to migrate data between these components. Specifically, when transitioning from retention to regular operational mode, the system moves second data from the memory block to a second group of retention-relevant storage devices within the logic block. This migration ensures that critical data remains accessible and properly stored during the mode transition, preventing data loss or corruption. The retention control mechanism may also include additional means for managing data flow, such as data egress means for transferring data from the logic block to the memory block during other operational transitions. The invention improves data retention reliability in integrated circuits by dynamically allocating storage resources based on operational requirements, optimizing both power efficiency and data accessibility. This is particularly useful in systems requiring low-power states while maintaining fast access to critical data.
25. The integrated circuit of claim 24 , wherein the data ingress means comprises: retrieval means for reading the second data from the memory block; and insertion means for scanning the second data into the at least one scan chain activated from the second group of the retention-relevant storage devices.
Technical Summary: This invention relates to integrated circuits with enhanced data retention and testing capabilities. The problem addressed is ensuring reliable data storage and retrieval in integrated circuits, particularly during power-down or low-power states, while maintaining testability through scan chain functionality. The integrated circuit includes a memory block for storing data and a plurality of retention-relevant storage devices organized into multiple groups. These storage devices are configured to retain data during power-down or low-power states. The circuit further includes data ingress means for transferring data between the memory block and the storage devices. Specifically, the data ingress means comprises retrieval means for reading data from the memory block and insertion means for scanning the retrieved data into at least one scan chain. The scan chain is activated from a second group of the retention-relevant storage devices, allowing for efficient data transfer and testing operations. The invention ensures that critical data is preserved during low-power states while enabling seamless integration with scan testing mechanisms. This approach improves both data retention reliability and testability in integrated circuits.
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October 1, 2019
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