Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A compression circuit, comprising: A history buffer to store uncompressed data; a multiplexer coupled to the buffer and comprising first and second inputs, wherein the first input is configured to provide an initial value, and wherein the multiplexer is configured to generate a read pointer value to the buffer; a feedback register coupled to an output of the multiplexer and configured to store the read pointer value; an adder coupled to the feedback register and the second input of the multiplexer, wherein the adder is configured to increment the read pointer value from the feedback register to thereby generate an incremented read pointer value, and wherein the adder is configured provide the incremented read pointer value to the second input of the multiplexer; a compare circuit coupled to the history buffer; and a control circuit containing a programmable configuration register configured to store a depth value, wherein the control circuit is configured to cause the multiplexer to select the initial value as the read pointer and then to iteratively select the incremented read pointer value from the adder until the read pointer value matches the depth value, and then to again select the initial value as the read pointer value; wherein the compare circuit is configured to compare input symbols to uncompressed data from the history buffer to thereby generate output compressed data.
This invention relates to a compression circuit designed to efficiently compress data by leveraging a history buffer to store uncompressed data. The circuit includes a history buffer that holds uncompressed data for reference during compression. A multiplexer is coupled to the buffer and has two inputs: one for an initial value and another for an incremented read pointer value. The multiplexer generates a read pointer value to access the history buffer. A feedback register stores the current read pointer value, while an adder increments this value and provides it back to the multiplexer. A compare circuit checks input symbols against uncompressed data from the history buffer to produce compressed output data. A control circuit, featuring a programmable configuration register, stores a depth value that determines the range of the read pointer. The control circuit directs the multiplexer to start with the initial value, then iteratively select incremented values from the adder until the read pointer matches the depth value, at which point it resets to the initial value. This process ensures efficient data compression by repeatedly comparing input symbols to historical data within a defined range. The circuit optimizes compression by dynamically adjusting the read pointer to scan through the history buffer, improving matching efficiency and reducing redundancy in the output.
2. The compression circuit of claim 1 , wherein the depth value comprises a value such that less than the entire history buffer is read for comparison to the input symbols to thereby increase compression speed of the compression circuit.
The invention relates to a compression circuit designed to improve compression speed by optimizing the use of a history buffer. The circuit processes input symbols by comparing them to previously stored symbols in the history buffer to identify matches, which are then encoded for compression. A key feature is the use of a depth value that limits the portion of the history buffer read during comparisons, reducing the number of comparisons needed. This selective reading of the buffer accelerates the compression process without sacrificing compression efficiency. The depth value ensures that only a subset of the buffer is accessed, which is particularly useful in scenarios where full buffer searches are computationally expensive. The circuit may also include additional components such as a symbol encoder and a buffer manager to handle symbol encoding and buffer updates. The overall system balances speed and efficiency by dynamically adjusting the depth value based on the input data characteristics, ensuring optimal performance for different compression workloads. This approach is beneficial in applications requiring fast compression, such as real-time data processing or embedded systems with limited computational resources.
3. The compression circuit of claim 1 , further comprising a line buffer, and wherein: the history buffer is configured to store the uncompressed data in a plurality of lines, each line having a line width; the line buffer has a capacity equal to the line width of the history buffer; line buffer is configured to store the input symbols; and responsive to the line buffer becoming full of input symbols, the line buffer is configured to write its stored input symbols to the history buffer.
This invention relates to data compression systems, specifically a compression circuit that improves efficiency by managing uncompressed data storage and retrieval. The problem addressed is the need for efficient handling of uncompressed data in compression systems, particularly when dealing with large datasets or high-speed data streams. The compression circuit includes a history buffer that stores uncompressed data in multiple lines, each with a defined line width. A line buffer is integrated into the circuit, with a capacity matching the line width of the history buffer. The line buffer temporarily stores input symbols (data to be compressed) before they are transferred to the history buffer. When the line buffer fills with input symbols, it automatically writes its contents to the history buffer, ensuring continuous and organized data flow. This design optimizes memory usage and reduces latency by preventing direct, unstructured writes to the history buffer. The line buffer acts as an intermediary, allowing the compression circuit to process data in manageable segments while maintaining synchronization between input data and historical reference storage. The system is particularly useful in applications requiring real-time compression, such as video encoding or high-speed data transmission, where efficient data handling is critical.
4. The compression circuit of claim 1 , wherein the initial value is 0.
A compression circuit is designed to efficiently encode data by reducing redundancy, particularly in digital signals or data streams. The circuit addresses the challenge of minimizing storage or transmission bandwidth by compressing data while maintaining accuracy and reducing computational overhead. The circuit includes a processing unit that applies a compression algorithm to input data, where the algorithm utilizes an initial value to optimize the compression process. In this specific embodiment, the initial value is set to 0, which simplifies calculations and reduces the complexity of the compression logic. The processing unit may include arithmetic or logical operations to transform the input data into a compressed form, such as differential encoding, run-length encoding, or entropy coding. The circuit may also include memory or buffer components to store intermediate or final compressed data. The use of an initial value of 0 ensures that the compression process starts from a neutral state, avoiding bias and improving efficiency. The circuit may be integrated into larger systems, such as data storage devices, communication systems, or multimedia processing units, to enhance performance and reduce resource usage. The compression circuit is particularly useful in applications where low-latency and high-efficiency compression are required, such as real-time data transmission or embedded systems with limited processing power.
5. The compression circuit of claim 1 , wherein the compare circuit is configured to generate lossless output compressed data.
A compression circuit is designed to improve data compression efficiency by generating lossless output compressed data. The circuit includes a compare circuit that evaluates input data to determine the most efficient compression method. The compare circuit identifies patterns or redundancies in the input data and applies lossless compression techniques to ensure no data is lost during the process. These techniques may include dictionary-based methods, run-length encoding, or other lossless algorithms that preserve the original data integrity. The circuit also includes a selection circuit that chooses the optimal compression method based on the analysis performed by the compare circuit. This selection is dynamic, adapting to the characteristics of the input data to maximize compression efficiency while maintaining lossless quality. The output of the compression circuit is fully decompressible back to the original input data, ensuring no information is lost. This approach is particularly useful in applications where data integrity is critical, such as in medical imaging, financial records, or any system requiring exact data reconstruction. The circuit's ability to dynamically select the best compression method enhances performance and reduces storage or transmission requirements without compromising data accuracy.
6. The compression circuit of claim 1 , wherein the compare circuit is configured to compare the input symbols to uncompressed data read from the history buffer based on a second depth value stored in the programmable configuration register.
The invention relates to a compression circuit designed to improve data compression efficiency by dynamically adjusting comparison operations. The circuit addresses the problem of inefficient compression in systems where fixed comparison depths fail to adapt to varying data patterns, leading to suboptimal compression ratios or excessive processing overhead. The compression circuit includes a compare circuit that evaluates input symbols against uncompressed data stored in a history buffer. The comparison process is controlled by a programmable configuration register, which stores a second depth value. This depth value determines the extent of the comparison operation, allowing the circuit to dynamically adjust how many historical data entries are checked against the input symbols. By programmably setting this depth, the system can balance between compression performance and computational overhead, adapting to different data characteristics. The history buffer stores uncompressed data that has been previously processed, enabling the compare circuit to identify repeating patterns or sequences. The programmable configuration register allows the depth value to be modified, providing flexibility in how many historical entries are compared. This adaptability ensures that the compression circuit can optimize its operations based on real-time data patterns, improving efficiency without requiring manual adjustments. The overall system enhances compression performance by dynamically adjusting the comparison depth, reducing unnecessary computations while maintaining high compression ratios. This approach is particularly useful in applications where data patterns vary significantly, such as in real-time data processing or adaptive storage systems.
7. A circuit, comprising: a history buffer to store uncompressed data; a selection circuit coupled to the history buffer and configured to provide a read pointer value to the history buffer; a compare circuit coupled to the history buffer; and a control circuit containing a programmable configuration register, wherein the configuration register is configured to store a depth value for reading uncompressed data from the history buffer and the control circuit is configured to generate control signals for the selection circuit to cause the selection circuit to iteratively increment the read pointer value from an initial value to a second value that corresponds to the depth value and, responsive to the second value corresponding to the depth value, to reset the read pointer value to the initial value; wherein the compare circuit is configured to compare input symbols from a data source to uncompressed data from the buffer history to thereby generate output compressed data.
This invention relates to a data compression circuit designed to improve efficiency in data processing systems by leveraging a history buffer to store uncompressed data for comparison with input symbols. The circuit includes a history buffer that retains uncompressed data, a selection circuit that provides a read pointer to access the buffer, a compare circuit that matches input symbols against the buffered data, and a control circuit with a programmable configuration register. The configuration register sets a depth value that determines how many data entries the selection circuit reads from the buffer before resetting the read pointer. The control circuit generates signals to increment the read pointer iteratively from an initial value until it reaches the depth value, at which point it resets to the initial value. The compare circuit then compares input symbols from a data source to the uncompressed data retrieved from the buffer, producing compressed output data based on these comparisons. This approach enhances compression efficiency by dynamically adjusting the search depth within the history buffer, allowing for more flexible and adaptive data matching. The programmable depth value enables customization for different compression scenarios, optimizing performance based on specific data patterns or system requirements.
8. The circuit of claim 7 , wherein the circuit is a system-on-chip (SoC).
A system-on-chip (SoC) integrates multiple electronic components, including a processor, memory, and specialized hardware, into a single integrated circuit. This design reduces power consumption, improves performance, and minimizes physical footprint compared to discrete components. The SoC includes a power management unit that dynamically adjusts power delivery to different components based on their operational demands. This unit monitors real-time power consumption and efficiency metrics, such as voltage, current, and thermal data, to optimize energy usage. The SoC also incorporates a thermal management system that detects overheating and triggers cooling mechanisms, such as throttling or redirecting power to cooling elements. Additionally, the SoC features a security module that enforces access controls and encrypts data to protect against unauthorized access. The integrated design ensures seamless communication between components, reducing latency and improving overall system efficiency. This approach is particularly useful in portable devices, embedded systems, and high-performance computing applications where power efficiency and compactness are critical.
9. The circuit of claim 7 , wherein the depth value comprises a value such that less than the entire history buffer is read for comparison to the input symbols.
A system for efficient pattern matching in data processing involves a circuit that compares input symbols against stored symbol sequences in a history buffer to identify matches. The circuit includes a depth value that determines how much of the history buffer is searched during each comparison operation. By limiting the search depth to less than the full buffer, the system reduces computational overhead while still detecting relevant patterns. The circuit may also include a buffer for storing input symbols, a comparator for matching symbols against the history buffer, and a controller for managing the comparison process. The depth value can be dynamically adjusted based on system requirements or input characteristics to balance accuracy and performance. This approach is particularly useful in applications like data compression, where partial matching can significantly improve efficiency without sacrificing compression quality. The system ensures that only a portion of the history buffer is accessed during each comparison, minimizing memory bandwidth and processing time. The depth value can be set to a fixed value or adjusted adaptively to optimize performance for different input data types.
10. The circuit of claim 7 , wherein the selection circuit comprises a multiplexer coupled to a feedback register and an adder.
A circuit is provided for processing digital signals, particularly in applications requiring dynamic selection of input data paths. The circuit includes a selection circuit that dynamically routes input signals to a processing unit, such as an adder, based on control signals. The selection circuit comprises a multiplexer coupled to a feedback register and an adder. The multiplexer selects between multiple input signals or feedback signals from the register, allowing flexible data routing. The feedback register stores intermediate results, which can be fed back into the multiplexer for further processing. The adder performs arithmetic operations on the selected inputs, enabling computations such as accumulation or summation. This configuration allows the circuit to perform iterative calculations, such as those used in digital filtering, signal processing, or arithmetic operations, by dynamically adjusting the data path based on control inputs. The circuit is particularly useful in systems requiring real-time processing and adaptive data routing, such as digital signal processors or programmable logic devices. The feedback loop enables continuous processing of data streams, improving efficiency and reducing latency in applications like audio processing, communication systems, or control systems.
11. The circuit of claim 10 , wherein: the feedback register is configured to store each generated value of the read pointe value; the adder is configured to increment the read pointer value stored in the feedback register to produce an adder output value; and the multiplexer inputs include the initial value and the adder output value.
This invention relates to a digital circuit for managing read pointer values in a data processing system. The problem addressed is the need for efficient and accurate tracking of read pointer positions, particularly in systems where data is accessed sequentially or in a circular buffer. The circuit includes a feedback register, an adder, and a multiplexer to dynamically update and control the read pointer value. The feedback register stores each generated value of the read pointer, ensuring that the current position is retained for subsequent operations. The adder increments the read pointer value stored in the feedback register to produce an adder output value, which represents the next position in the sequence. The multiplexer selects between an initial value and the adder output value, allowing the read pointer to be reset or advanced as needed. This configuration enables flexible and precise control over read operations, ensuring correct data access in systems requiring sequential or circular addressing. The circuit is particularly useful in memory management, buffer handling, and data streaming applications where accurate pointer tracking is critical.
12. The circuit of claim 7 , further comprising a line buffer coupled to the history buffer and the compare circuit, and wherein: the history buffer is configured to store the uncompressed data in a plurality of lines, each line having a line width; the line buffer has a capacity equal to the line width of the history buffer; the line buffer is configured to store input symbols, each input symbol having a size smaller than the capacity of the line buffer; and responsive to the line buffer becoming full of input symbols, the line buffer is configured to write its stored input symbols to the history buffer.
This invention relates to data compression systems, specifically a circuit for efficient data storage and retrieval in a lossless compression scheme. The problem addressed is optimizing memory usage and processing speed when handling uncompressed data before compression, particularly in systems where data is processed in fixed-width lines. The circuit includes a history buffer that stores uncompressed data in multiple lines, each with a defined line width. A line buffer, with a capacity matching the history buffer's line width, temporarily holds input symbols (each smaller than the line buffer's capacity) before they are written to the history buffer. When the line buffer fills with input symbols, it transfers its contents to the history buffer. This ensures efficient data organization and reduces memory access overhead by minimizing partial writes. Additionally, the circuit includes a compare circuit that checks input symbols against data in the history buffer to identify matches, enabling compression by referencing previously stored data. The line buffer's role is to aggregate symbols into complete lines before storage, improving throughput and reducing fragmentation in the history buffer. This design is particularly useful in real-time compression applications where data must be processed sequentially and efficiently.
13. The circuit of claim 7 , wherein the compare circuit is configured to generate lossless output compressed data using the Lempel-Ziv (LZ) compression algorithm.
The invention relates to data compression circuits, specifically those implementing the Lempel-Ziv (LZ) compression algorithm to generate lossless output compressed data. The circuit includes a compare circuit that identifies repeated sequences in input data and replaces them with references to previously occurring sequences, a key feature of LZ compression. This approach reduces data size without losing any information, making it suitable for applications requiring efficient storage or transmission of data. The circuit may also include a memory for storing previously encountered sequences and a substitution circuit for replacing repeated sequences with references. The compare circuit operates by scanning the input data, detecting patterns that match earlier sequences, and generating compressed output by encoding these patterns as references. This method ensures that the original data can be perfectly reconstructed during decompression. The invention addresses the need for efficient, lossless data compression in digital systems, particularly where bandwidth or storage constraints are critical. The LZ algorithm is chosen for its balance between compression efficiency and computational simplicity, making it practical for hardware implementation. The circuit may be integrated into larger systems such as data storage devices, communication systems, or embedded processors to enhance performance by reducing data size while maintaining data integrity.
14. The circuit of claim 7 , wherein the control circuit is configured to generate the control signals to thereby cause less than all of the contents from the history buffer to be read from the history buffer for use in comparison to the input symbols for generation of the output compressed data.
This invention relates to data compression systems, specifically improving efficiency in history-based compression techniques. The problem addressed is the computational overhead and latency associated with reading and comparing large amounts of historical data during compression, which can slow down real-time processing. The system includes a history buffer that stores previously processed data symbols and a control circuit that manages the reading and comparison of these symbols. The control circuit selectively reads only a portion of the history buffer contents rather than the entire buffer, reducing the amount of data that must be compared against incoming input symbols. This selective reading is based on control signals generated by the control circuit, which determine which portions of the history buffer are accessed for comparison. By limiting the comparison to a subset of the history buffer, the system reduces processing time and power consumption while maintaining compression efficiency. The control circuit may use various strategies to determine which portions of the history buffer to read, such as prioritizing recently stored symbols or focusing on specific memory regions. The output compressed data is generated by comparing the input symbols to the selected subset of historical symbols, ensuring that only relevant historical data is used in the compression process. This approach optimizes performance in applications requiring fast compression, such as real-time data transmission or storage systems.
15. The compression circuit of claim 7 , wherein the compare circuit is configured to: compare a first set of input symbols from the data source to a first portion of the history buffer read using the depth value to thereby generate the output compressed data; and then to compare a second set of input symbols from the data source to a second portion of the history buffer, different in size from the first portion, the second portion having been read using a second depth value stored in the programmable configuration register to thereby generate additional output compressed data.
This invention relates to a compression circuit designed to improve data compression efficiency by dynamically adjusting the size of the history buffer portion used for comparisons. The problem addressed is the static approach in traditional compression circuits, which limits compression performance by using a fixed-size history buffer portion for all comparisons. The invention introduces a programmable configuration register that stores a second depth value, allowing the compare circuit to switch between different-sized portions of the history buffer. Initially, the compare circuit compares a first set of input symbols from the data source to a first portion of the history buffer, read using a depth value, to generate output compressed data. Subsequently, the compare circuit compares a second set of input symbols to a second, differently sized portion of the history buffer, read using the second depth value from the programmable register, to generate additional compressed data. This adaptability enhances compression ratios by leveraging variable-length history buffer portions, optimizing for different data patterns. The circuit includes a history buffer for storing previously processed data, a programmable configuration register to store the second depth value, and a compare circuit that dynamically adjusts the comparison window size based on the stored depth values. This approach improves compression efficiency without requiring additional hardware complexity.
16. A method, comprising: storing a programmable depth value into a configuration register; storing data from a data source into a history buffer; reading a portion of the history buffer based on the depth value; and compressing data from the data source using the portion of the history buffer; wherein reading the portion of the history buffer includes: initializing a read pointer to an initial value; retrieving data from the history buffer using the read pointer; incrementing the read pointer to produce an incremented read pointer; and responsive to the incremented read pointer corresponding to the depth value, re-initializing the read pointer to the initial value and retrieving additional data from the history buffer.
This invention relates to data compression techniques that utilize a history buffer to improve compression efficiency. The problem addressed is the need for efficient data compression, particularly in systems where historical data patterns can be leveraged to reduce redundancy. The method involves storing a programmable depth value in a configuration register, which defines the size or range of the history buffer to be used for compression. Data from a data source is stored in a history buffer, which acts as a reference for identifying repeating patterns. A portion of the history buffer is read based on the depth value, where the reading process involves initializing a read pointer to a starting position, retrieving data at that position, incrementing the pointer, and resetting the pointer to the initial value when it reaches the depth value. This ensures that only the relevant portion of the history buffer is used for compression. The retrieved data is then used to compress the incoming data from the data source, leveraging the historical patterns to achieve higher compression ratios. The method dynamically adjusts the read pointer to maintain a fixed-size window of historical data, optimizing the compression process for efficiency and accuracy.
17. The method of claim 16 , further comprising, after compressing a portion of the data source: storing a second programmable depth value into the configuration register; determining that the incremented read pointer corresponds to the second programmable depth value; responsive to the determination that the incremented read pointer corresponds to the second programmable depth value, re-initializing the read pointer to the initial value; and compressing additional data from the data source using a second portion of the history read based on the second programmable depth value.
This invention relates to data compression systems that use a history buffer to improve compression efficiency. The problem addressed is managing the read pointer in a circular history buffer to ensure efficient data compression without losing historical context. The system includes a data compression module that compresses data from a data source using a history buffer. The history buffer stores previously compressed data to improve compression efficiency. A read pointer tracks the position within the history buffer. The system also includes a configuration register that stores a programmable depth value, which defines the active portion of the history buffer used for compression. The method involves compressing a portion of the data source using a first portion of the history buffer based on an initial read pointer value. The read pointer is incremented after each compression operation. If the incremented read pointer reaches a programmable depth value stored in the configuration register, the read pointer is reset to its initial value. This ensures the history buffer remains within a defined active region, preventing the read pointer from overwriting critical historical data. Additionally, the system allows for dynamic adjustment of the active history buffer region by storing a second programmable depth value in the configuration register. When the incremented read pointer matches this second value, the read pointer is re-initialized to the initial value, and compression continues using a second portion of the history buffer based on the new depth value. This flexibility allows the system to adapt to different compression requirements or data patterns.
18. The method of claim 16 , wherein reading a portion of the history buffer based on the depth value comprises reading less than all of the contents of the history buffer.
A system and method for efficiently accessing historical data in a computing environment, particularly for optimizing performance in applications requiring frequent access to past states or operations. The invention addresses the challenge of managing large volumes of historical data while minimizing resource consumption, such as memory and processing time. The method involves storing a sequence of historical data in a buffer, where the buffer retains a configurable depth of entries. When accessing the buffer, the system reads only a portion of the stored data based on a specified depth value, rather than retrieving the entire contents. This selective reading reduces unnecessary data retrieval, improving efficiency. The depth value determines how much of the buffer is accessed, allowing the system to dynamically adjust the amount of historical data processed based on current requirements. This approach is particularly useful in applications like undo/redo operations, performance monitoring, or predictive analytics, where partial historical data may suffice for the task at hand. By limiting the read operations to a subset of the buffer, the system conserves resources and enhances responsiveness. The method ensures that only relevant portions of the historical data are accessed, balancing performance and accuracy.
19. The method of claim 16 , further comprising receiving the programmable depth value from a user.
A system and method for adjusting depth perception in a display device addresses the challenge of optimizing visual comfort and clarity for users viewing three-dimensional (3D) content. The invention involves dynamically modifying the depth perception of displayed content based on user preferences or environmental conditions. The core method includes generating a depth map for the content, where the depth map defines spatial relationships between objects in the scene. A programmable depth value is applied to adjust the perceived depth of the content, enhancing or reducing the 3D effect as needed. This adjustment can be performed in real-time to improve user experience, particularly in applications like gaming, virtual reality, or medical imaging where depth perception is critical. The system may also include a user interface for receiving the programmable depth value, allowing users to manually fine-tune the depth setting to their liking. Additionally, the method may incorporate environmental sensors to automatically adjust depth perception based on ambient lighting or viewing distance, ensuring optimal visual comfort. The invention aims to provide a flexible and adaptive solution for enhancing depth perception in digital displays, improving usability and reducing eye strain.
Unknown
October 1, 2019
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