Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A data storage device comprising: a first printed circuit board (PCB) comprising a main transmission pattern formed on at least one surface of the first PCB and/or within the first PCB, a memory controller provided on the first PCB; and a plurality of nonvolatile memory devices provided on the first PCB, the plurality of nonvolatile memory devices connected to the memory controller through a channel and configured to exchange data with the memory controller, wherein the channel includes a data transmission line connecting data pads of the memory controller and the nonvolatile memory devices, wherein the data transmission line comprises the main transmission pattern, a branch transmission pattern and an open stub contacting the main transmission pattern, wherein the open stub does not contact any other conductor other than the main transmission pattern, wherein the branch transmission pattern includes a plurality of branch wires, wherein the main transmission pattern includes a first end contacting the memory controller and a second end contacting only a first branch wire of tihe branch transmission pattern, and wherein the memory controller connects to the nonvolatile memory devices through the main transmission pattern and the plurality of branch wires, which connect to each other in series.
A data storage device includes a printed circuit board (PCB) with a main transmission pattern on or within its surface, a memory controller, and multiple nonvolatile memory devices. The memory controller and memory devices are connected via a channel that includes a data transmission line. This line consists of the main transmission pattern, a branch transmission pattern, and an open stub. The open stub connects only to the main transmission pattern and no other conductors. The branch transmission pattern has multiple branch wires, with the main transmission pattern having one end connected to the memory controller and the other end connected only to the first branch wire. The memory controller communicates with the memory devices through the main transmission pattern and the branch wires, which are connected in series. This design optimizes signal integrity and reduces interference in high-speed data transmission between the controller and memory devices. The open stub and series-connected branch wires help manage signal reflections and impedance matching, improving reliability in data storage operations.
2. The data storage device of claim 1 , wherein the open stub comprises a first open stub pattern which extends along a second direction from a first position of the main transmission pattern, wherein the main transmission pattern extends in a first direction perpendicular to the second direction, and wherein the first position of the main transmission pattern is closer to the memory controller than the branch transmission pattern.
This invention relates to data storage devices, specifically addressing signal integrity and transmission efficiency in high-density storage systems. The device includes a main transmission pattern for data signals, a branch transmission pattern connected to the main pattern, and an open stub extending from the main pattern. The open stub features a first open stub pattern that runs perpendicular to the main transmission pattern, starting from a position on the main pattern that is closer to the memory controller than the branch transmission pattern. This configuration optimizes signal routing, reducing reflections and improving data transmission reliability. The open stub's specific placement and orientation help mitigate signal distortion, particularly in high-frequency operations, while maintaining compact design. The branch transmission pattern connects to the main pattern at a point farther from the controller, ensuring efficient signal distribution to multiple storage elements. The overall design enhances signal integrity in densely packed storage architectures, addressing challenges in high-speed data transfer and minimizing electromagnetic interference.
3. The data storage device of claim 2 , wherein a length of the first open stub pattern in the second direction is 1/K of a length of the main transmission pattern in the first direction, K being a natural number greater than 1.
The invention relates to data storage devices, specifically those using open stub patterns to improve signal integrity in high-density storage systems. The problem addressed is signal distortion and crosstalk in densely packed storage media, which can degrade data reliability. The solution involves a data storage device with a main transmission pattern and at least one open stub pattern. The open stub pattern is positioned adjacent to the main transmission pattern to mitigate signal interference. The open stub pattern extends in a second direction perpendicular to the first direction of the main transmission pattern. The length of the open stub pattern in the second direction is precisely controlled to be 1/K of the length of the main transmission pattern in the first direction, where K is a natural number greater than 1. This proportional relationship ensures optimal impedance matching and minimizes reflections, thereby enhancing signal quality. The open stub pattern may be positioned on either side of the main transmission pattern or between multiple main transmission patterns to further reduce crosstalk. The design is particularly useful in high-frequency data transmission applications where signal integrity is critical.
4. The data storage device of claim 2 , further comprising: a second PCB connected with the first PCB through a through-substrate via, wherein the first open stub pattern is formed on the second PCB which is formed on a different layer from a layer in which the first PCB is formed, and the first open stub pattern is connected to the main transmission pattern through the through-substrate via formed in the first PCB.
This invention relates to a data storage device with an improved signal transmission structure. The device addresses signal integrity issues in high-speed data transmission within multi-layer printed circuit boards (PCBs), particularly in storage devices where multiple PCBs are interconnected. The problem arises from signal reflections and impedance mismatches caused by abrupt changes in transmission paths, degrading performance in high-frequency applications. The device includes a first PCB with a main transmission pattern for carrying signals and a first open stub pattern connected to the main transmission pattern. The open stub pattern is designed to absorb or reflect unwanted signal reflections, improving signal quality. A second PCB is connected to the first PCB via a through-substrate via, which is a conductive path penetrating the substrate. The first open stub pattern is formed on the second PCB, which is on a different layer than the first PCB. The through-substrate via in the first PCB connects the open stub pattern to the main transmission pattern, ensuring continuous signal transmission across layers while maintaining impedance matching. This layered structure allows for compact design and efficient signal management in multi-layer storage devices. The invention enhances signal integrity and reliability in high-speed data storage applications.
5. The data storage device of claim 1 , further comprising: an interposer interposed between the first PCB and the memory controller, wherein the at least a portion of the open stub is formed in the interposer.
This invention relates to data storage devices, specifically addressing the challenge of signal integrity and space constraints in high-density memory systems. The device includes a printed circuit board (PCB) with a memory controller and a memory module, where the PCB has an open stub structure designed to improve signal transmission. The open stub is a conductive trace segment that extends beyond a connection point, tuned to specific electrical characteristics to minimize signal reflections and enhance data transfer reliability. The memory module is electrically connected to the PCB, and the memory controller manages data operations between the memory module and a host system. The interposer, a thin circuit layer, is placed between the PCB and the memory controller. This interposer incorporates at least part of the open stub, allowing for compact integration while maintaining signal integrity. By embedding the open stub in the interposer, the design optimizes space utilization and reduces signal degradation, particularly in high-speed memory applications. The interposer may also include additional conductive paths or passive components to further refine signal performance. This configuration is particularly useful in devices requiring high-density memory configurations, such as solid-state drives or high-performance computing systems.
6. The data storage device of claim 1 , further comprising: an interposer interposed between the first PCB and a package containing the nonvolatile memory devices, wherein the at least a portion of the open stub is formed in the interposer.
The invention relates to data storage devices, specifically addressing challenges in signal integrity and space efficiency in high-density memory systems. Traditional designs often suffer from signal reflections and crosstalk due to improperly terminated transmission lines, particularly in high-speed interfaces. The invention improves upon prior art by incorporating an interposer between a printed circuit board (PCB) and a memory package containing nonvolatile memory devices. This interposer includes at least a portion of an open stub, a transmission line segment intentionally left unterminated to control impedance and signal reflections. The interposer acts as an intermediate layer, facilitating electrical connections while optimizing signal routing and termination. By integrating the open stub within the interposer, the design reduces signal degradation and improves data transfer reliability without increasing the overall footprint of the storage device. The interposer may also include additional components or routing layers to further enhance performance. This approach is particularly useful in solid-state drives (SSDs) and other high-performance storage systems where minimizing signal interference and maximizing space utilization are critical. The invention ensures efficient signal management while maintaining compact form factors.
7. The data storage device of claim 1 , wherein the open stub comprises: a first open stub pattern which extends in a second direction at a first position from the main transmission pattern; a second open stub pattern which extends in a direction opposite to the second direction from the first position; and the first position of the main transmission pattern is closer two times to the memory controller than the branch transmission pattern, wherein the main transmission pattern extends in a first direction perpendicular to the second direction.
This invention relates to data storage devices, specifically to the design of transmission patterns and open stubs in high-speed data transmission systems. The problem addressed is signal integrity and timing synchronization in data storage devices, particularly in systems where data is transmitted between a memory controller and memory chips. The invention improves signal transmission by optimizing the layout of open stubs and transmission patterns to reduce signal reflections and skew. The data storage device includes a main transmission pattern and a branch transmission pattern connected to a memory controller. The main transmission pattern extends in a first direction, while an open stub extends from the main transmission pattern at a first position. The open stub comprises two patterns: a first open stub pattern extending in a second direction (perpendicular to the first direction) and a second open stub pattern extending in the opposite direction. The first position is located such that it is twice as close to the memory controller as the branch transmission pattern. This configuration ensures balanced signal propagation, minimizing signal distortion and improving timing accuracy. The design helps maintain signal integrity by reducing reflections and ensuring consistent signal arrival times across different transmission paths.
8. The data storage device of claim 7 , wherein a length of the first open stub pattern in the second direction is 1/K times greater than a length of the main transmission pattern in the first direction, K being a natural number greater than 1.
This invention relates to data storage devices, specifically those using high-density storage techniques where signal integrity and transmission efficiency are critical. The problem addressed is optimizing signal transmission in storage devices by improving the design of transmission lines and stub patterns to reduce signal reflections and crosstalk, thereby enhancing data reliability and performance. The invention describes a data storage device with a transmission line structure that includes a main transmission pattern and multiple open stub patterns. The main transmission pattern is oriented in a first direction and is used for transmitting signals. The open stub patterns are oriented in a second direction, perpendicular to the first, and are connected to the main transmission pattern. These stubs are designed to improve signal integrity by absorbing or reflecting unwanted signal components. A key feature is that the length of the first open stub pattern in the second direction is 1/K times the length of the main transmission pattern in the first direction, where K is a natural number greater than 1. This ratio ensures precise control over signal propagation, minimizing reflections and optimizing impedance matching. The stub patterns may be arranged symmetrically or asymmetrically to further enhance performance. The device may also include additional open stub patterns with varying lengths to fine-tune signal characteristics. The overall design aims to improve signal quality, reduce errors, and increase data transfer rates in high-density storage systems.
9. The data storage device of claim 1 , wherein the nonvolatile memory devices are provided in a form of multi-stacked chips on the first PCB.
The invention relates to data storage devices, specifically addressing the challenge of increasing storage density and efficiency in electronic devices. Traditional data storage devices often struggle with limited space and thermal management issues as they scale up in capacity. This invention improves upon prior designs by incorporating nonvolatile memory devices in a multi-stacked chip configuration on a first printed circuit board (PCB). The multi-stacked chips allow for higher storage density within a compact footprint, optimizing space utilization. The nonvolatile memory devices, which retain data without power, are arranged in a stacked formation to maximize vertical space efficiency while maintaining reliable performance. This configuration also enhances thermal dissipation by distributing heat more effectively across the stacked layers. The first PCB provides structural support and electrical connectivity for the stacked memory chips, ensuring stable operation. The overall design aims to improve storage capacity, thermal management, and space efficiency in data storage devices, making it suitable for applications requiring high-density storage in constrained environments.
10. The data storage device of claim 9 , wherein each of the nonvolatile memory devices comprises: a memory cell array including a plurality of nonvolatile memory cells; a data input/output (I/O) circuit configured to receive data to be programmed in the memory cell array through a pad coupled to the data transmission line and configured to provide data read from the memory cell array to the pad; a data I/O switch coupled between the pad and the data I/O circuit; and a control circuit configured to generate a switch control signal that controls turn-on and turn-off of the data I/O switch in response to a chip enable signal.
This invention relates to data storage devices, specifically nonvolatile memory systems, addressing challenges in data transmission efficiency and power management. The device includes multiple nonvolatile memory devices, each containing a memory cell array with numerous nonvolatile memory cells for storing data. A data input/output (I/O) circuit is configured to receive data for programming into the memory cell array via a pad connected to a data transmission line and to output data read from the memory cell array to the same pad. A data I/O switch is positioned between the pad and the data I/O circuit, controlling data flow. A control circuit generates a switch control signal to activate or deactivate the data I/O switch based on a chip enable signal, ensuring efficient data transmission and reducing power consumption by selectively enabling data paths only when necessary. This design optimizes data handling in nonvolatile memory systems by dynamically managing data I/O operations, improving energy efficiency and performance. The invention is particularly useful in high-density storage applications where power management and data transfer speed are critical.
11. The data storage device of claim 10 , wherein the memory cell array includes a plurality of cell strings, and each of the plurality of cell strings includes a plurality of memory cells which are stacked vertically with respect to a substrate of each of the nonvolatile memory devices.
This invention relates to a data storage device with a vertically stacked memory cell array. The device addresses the challenge of increasing storage density in nonvolatile memory systems by utilizing a three-dimensional (3D) architecture. The memory cell array comprises multiple cell strings, each containing a vertical stack of memory cells arranged perpendicular to a substrate. This vertical stacking allows for higher memory density compared to traditional planar memory structures, enabling more efficient use of chip area. The memory cells in each string are connected in series, forming a vertical column that enhances scalability and reduces footprint. The device leverages nonvolatile memory technology, such as NAND flash, to retain data without power. The vertical arrangement improves performance by reducing cell-to-cell interference and enabling faster access times. This design is particularly useful in solid-state drives (SSDs) and other high-density storage applications where space efficiency and reliability are critical. The invention focuses on optimizing the physical layout of memory cells to achieve higher storage capacity while maintaining or improving performance characteristics.
12. A method of operating a data storage device, the method comprising: providing a memory controller and a plurality of nonvolatile memory devices on a first printed circuit board (PCB); providing a data transmission line electrically connecting the memory controller and the nonvolatile memory devices on the first PCB, the data transmission line including a main transmission pattern, a branch transmission pattern and at least a first open stub; and transmitting data to at least one of the nonvolatile memory devices from the memory controller through the data transmission line, wherein the first open stub extends in a second direction at a first position of the data transmission line which extends in a first direction perpendicular to the second direction, wherein the first position of the data transmission line is closer to the memory controller than the nonvolatile memory devices, wherein the first open stub includes one end electrically connected to the first position of the data transmission line and one end open, wherein the branch transmission pattern includes a plurality of branch wires, wherein the main transmission pattern includes a first end contacting the memory controller and a second end contacting only a first branch wire of the branch transmission pattern, and wherein the memory controller connects to the nonvolatile memory devices through the main transmission pattern and the plurality of branch wires, which connect to each other in series.
This invention relates to a data storage system with improved signal integrity in high-speed data transmission between a memory controller and nonvolatile memory devices. The system addresses signal reflection and impedance mismatches in data transmission lines, which can degrade performance in high-speed storage devices. The system includes a memory controller and multiple nonvolatile memory devices mounted on a printed circuit board (PCB). A data transmission line connects the memory controller to the memory devices, featuring a main transmission pattern, a branch transmission pattern, and at least one open stub. The main transmission pattern extends in a first direction and connects directly to the memory controller at one end, while its other end connects only to the first branch wire of the branch transmission pattern. The branch transmission pattern consists of multiple branch wires connected in series, linking the main transmission pattern to the memory devices. An open stub extends perpendicularly from the main transmission pattern at a position closer to the memory controller than the memory devices. The stub has one end connected to the main transmission pattern and the other end left open. This configuration helps mitigate signal reflections and impedance mismatches, improving data transmission reliability in high-speed storage applications. The serial connection of branch wires ensures controlled signal propagation to each memory device.
13. The method of claim 12 , wherein the first open stub is provided on the first PCB.
A method for optimizing signal integrity in high-speed electronic circuits involves using open stubs on printed circuit boards (PCBs) to improve impedance matching and reduce signal reflections. The method addresses the problem of signal degradation in high-frequency applications, where mismatched impedances cause reflections that degrade performance. The technique involves strategically placing open stubs on the PCB to tune the impedance of transmission lines, ensuring signals propagate without distortion. The open stubs are designed to resonate at specific frequencies, absorbing or reflecting unwanted signal components to minimize interference. The method also includes adjusting the length and position of the stubs to match the impedance of the transmission lines with the connected components, such as connectors or integrated circuits. By fine-tuning these parameters, the method ensures optimal signal transmission across the PCB, reducing losses and improving overall system reliability. The open stubs are integrated directly into the PCB layout, allowing for precise control over signal integrity without requiring additional external components. This approach is particularly useful in high-speed digital and RF applications where signal fidelity is critical.
14. The method of claim 12 , wherein the first open stub is provided on a second PCB which is formed on a different layer from a layer in which the first PCB is formed.
This invention relates to printed circuit board (PCB) designs for high-frequency signal transmission, addressing signal integrity issues caused by impedance mismatches and reflections in multi-layer PCB assemblies. The method involves using open stubs to improve signal transmission by terminating transmission lines at specific points. The open stubs are conductive traces that extend from the main signal path but are left electrically open at one end, acting as impedance-matching elements to reduce signal reflections. The method includes positioning a first open stub on a second PCB, which is fabricated on a different layer than the layer containing the primary PCB. This layered arrangement allows for optimized signal routing and improved impedance control, particularly in high-density or multi-layer PCB designs where signal integrity is critical. The open stubs are designed to resonate at specific frequencies, absorbing unwanted reflections and minimizing signal distortion. The technique is particularly useful in high-speed digital and RF applications where maintaining signal integrity across different PCB layers is essential. By strategically placing open stubs on separate layers, the method ensures consistent impedance matching and reduces signal degradation, enhancing overall system performance.
15. A data storage device comprising: a first printed circuit board (PCB) comprising a main transmission line; a memory controller provided on the first PCB; and a plurality of memory devices provided on the first PCB, and connected to the memory controller through a transmission line comprising the main transmission line, a branch transmission line and an open stub, wherein the main transmission line extends in a first direction, and has a first end connected to the memory controller and a second end connected to the plurality of memory devices through the branch transmission line, wherein the open stub extends in a second direction different from the first direction, and has a first end connected to the main transmission line at a first position of the main transmission line and a second end open, wherein the first position is closer to the memory controller than at least one of the plurality of memory devices, or is closer to at least one of the plurality of memory devices than the memory controller, wherein the branch transmission line includes a plurality of branch wires, wherein the main transmission line includes a first end contacting the memory controller and a second end contacting only a first branch wire of the branch transmission line, and wherein the memory controller connects to the memory devices through the main transmission line and the plurality of branch wires, which connect to each other in series.
This invention relates to a data storage device with an improved transmission line structure for connecting a memory controller to multiple memory devices. The device addresses signal integrity and transmission efficiency challenges in high-speed memory systems, particularly in configurations where multiple memory devices are connected to a single controller. The design features a first printed circuit board (PCB) with a main transmission line extending in a first direction, connected at one end to the memory controller and at the other end to a branch transmission line. The branch transmission line includes multiple branch wires that connect the memory devices in series to the main transmission line. An open stub extends from the main transmission line in a second direction, with one end connected to the main transmission line and the other end open. The stub's connection point is positioned closer to either the memory controller or at least one memory device, optimizing signal reflection and impedance matching. The main transmission line directly contacts the memory controller at one end and only the first branch wire at the other end, ensuring controlled signal propagation. This configuration enhances signal quality and reduces transmission losses in high-speed memory access operations.
16. The data storage device of claim 15 , further comprising: a through-substrate via formed in the first PCB; and a second PCB connected with the first PCB through the through-substrate via, wherein the open stub is formed on the second PCB which is formed on a different layer from a layer in which the first PCB is formed, and the first end of the open stub is connected to the main transmission line through the through-substrate via.
This invention relates to a data storage device with an improved signal transmission structure. The device addresses signal integrity issues in high-speed data transmission, particularly in multi-layer printed circuit board (PCB) configurations where signal reflections and impedance mismatches can degrade performance. The invention includes a main transmission line for carrying data signals and an open stub structure to enhance signal quality. The open stub is a conductive trace with one end connected to the main transmission line and the other end left open, acting as a resonant element to absorb or reflect specific signal frequencies, thereby reducing noise and improving signal integrity. The open stub is formed on a second PCB layer, distinct from the first PCB layer where the main transmission line resides. A through-substrate via connects the two PCBs, allowing the open stub to interface with the main transmission line. This multi-layer design optimizes space utilization and signal routing while maintaining high-speed data transmission efficiency. The invention is particularly useful in compact storage devices requiring reliable high-frequency signal transmission.
17. The data storage device of claim 15 , wherein a length of the open stub in the second direction is 1/K of a length of the main transmission line in the first direction, K being a natural number greater than 2.
This invention relates to data storage devices, specifically those using high-speed serial communication interfaces. The problem addressed is signal integrity degradation in high-speed data transmission due to impedance mismatches and reflections in the transmission lines. The invention improves signal quality by incorporating an open stub structure in the transmission line to mitigate reflections and ensure proper impedance matching. The data storage device includes a main transmission line for transmitting data signals, where the transmission line extends in a first direction. An open stub is connected to the main transmission line and extends in a second direction, perpendicular to the first direction. The length of the open stub in the second direction is precisely controlled to be 1/K of the length of the main transmission line in the first direction, where K is a natural number greater than 2. This specific length ratio ensures that the stub acts as a resonant structure, effectively absorbing or reflecting unwanted signal components at specific frequencies, thereby reducing signal distortion. The open stub is positioned at a location along the main transmission line where signal reflections are most problematic, such as near a connector or a transition point. The stub's length is optimized to target common high-frequency noise components, improving signal integrity without requiring additional complex circuitry. This design is particularly useful in high-speed serial interfaces, such as those found in solid-state drives (SSDs) or other storage devices, where maintaining signal quality is critical for reliable data transmission.
18. The data storage device of claim 15 , wherein the main transmission line further includes a second open stub having a first end connected to the main transmission line at the first position of the main transmission line and a second end open, and wherein the second open stub extends in a third direction opposite to the second direction.
This invention relates to data storage devices, specifically high-speed data transmission systems within such devices. The problem addressed is signal integrity degradation in high-speed data transmission lines due to impedance mismatches, reflections, and crosstalk, which can lead to data errors and reduced performance. The invention describes a data storage device with an improved transmission line structure. The main transmission line includes a first open stub extending in a first direction and a second open stub extending in a third direction opposite to a second direction. The first open stub is connected at a first position on the main transmission line, while the second open stub is also connected at the same first position but extends in the opposite direction. This configuration helps mitigate signal reflections and impedance mismatches by providing controlled signal paths that absorb or redirect unwanted reflections, thereby improving signal integrity and transmission efficiency. The transmission line may also include a ground plane and a dielectric layer, with the stubs positioned to optimize signal propagation. The stubs are designed to have specific lengths and widths to tune the impedance characteristics of the transmission line, ensuring minimal signal distortion. This design is particularly useful in high-density storage devices where multiple transmission lines operate in close proximity, reducing crosstalk and enhancing overall system reliability. The invention provides a cost-effective solution to improve data transmission performance without requiring complex or expensive modifications to existing storage device architectures.
19. The data storage device of claim 15 , wherein when the first position is closer to the memory controller, a distance between the first position and the at least one of the plurality of memory devices is at least twice a distance between the first position and the memory controller, or wherein when the first position is closer to the at least one of the plurality of memory devices, the distance between the first position and the memory controller is at least twice the distance between the first position and at least one of the plurality of memory devices.
A data storage device includes a memory controller and multiple memory devices, with a buffer positioned between them. The buffer is placed at a first position along a communication path to optimize signal integrity and reduce latency. The first position is strategically located such that if it is closer to the memory controller, the distance to the nearest memory device is at least twice the distance to the memory controller. Conversely, if the first position is closer to the memory devices, the distance to the memory controller is at least twice the distance to the nearest memory device. This arrangement ensures efficient signal transmission by minimizing signal degradation and reflection, improving data transfer reliability and performance. The buffer may include a register or other buffering circuitry to temporarily store data during transmission, further enhancing signal quality. The design addresses challenges in high-speed data communication within storage systems, particularly in maintaining signal integrity over long distances and reducing latency in data access operations.
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October 8, 2019
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