Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: a tessellation queue to store portions of a first image frame to be tessellated; and motion vector analysis circuitry to group a plurality of sub-tiles within each of a plurality of tiles at multiple levels of granularity, wherein the sub-tiles of a first level comprise pixels and the sub-tiles of each successive level comprise tiles from a previous level, the motion vector analysis circuitry to iteratively analyze motion vectors of each group of sub-tiles at each level of granularity to determine whether the motion vectors are similar in accordance with a defined threshold, the motion vector analysis circuitry to queue tiles having sub-tiles which are determined to be dissimilar to the tessellation queue, wherein the motion vector analysis circuitry is to start performing its iterative analysis on the first level, in which each sub-tile comprises a pixel.
Image processing and video compression. This invention addresses the efficient processing of image frames for tasks like video encoding by optimizing tessellation. The apparatus includes a tessellation queue for storing image portions that require tessellation. It also features motion vector analysis circuitry. This circuitry groups sub-tiles within larger tiles at various levels of detail. At the most granular level, sub-tiles consist of individual pixels. At subsequent levels, sub-tiles are composed of tiles from the preceding level. The motion vector analysis circuitry iteratively examines the motion vectors of these sub-tile groups at each granularity level. It determines if the motion vectors within a group are similar, based on a predefined threshold. Tiles containing sub-tiles with dissimilar motion vectors are then sent to the tessellation queue. The iterative analysis begins at the pixel level.
2. The apparatus of claim 1 wherein the motion vector analysis circuitry is to further queue tiles in the tessellation queue having at least one sub-tile already queued.
The invention relates to graphics processing systems, specifically to improving the efficiency of tessellation operations in rendering pipelines. The problem addressed is the inefficiency in processing tessellation tasks, particularly when handling complex geometric data that requires subdivision into smaller tiles and sub-tiles. Traditional methods often lead to redundant computations or delays due to improper queuing of tessellation tasks, impacting rendering performance. The apparatus includes motion vector analysis circuitry designed to optimize the tessellation process by intelligently managing the queuing of tiles. The circuitry analyzes motion vectors associated with the tiles to determine their relevance and priority in the rendering pipeline. A key feature is the ability to queue tiles that share at least one sub-tile already in the tessellation queue. This ensures that related tessellation tasks are grouped together, reducing redundant computations and improving processing efficiency. The tessellation queue dynamically adjusts based on the analysis, ensuring that the most relevant tiles are processed first, which enhances overall rendering performance and reduces latency. The system is particularly useful in real-time rendering applications where efficient tessellation is critical for high-quality visual output.
3. The apparatus of claim 2 wherein the motion vector analysis circuitry is to merge sub-tiles of a group which are determined to be similar, each merged group of sub-tiles to be analyzed as an individual sub-tile at a next level of granularity.
This invention relates to video processing, specifically to motion vector analysis in video encoding or decoding systems. The problem addressed is the computational inefficiency of analyzing motion vectors at fine granularity, which can lead to excessive processing time and resource usage without significant quality improvements. The apparatus includes motion vector analysis circuitry designed to optimize motion vector processing by merging sub-tiles of a video frame that are determined to be similar. These sub-tiles are grouped together, and the merged group is then analyzed as a single, larger sub-tile at a coarser level of granularity. This hierarchical approach reduces the number of individual sub-tiles that must be processed, improving efficiency while maintaining accuracy. The similarity determination between sub-tiles can be based on factors such as motion vector magnitude, direction, or other statistical properties. By dynamically adjusting the granularity of analysis, the system avoids unnecessary computations on redundant or similar sub-tiles, leading to faster encoding or decoding without degrading video quality. This method is particularly useful in real-time applications where processing speed is critical.
4. The apparatus of claim 1 wherein, upon performing its iterative analysis on each group of pixels at the first level, the motion vector analysis circuitry is to move to each next level in sequence from the first level to perform the grouping, analyzing motion vectors, and queuing operations, until a final level is reached.
This invention relates to motion vector analysis in video processing, specifically for improving efficiency in motion estimation by hierarchically analyzing pixel groups at multiple resolution levels. The problem addressed is the computational complexity of traditional motion estimation techniques, which often require processing large amounts of pixel data at full resolution, leading to high processing demands and latency. The apparatus includes motion vector analysis circuitry configured to perform iterative analysis on groups of pixels at a first resolution level. The circuitry groups pixels into blocks, analyzes motion vectors for each block, and queues the results for further processing. After completing analysis at the first level, the circuitry proceeds sequentially to the next higher resolution level, repeating the grouping, motion vector analysis, and queuing operations. This hierarchical approach continues until a final, highest resolution level is reached, where the most detailed motion vectors are computed. By progressively refining motion vectors from lower to higher resolution levels, the system reduces computational overhead while maintaining accuracy. The hierarchical structure allows for efficient parallel processing and early termination of unnecessary computations, optimizing resource usage in real-time video applications.
5. The apparatus of claim 1 further comprising: tessellation circuitry to perform tessellation on tiles queued in the tessellation queue.
The invention relates to a graphics processing apparatus designed to improve rendering efficiency by managing tessellation operations. The apparatus includes a tessellation queue that stores tiles awaiting tessellation, where each tile represents a portion of a geometric surface to be subdivided. The tessellation circuitry performs the actual tessellation process, dividing each tile into smaller geometric elements (e.g., triangles or patches) to enhance rendering detail. This circuitry operates on the tiles stored in the queue, ensuring that the tessellation process is efficiently managed and executed. The apparatus may also include additional components, such as a tessellation queue manager that controls the flow of tiles into and out of the queue, ensuring optimal utilization of the tessellation circuitry. The overall system is designed to reduce processing bottlenecks by dynamically adjusting the tessellation workload based on available resources, improving real-time rendering performance in graphics applications. The invention addresses the challenge of efficiently handling complex geometric subdivisions in real-time rendering, particularly in applications requiring high-detail visual output, such as gaming, virtual reality, or computer-aided design.
6. The apparatus of claim 5 further comprising: a hull shader to read tiles queued in the tessellation queue and to decode the tiles and set up tessellation of the tiles by the tessellation circuitry.
This invention relates to graphics processing systems, specifically improving the efficiency of tessellation operations in real-time rendering pipelines. The problem addressed is the computational overhead and latency in processing tessellated geometry, particularly when handling large or complex scenes with high-resolution details. Traditional approaches often suffer from bottlenecks in tile management and tessellation setup, leading to inefficiencies in memory access and shader execution. The apparatus includes a hull shader that interfaces with a tessellation queue to manage and process geometric tiles. The hull shader reads tiles queued in the tessellation queue, decodes the tile data, and prepares the tiles for tessellation by the tessellation circuitry. This involves parsing tile attributes, determining tessellation factors, and generating control data for the tessellation stage. The tessellation circuitry then uses this setup to subdivide the tiles into finer geometric primitives, such as triangles or patches, for further processing by domain shaders. The hull shader optimizes the tessellation pipeline by reducing latency in tile processing and ensuring efficient data flow between the queue and the tessellation circuitry. This approach minimizes redundant computations and improves the overall performance of the graphics rendering pipeline, particularly in applications requiring high-detail geometry, such as virtual reality, gaming, or CAD modeling. The system dynamically adjusts tessellation parameters based on tile complexity, balancing quality and performance.
7. The apparatus of claim 6 further comprising: a domain shader to apply transformations on vertices resulting from the tessellation to obtain normalized device coordinates in a current frame.
This invention relates to graphics processing, specifically to a system for generating and transforming geometric data in real-time rendering pipelines. The problem addressed is the need for efficient vertex processing after tessellation to ensure accurate and optimized rendering in normalized device coordinates (NDC) for each frame. The apparatus includes a tessellation unit that subdivides input geometry into finer detail, producing vertices that require further processing. A domain shader then applies transformations to these vertices, converting them into normalized device coordinates for the current frame. This ensures that the rendered geometry is correctly positioned and scaled within the viewport. The domain shader may perform additional operations such as perspective division or other coordinate transformations to prepare the vertices for rasterization. The system is designed to handle dynamic geometry adjustments in real-time, ensuring smooth and accurate rendering across frames. By integrating tessellation with domain shading, the apparatus enables high-quality geometric detail while maintaining computational efficiency. This approach is particularly useful in applications requiring adaptive geometry refinement, such as real-time 3D rendering in gaming, virtual reality, or simulation environments. The invention optimizes the pipeline by reducing redundant calculations and ensuring consistent vertex processing for each frame.
8. The apparatus of claim 3 further comprising: a temporary inter-level data buffer to store data related to the analysis of motion vectors across the levels.
The invention relates to video processing systems, specifically apparatuses for analyzing motion vectors in video data across multiple hierarchical levels. The problem addressed is the need for efficient storage and management of intermediate data during motion vector analysis, which is critical for tasks like video compression, motion estimation, and frame interpolation. Traditional systems often lack dedicated buffering mechanisms, leading to inefficiencies in processing and increased computational overhead. The apparatus includes a temporary inter-level data buffer designed to store data related to the analysis of motion vectors across different hierarchical levels. This buffer facilitates the transfer and temporary storage of motion vector data between levels, ensuring smooth and efficient processing. The buffer is integrated with a motion vector analysis module that processes motion vectors at multiple levels of a hierarchical structure, such as in a pyramid-based motion estimation system. The analysis module generates motion vector data at each level, which is then stored in the buffer before being passed to higher or lower levels for further processing. This intermediate storage prevents data loss and reduces the need for repeated calculations, improving overall system performance. The apparatus may also include a motion vector refinement module that refines motion vectors based on the data stored in the buffer, enhancing accuracy and reducing artifacts in the final output. The buffer is dynamically managed to optimize storage and retrieval, ensuring real-time processing capabilities. This invention is particularly useful in video encoding and decoding systems where motion vector analysis is a critical step.
9. The apparatus of claim 8 wherein the motion vector analysis circuitry is to store dissimilarity data related to the sub-tiles in the temporary inter-level data buffer.
This invention relates to video processing, specifically to motion vector analysis in video encoding or decoding systems. The problem addressed is efficiently managing and analyzing motion vectors to improve compression efficiency and reduce computational overhead in video coding. The apparatus includes motion vector analysis circuitry that processes motion vectors for video frames divided into sub-tiles. The circuitry analyzes these motion vectors to determine dissimilarity data, which quantifies differences in motion characteristics between adjacent sub-tiles. This dissimilarity data is stored in a temporary inter-level data buffer, allowing for efficient access and reuse during subsequent encoding or decoding stages. The buffer enables hierarchical motion analysis, where motion information from larger tiles is used to refine motion estimation at smaller sub-tile levels, improving prediction accuracy while reducing redundant computations. The motion vector analysis circuitry may also include a motion vector predictor that generates predicted motion vectors for sub-tiles based on stored dissimilarity data, further optimizing the encoding process. The apparatus may also include a motion vector buffer that stores motion vectors for multiple sub-tiles, enabling temporal prediction across frames. The temporary inter-level data buffer ensures that dissimilarity data is retained for use in subsequent processing steps, enhancing the overall efficiency of the video coding system. This approach reduces bandwidth and computational requirements while maintaining high-quality motion prediction.
10. A method comprising: grouping a plurality of sub-tiles within each of a plurality of tiles of an image frame at multiple levels of granularity, wherein the sub-tiles of a first level comprise pixels and the sub-tiles of each successive level comprise tiles from a previous level, analyzing motion vectors of each group of sub-tiles at each level of granularity to determine whether the motion vectors are similar in accordance with a defined threshold, wherein the analysis is to be initiated on the first level, in which each sub-tile comprises a pixel; and queuing tiles having sub-tiles which are determined to be dissimilar to a tessellation queue.
This invention relates to image processing, specifically to methods for analyzing motion vectors in video frames to identify regions with dissimilar motion patterns. The problem addressed is efficiently detecting and prioritizing areas of an image frame that exhibit significant motion differences, which is useful for tasks like video compression, object tracking, or adaptive encoding. The method involves hierarchically grouping sub-tiles within tiles of an image frame at multiple levels of granularity. At the finest level, sub-tiles consist of individual pixels, while each subsequent level groups tiles from the previous level into larger sub-tiles. Motion vectors for each group of sub-tiles are analyzed at every level to determine similarity based on a defined threshold. The analysis begins at the pixel level and progresses through coarser levels. If motion vectors within a group are dissimilar, the containing tile is added to a tessellation queue for further processing. This hierarchical approach allows efficient identification of motion boundaries without redundant computations, improving processing speed and accuracy in motion analysis tasks.
11. The method of claim 10 further comprising: queueing tiles to the tessellation queue which have at least one sub-tile already queued.
This invention relates to graphics processing, specifically optimizing tessellation operations in a graphics pipeline. The problem addressed is inefficient tessellation processing, where redundant or unnecessary tessellation operations are performed, leading to wasted computational resources and reduced performance. The method involves a tessellation queue that manages the order in which tiles are processed. Tiles are divided into smaller sub-tiles, and the method ensures that only tiles with at least one sub-tile already queued are added to the tessellation queue. This prevents redundant tessellation operations by prioritizing tiles that are already partially processed, reducing unnecessary computations and improving efficiency. The method also includes determining whether a tile is adjacent to a previously processed tile and, if so, adding it to the tessellation queue. This ensures that adjacent tiles are processed in a coherent manner, further optimizing the tessellation process. The method may also involve tracking the status of tiles and sub-tiles to ensure that only relevant tiles are processed, avoiding redundant work. By selectively queuing tiles based on their adjacency and partial processing status, the method reduces the computational overhead of tessellation, improving graphics rendering performance and efficiency. This approach is particularly useful in real-time rendering applications where minimizing processing time is critical.
12. The method of claim 11 further comprising: merging sub-tiles of a group which are determined to be similar, based on the defined threshold, each merged group of sub-tiles to be analyzed as an individual sub-tile at a next level of granularity.
This invention relates to image or data processing, specifically methods for analyzing and merging similar sub-tiles within a larger tile to improve computational efficiency. The problem addressed is the inefficiency in processing large datasets or images when analyzing them at a fine granularity, which can be computationally expensive and time-consuming. The solution involves grouping and merging sub-tiles that are determined to be similar based on a predefined threshold, allowing them to be treated as a single sub-tile at a higher level of granularity. This reduces the number of individual sub-tiles that need to be processed, thereby optimizing resource usage and speeding up analysis. The method first divides a larger tile into smaller sub-tiles. Each sub-tile is then analyzed to determine its similarity to others within a defined group. If the similarity exceeds the threshold, the sub-tiles are merged into a single, larger sub-tile. This merged sub-tile is then processed as an individual unit in subsequent analysis steps, effectively reducing the granularity of the data being processed. The threshold for similarity can be adjusted based on the desired level of detail or computational constraints. This approach is particularly useful in applications such as image recognition, data compression, or large-scale data analysis where efficiency is critical.
13. The method of claim 10 wherein, upon performing the iterative analysis on each group of pixels at the first level, progressing to each next level in sequence from the first level to perform the grouping, analyzing motion vectors, and queuing, until a final level is reached.
This invention relates to a multi-level motion analysis system for processing video data. The system addresses the challenge of efficiently detecting and analyzing motion in video frames, particularly in scenarios where motion patterns vary across different regions of the frame. Traditional single-level motion analysis methods often fail to capture fine-grained motion details or scale effectively to large video frames. The method involves a hierarchical, multi-level approach to motion analysis. Initially, the video frame is divided into groups of pixels at a first level of granularity. Motion vectors are then calculated for each group, representing the direction and magnitude of motion within that region. These motion vectors are analyzed iteratively, and groups exhibiting similar motion characteristics are queued for further processing. The analysis progresses sequentially through each subsequent level, refining the grouping of pixels and recalculating motion vectors at increasingly finer resolutions. This iterative process continues until a final level is reached, where the motion vectors are fully analyzed and refined. The hierarchical structure allows for efficient computation while preserving detailed motion information, making it suitable for applications such as video compression, object tracking, and motion-based event detection. The system dynamically adapts to varying motion patterns, improving accuracy and computational efficiency compared to traditional single-level approaches.
14. The method of claim 10 further comprising: performing tessellation on tiles queued in the tessellation queue.
This invention relates to graphics processing, specifically optimizing the handling of tessellation operations in a graphics pipeline. The problem addressed is the inefficient processing of tessellation tasks, which can lead to bottlenecks and reduced performance in real-time rendering applications. The method involves managing a tessellation queue that stores tiles awaiting tessellation. Tiles are geometric units that require subdivision into smaller patches for detailed rendering. The method further includes performing tessellation on these queued tiles, where tessellation is the process of dividing a surface into smaller, more manageable geometric patches. This step ensures that the tessellation workload is distributed efficiently, preventing delays and improving rendering performance. The method may also involve prioritizing tiles based on factors such as visibility, proximity to the camera, or computational complexity. By dynamically adjusting the order of tessellation operations, the system can optimize resource usage and reduce unnecessary processing of off-screen or low-priority tiles. Additionally, the method may include monitoring the tessellation queue to balance the workload across multiple processing units, ensuring that no single unit is overwhelmed while others remain idle. The invention is particularly useful in applications requiring high-detail rendering, such as video games, virtual reality, and computer-aided design, where efficient tessellation is critical for maintaining smooth frame rates and visual fidelity. By optimizing the tessellation process, the method enhances overall system performance and responsiveness.
15. The method of claim 14 further comprising: reading and decoding tiles queued in the tessellation queue in preparation for tessellation.
This invention relates to graphics processing, specifically methods for optimizing tessellation operations in a graphics pipeline. The problem addressed is the inefficient handling of tessellation tasks, which can lead to bottlenecks in rendering performance. The method involves managing a tessellation queue that stores tiles representing geometric data to be processed. The method further includes reading and decoding these tiles from the queue in preparation for tessellation. This step ensures that the data is properly formatted and ready for the tessellation stage, where the geometric primitives are subdivided into smaller, more detailed elements. The method may also involve prioritizing tiles based on factors such as rendering priority or data complexity, ensuring that the most critical or computationally intensive tasks are processed first. By efficiently managing the tessellation queue and preparing the tiles in advance, the method reduces latency and improves overall rendering performance in graphics applications. The invention is particularly useful in real-time rendering systems, such as video games or virtual reality applications, where smooth and fast rendering is essential.
16. The method of claim 15 further comprising: applying transformations on vertices resulting from the tessellation to obtain normalized device coordinates in a current frame.
This invention relates to computer graphics processing, specifically to methods for optimizing vertex transformations in real-time rendering pipelines. The problem addressed is the computational overhead of repeatedly transforming vertices from object space to normalized device coordinates (NDC) in each frame, which can degrade performance in dynamic scenes with frequent geometry updates. The method involves a multi-step process. First, a tessellation operation is performed on input geometry to generate additional vertices, subdividing the original mesh into smaller primitives. These tessellated vertices are then processed through a series of transformations to convert them into normalized device coordinates for the current frame. The transformations account for the current frame's view and projection matrices, ensuring accurate positioning in the rendering pipeline. This approach reduces redundant calculations by leveraging tessellation results and applying frame-specific adjustments only when necessary, improving rendering efficiency without sacrificing visual fidelity. The method is particularly useful in applications requiring high-performance rendering, such as video games, virtual reality, and real-time simulations.
17. The method of claim 12 further comprising: storing data related to the analysis of motion vectors across the levels in an inter-level storage buffer.
This invention relates to video processing, specifically analyzing motion vectors across different hierarchical levels of a video encoding or decoding system. The problem addressed is the need for efficient storage and management of motion vector data during inter-level processing, which is critical for tasks like motion estimation, prediction, and compression. The invention provides a method that includes storing data related to the analysis of motion vectors across multiple levels in an inter-level storage buffer. This buffer facilitates the transfer and processing of motion vector information between different hierarchical stages, improving accuracy and reducing computational overhead. The method may involve generating motion vectors at one level, analyzing their relationships with vectors from other levels, and storing intermediate results in the buffer to optimize subsequent processing steps. The inter-level storage buffer ensures that motion vector data is accessible and efficiently managed, enhancing the overall performance of video encoding or decoding systems. This approach is particularly useful in applications requiring high-quality motion analysis, such as video compression, object tracking, and motion compensation.
18. The method of claim 17 wherein dissimilarity data related to the sub-tiles is to be stored in the temporary inter-level data buffer.
This invention relates to image or video processing systems that use hierarchical tile-based compression techniques. The problem addressed is the efficient storage and management of intermediate dissimilarity data during multi-level compression, particularly when processing sub-tiles within a larger tile structure. Dissimilarity data represents differences between sub-tiles or their encoded representations, which is critical for maintaining compression efficiency and quality across hierarchical levels. The method involves storing dissimilarity data associated with sub-tiles in a temporary inter-level data buffer. This buffer acts as an intermediate storage mechanism between compression levels, allowing the system to retain necessary information for subsequent processing steps without permanently storing it in the final compressed output. The buffer ensures that dissimilarity data is accessible when needed for higher-level compression decisions, such as merging or refining sub-tiles, while avoiding redundant storage or excessive memory usage. The technique is particularly useful in systems where sub-tiles are processed independently at lower levels before being combined or further compressed at higher levels. By temporarily storing dissimilarity data, the system can dynamically adjust compression parameters or strategies based on the relationships between sub-tiles, improving overall compression efficiency and quality. The buffer may be implemented in hardware or software, depending on the system architecture, and can be optimized for fast access and minimal overhead. This approach reduces the computational and memory demands of hierarchical compression while maintaining the integrity of the compressed data.
19. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of: grouping a plurality of sub-tiles within each of a plurality of tiles of an image frame at multiple levels of granularity, wherein the sub-tiles of a first level comprise pixels and the sub-tiles of each successive level comprise tiles from a previous level, analyzing motion vectors of each group of sub-tiles at each level of granularity to determine whether the motion vectors are similar in accordance with a defined threshold, wherein the analysis is to be initiated on the first level, in which each sub-tile comprises a pixel; and queuing tiles having sub-tiles which are determined to be dissimilar to a tessellation queue.
This invention relates to image processing, specifically optimizing motion vector analysis for video encoding or compression. The problem addressed is efficiently identifying and processing regions of an image frame with significant motion changes, which is critical for reducing computational overhead in video encoding pipelines. The system groups pixels and larger sub-tiles within an image frame into hierarchical structures at multiple levels of granularity. At the finest level, sub-tiles consist of individual pixels. Each successive level aggregates sub-tiles from the previous level into larger tiles. The system analyzes motion vectors for each group of sub-tiles at every level to determine if the vectors are similar based on a predefined threshold. The analysis begins at the pixel level and progresses through coarser levels. If motion vectors within a tile's sub-tiles are found to be dissimilar, the entire tile is added to a tessellation queue for further processing. This hierarchical approach allows the system to efficiently identify regions with complex motion patterns while minimizing unnecessary computations on uniform areas. The method improves encoding efficiency by focusing computational resources on areas with significant motion changes.
20. The non-transitory machine-readable medium of claim 19 further comprising program code to cause the machine to perform the operations of: queueing tiles to the tessellation queue which have at least one sub-tile already queued.
This invention relates to computer graphics rendering, specifically optimizing the tessellation process in graphics processing units (GPUs). The problem addressed is inefficient tessellation, where redundant or unnecessary computations occur when processing geometric tiles, leading to performance bottlenecks. The solution involves a method for prioritizing and managing tessellation operations by intelligently queuing tiles based on their sub-tile dependencies. The system includes a tessellation queue that stores geometric tiles awaiting processing. The key improvement is the ability to queue tiles that have at least one sub-tile already in the queue, ensuring that dependent sub-tiles are processed in an optimal order. This reduces redundant computations by avoiding reprocessing of overlapping or dependent sub-tiles. The method dynamically tracks sub-tile dependencies and prioritizes tiles accordingly, improving rendering efficiency and performance. The invention also includes a machine-readable medium containing program code to execute these operations. The code ensures that tiles with existing sub-tile dependencies are processed first, minimizing redundant work and optimizing GPU resource utilization. This approach is particularly useful in real-time rendering applications where performance and efficiency are critical.
21. The non-transitory machine-readable medium of claim 20 further comprising program code to cause the machine to perform the operations of: merging sub-tiles of a group which are determined to be similar, based on the defined threshold, each merged group of sub-tiles to be analyzed as an individual sub-tile at a next level of granularity.
This invention relates to image or data processing systems that handle large datasets by dividing them into smaller sub-tiles for analysis. The problem addressed is the inefficiency in processing when similar sub-tiles are analyzed separately, leading to redundant computations and increased processing time. The solution involves a method for merging sub-tiles that are determined to be similar based on a predefined threshold. Once merged, these groups of sub-tiles are treated as a single sub-tile at the next level of granularity, reducing the number of individual analyses required. The similarity determination may involve comparing features, patterns, or other characteristics of the sub-tiles. By merging similar sub-tiles, the system optimizes processing by minimizing redundant operations and improving computational efficiency. This approach is particularly useful in applications such as image recognition, data compression, or large-scale data analysis where granularity levels are adjusted dynamically. The method ensures that only distinct sub-tiles are processed individually, while similar ones are grouped to streamline analysis. The threshold for similarity can be adjusted based on the specific requirements of the application, allowing flexibility in balancing accuracy and performance.
22. The non-transitory machine-readable medium of claim 19 wherein, upon performing the iterative analysis on each group of pixels at the first level, progressing to each next level in sequence from the first level to perform the grouping, analyzing motion vectors, and queuing, until a final level is reached.
This invention relates to image processing, specifically a method for analyzing motion in video frames using hierarchical pixel grouping and motion vector analysis. The problem addressed is efficiently detecting and tracking motion across video frames while reducing computational complexity. The solution involves a multi-level hierarchical approach where pixels are grouped at different levels of granularity, motion vectors are analyzed, and results are queued for further processing. The process begins by dividing an image into groups of pixels at a first level. Motion vectors for these groups are analyzed to detect movement. The results are then queued for subsequent processing. The analysis progresses iteratively through each subsequent level, refining the grouping of pixels and analyzing motion vectors at each level until a final level is reached. This hierarchical approach allows for efficient motion detection by leveraging coarse-to-fine analysis, reducing computational overhead compared to pixel-by-pixel processing. The method ensures that motion vectors are analyzed at progressively finer levels of detail, improving accuracy while maintaining computational efficiency. The queuing mechanism ensures that results from each level are properly managed for further processing. This technique is particularly useful in applications requiring real-time motion analysis, such as video compression, surveillance, and object tracking.
23. The non-transitory machine-readable medium of claim 19 further comprising program code to cause the machine to perform the operations of: performing tessellation on tiles queued in the tessellation queue.
This invention relates to computer graphics processing, specifically optimizing tessellation operations in a graphics pipeline. The problem addressed is inefficient handling of tessellation tasks, which can lead to bottlenecks in rendering performance. The solution involves a system that dynamically manages tessellation workloads by queuing tiles for processing and executing tessellation operations on those tiles in an optimized manner. The system includes a tessellation queue that stores tiles awaiting tessellation, where each tile represents a portion of a geometric surface to be subdivided. The system further includes a tessellation engine that retrieves tiles from the queue and performs tessellation, which involves subdividing the tiles into smaller geometric primitives (e.g., triangles) to increase rendering detail. The tessellation engine may adjust the level of subdivision based on factors such as screen space error metrics or application-specific requirements. Additionally, the system may include a pre-tessellation stage that prepares tiles for processing, such as by determining optimal tessellation factors or culling tiles that do not contribute to the final rendered image. The system may also include a post-tessellation stage that processes the subdivided primitives, such as by applying vertex shading or preparing them for rasterization. By dynamically managing tessellation workloads, the system improves rendering efficiency, reduces bottlenecks, and enhances visual quality in real-time graphics applications.
24. The non-transitory machine-readable medium of claim 23 further comprising program code to cause the machine to perform the operations of: reading and decoding tiles queued in the tessellation queue in preparation for tessellation.
The invention relates to computer graphics processing, specifically to systems and methods for managing and processing tessellation operations in a graphics pipeline. The problem addressed is the efficient handling of tessellation tasks, particularly in scenarios where multiple tiles or patches need to be processed in a structured manner. The solution involves a non-transitory machine-readable medium containing program code that enables a machine to perform tessellation operations. The medium includes program code to manage a tessellation queue, which organizes and prioritizes tessellation tasks. Additionally, the program code reads and decodes tiles queued in the tessellation queue, preparing them for tessellation. This preparation step involves interpreting the data structure of each tile, extracting necessary information, and ensuring the data is in a suitable format for subsequent tessellation. The system optimizes the tessellation process by systematically processing queued tiles, reducing bottlenecks and improving rendering performance. The invention is particularly useful in real-time graphics applications, such as video games or virtual reality, where efficient tessellation is critical for high-quality visual output.
25. The non-transitory machine-readable medium of claim 24 further comprising program code to cause the machine to perform the operations of: applying transformations on vertices resulting from the tessellation to obtain normalized device coordinates in a current frame.
This invention relates to computer graphics processing, specifically optimizing the transformation of geometric data in real-time rendering pipelines. The problem addressed is the computational overhead and inefficiency in converting tessellated vertices into normalized device coordinates (NDC) for display, which is a critical step in modern graphics rendering but can introduce latency and performance bottlenecks. The invention describes a system that includes a non-transitory machine-readable medium storing program code to perform tessellation of geometric primitives into vertices and then apply transformations to these vertices to achieve normalized device coordinates. The transformations account for the current frame's rendering context, ensuring accurate and efficient conversion of vertex data. The process involves mathematical operations that adjust vertex positions, orientations, and other attributes to fit within the standardized NDC space, which is essential for subsequent rasterization and display. The solution optimizes the transformation pipeline by integrating tessellation and coordinate normalization into a unified workflow, reducing redundant computations and improving rendering performance. This is particularly useful in applications requiring high frame rates, such as gaming, virtual reality, and real-time simulations, where minimizing latency is crucial. The invention ensures that the transformed vertices are correctly mapped to the NDC space for each frame, maintaining visual fidelity while enhancing processing efficiency.
26. The non-transitory machine-readable medium of claim 21 further comprising program code to cause the machine to perform the operations of: storing data related to the analysis of motion vectors across the levels in an inter-level storage buffer.
The invention relates to video processing systems, specifically methods for analyzing motion vectors in video encoding or decoding. Motion vectors are used to describe the movement of objects between frames, and their analysis is critical for efficient compression and reconstruction of video data. A challenge in video processing is managing the computational complexity and memory usage when analyzing motion vectors across different hierarchical levels, such as in multi-level motion estimation or adaptive resolution encoding. The invention addresses this by introducing an inter-level storage buffer to store data related to motion vector analysis across these levels. This buffer allows intermediate results from one level to be efficiently passed to another, reducing redundant calculations and improving processing speed. The buffer may store motion vector predictions, residuals, or other derived data, enabling smoother transitions between levels and enhancing accuracy. By centralizing this data, the system avoids repeated computations, conserves memory bandwidth, and optimizes overall performance. The invention is particularly useful in real-time video encoding/decoding applications where efficiency is critical.
27. The non-transitory machine-readable medium of claim 26 wherein dissimilarity data related to the sub-tiles is to be stored in the temporary inter-level data buffer.
The invention relates to image processing systems that use hierarchical data structures to analyze and compress images. A common challenge in such systems is efficiently managing intermediate data during multi-level processing, particularly when comparing sub-tiles across different resolution levels. The invention addresses this by storing dissimilarity data—metrics that quantify differences between sub-tiles—in a temporary inter-level data buffer. This buffer acts as a staging area, allowing the system to retain comparison results between processing stages without overwriting or losing critical intermediate data. The buffer ensures that dissimilarity metrics, which may be used for tasks like motion estimation, compression, or image reconstruction, are preserved until needed for further processing. By isolating this data in a dedicated buffer, the system avoids unnecessary memory access delays and reduces computational overhead. The invention is particularly useful in real-time applications where low-latency processing is essential, such as video encoding or computer vision tasks. The buffer may be implemented in hardware or software, depending on system requirements, and can be dynamically resized to accommodate varying workloads. This approach improves efficiency by minimizing redundant calculations and ensuring seamless data flow between processing levels.
Unknown
December 3, 2019
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