10516439

Interference Testing

PublishedDecember 24, 2019
Assigneenot available in USPTO data we have
Technical Abstract

Patent Claims
9 claims

Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.

Claim 1

Original Legal Text

1. A controller, comprising logic, at least partially including hardware logic, configured to: receive a predetermined reload rate parameter and a save rate parameter from a memory location; generate a first set of repeating pseudo-random patterns by reloading a first seed according to the predetermined reload rate parameter; and transmit the first set of repeating pseudo-random patterns on a first lane of a communication interconnect, wherein the logic is further configured to save the first seed in accordance with the save rate.

Plain English Translation

A controller system is designed to enhance data transmission security and reliability in communication interconnects by generating and transmitting repeating pseudo-random patterns. The system addresses the need for secure and controlled data transmission in high-speed communication links, where predictable or static data patterns can be vulnerable to interception or interference. The controller includes hardware logic that receives configuration parameters, including a reload rate parameter and a save rate parameter, from a memory location. These parameters dictate how frequently the system reloads a seed value to generate new pseudo-random patterns and how often the seed is saved for future use. The controller generates a first set of repeating pseudo-random patterns by reloading a first seed according to the specified reload rate. These patterns are then transmitted on a first lane of a communication interconnect. The seed is saved at intervals defined by the save rate parameter to ensure continuity and consistency in pattern generation. This approach allows for controlled, repeatable pseudo-random data transmission, which can be used for testing, encryption, or error detection in communication systems. The hardware-based implementation ensures low-latency and high-performance operation, making it suitable for high-speed interconnects.

Claim 2

Original Legal Text

2. The controller of claim 1 , wherein the logic is configured to: generate a first pseudo-random pattern; and repeat a subset of the first pseudo-random pattern in accordance with the predetermined reload rate parameter; and transmit the subset of the pseudo-random pattern on the communication interconnect.

Plain English Translation

A controller for managing communication on an interconnect system addresses the challenge of efficiently transmitting data while maintaining signal integrity and minimizing interference. The controller includes logic that generates a first pseudo-random pattern, which is a sequence of data designed to reduce electromagnetic interference and improve signal quality. To optimize transmission, the logic repeats a subset of this pseudo-random pattern at a predetermined reload rate, ensuring consistent and controlled data flow. The subset is then transmitted over the communication interconnect, which may be a bus or other data transmission medium. This approach allows for flexible and adaptive data transmission, balancing performance and reliability. The pseudo-random pattern and its repetition help mitigate issues like signal distortion and crosstalk, which are common in high-speed communication systems. The reload rate parameter can be adjusted to suit different operating conditions, making the system adaptable to various environments and requirements. This method enhances data transmission efficiency while maintaining signal integrity, making it suitable for applications in computing, networking, and other high-speed communication systems.

Claim 3

Original Legal Text

3. The controller of claim 1 , wherein the logic is configured to execute at least one of: a predetermined number of testing loops; or a predetermined wait period.

Plain English Translation

A system for controlling a testing process involves a controller with logic to manage the execution of tests. The controller is designed to handle testing operations in a structured manner, ensuring that tests are performed efficiently and reliably. The logic within the controller can be configured to execute tests in at least one of two ways: either by running a predetermined number of testing loops or by waiting for a predetermined wait period before proceeding. The testing loops allow for repeated execution of tests to verify consistency and reliability, while the wait period ensures that tests are conducted at appropriate intervals, preventing premature or overlapping test executions. This approach helps in maintaining the integrity of the testing process, whether the focus is on repetitive validation or scheduled testing. The controller's flexibility in choosing between these methods allows for adaptability to different testing scenarios, ensuring that the system can be tailored to specific requirements. The logic ensures that tests are executed in a controlled environment, minimizing errors and maximizing the accuracy of the results. This system is particularly useful in automated testing environments where consistency and timing are critical.

Claim 4

Original Legal Text

4. An electronic device, comprising: at least one processing component; and a controller, comprising: logic, at least partially including hardware logic, configured to: receive a predetermined reload rate parameter and a save rate parameter from a memory location; generate a first set of repeating pseudo-random patterns by reloading a first seed according to the predetermined reload rate parameter; and transmit the first set of repeating pseudo-random patterns on a first lane of a communication interconnect, wherein the logic is further configured to save the first seed in accordance with the save rate.

Plain English Translation

This invention relates to electronic devices with enhanced communication interconnect security. The problem addressed is ensuring secure data transmission over communication interconnects by generating and transmitting pseudo-random patterns to detect and prevent potential security threats such as side-channel attacks or data leakage. The solution involves an electronic device with a controller that generates repeating pseudo-random patterns using a seed value, which is periodically reloaded and saved at configurable rates to maintain unpredictability while allowing recovery if needed. The controller includes hardware logic to receive reload and save rate parameters from memory, generate pseudo-random patterns by reloading a seed at the specified reload rate, and transmit these patterns on a communication interconnect lane. The seed is saved at a separate save rate to balance security and recoverability. This approach ensures that the pseudo-random patterns remain unpredictable to potential attackers while allowing the system to recover the seed if necessary, thus enhancing the security of data transmission over the interconnect. The hardware logic implementation ensures efficient and reliable execution of these security measures.

Claim 5

Original Legal Text

5. The electronic device of claim 4 , wherein the logic is configured to: generate a first pseudo-random pattern; and repeat a subset of the first pseudo-random pattern in accordance with the predetermined reload rate parameter; and transmit the subset of the pseudo-random pattern on the communication interconnect.

Plain English Translation

This invention relates to electronic devices with logic for generating and transmitting pseudo-random patterns on a communication interconnect. The problem addressed is the need for controlled, repeatable pseudo-random signal transmission to test or verify interconnect performance while maintaining randomness within defined constraints. The electronic device includes logic that generates a first pseudo-random pattern and repeats a subset of this pattern at a predetermined reload rate. The subset is transmitted on the communication interconnect. The logic may also generate a second pseudo-random pattern and repeat a subset of this pattern at a different reload rate, allowing for variable pattern repetition. The device can adjust the reload rate dynamically based on a control signal, enabling flexible testing scenarios. The logic may further include a pattern generator to produce the pseudo-random patterns and a multiplexer to select between different patterns or subsets for transmission. The device ensures that the transmitted patterns remain pseudo-random while allowing controlled repetition to meet specific testing or verification requirements. This approach balances randomness with predictability, useful for interconnect diagnostics, signal integrity testing, or protocol validation.

Claim 6

Original Legal Text

6. The controller of claim 4 , wherein the logic is configured to execute at least one of: a predetermined number of testing loops; or a predetermined wait period.

Plain English Translation

A system for controlling a process includes a controller with logic to manage testing operations. The controller is designed to handle scenarios where a process requires repeated testing or a waiting period before proceeding. The logic within the controller can be configured to either execute a predetermined number of testing loops or enforce a predetermined wait period before allowing further actions. This ensures that the process adheres to specific testing or timing requirements, improving reliability and consistency. The controller may also include communication interfaces to interact with external systems, such as sensors or actuators, to gather data or trigger actions based on the testing results. The system is particularly useful in automated manufacturing, quality control, or any application where precise testing or timing is critical. By allowing configurable testing loops or wait periods, the controller provides flexibility in adapting to different process requirements while maintaining control over the testing procedure.

Claim 7

Original Legal Text

7. A computer program product comprising logic instructions stored on a non-transitory computer readable medium which, when executed by a controller, configure the controller to: receive a predetermined reload rate parameter and a save rate parameter from a memory location; generate a first set of repeating pseudo-random patterns by reloading a first seed according to the predetermined reload rate parameter; and transmit the first set of repeating pseudo-random patterns on a first lane of a communication interconnect, wherein the logic instructions configure the controller to save the first seed in accordance with the save rate.

Plain English Translation

This invention relates to a system for generating and transmitting repeating pseudo-random patterns in a communication interconnect. The problem addressed is the need for controlled and repeatable pseudo-random pattern generation in communication systems, particularly for testing and validation purposes. The invention provides a computer program product with logic instructions stored on a non-transitory computer-readable medium. When executed by a controller, the instructions configure the controller to receive a reload rate parameter and a save rate parameter from a memory location. The controller then generates a first set of repeating pseudo-random patterns by reloading a first seed according to the predetermined reload rate parameter. The generated patterns are transmitted on a first lane of a communication interconnect. The logic instructions also configure the controller to save the first seed in accordance with the save rate parameter. This ensures that the pseudo-random patterns can be regenerated later for testing or analysis. The system allows for flexible control over pattern generation and storage, enabling precise testing and validation of communication interconnects. The invention may be used in high-speed data transmission systems where repeatable and controlled pseudo-random pattern generation is required.

Claim 8

Original Legal Text

8. The computer program product of claim 7 , wherein the logic is further configured to: generate a first pseudo-random pattern; and repeat a subset of the first pseudo-random pattern in accordance with the predetermined reload rate parameter; and transmit the subset of the pseudo-random pattern on the communication interconnect.

Plain English Translation

This invention relates to a computer program product for managing data transmission on a communication interconnect, particularly in systems where predictable or repetitive data patterns can lead to security vulnerabilities or performance issues. The invention addresses the problem of ensuring secure and efficient data transmission by introducing variability in the transmitted data patterns. The computer program product includes logic configured to generate a first pseudo-random pattern, which serves as a base sequence for data transmission. To further enhance security and prevent predictable patterns, the logic repeats a subset of this pseudo-random pattern at a predetermined reload rate parameter. This means that instead of transmitting the entire pattern repeatedly, only a portion of it is reused at specified intervals, introducing controlled variability. The subset of the pseudo-random pattern is then transmitted over the communication interconnect, ensuring that the data stream remains unpredictable while maintaining a structured transmission schedule. The logic may also include additional features, such as adjusting the reload rate parameter dynamically based on system conditions or security requirements. This ensures that the transmission remains adaptable to different operational scenarios. The overall approach improves security by preventing attackers from exploiting predictable data patterns while maintaining efficient data transmission.

Claim 9

Original Legal Text

9. The computer program product of claim 7 , wherein the logic is further configured to execute at least one of: a predetermined number of testing loops; or a predetermined wait period.

Plain English Translation

The invention relates to a computer program product for managing testing processes in software or system validation. The technology addresses the challenge of efficiently controlling test execution, particularly in automated testing environments where repetitive or time-sensitive testing is required. The program product includes logic that can execute a predetermined number of testing loops or enforce a predetermined wait period between test iterations. This ensures consistent and controlled testing cycles, preventing resource overuse or premature termination. The logic may also handle test initialization, execution, and result collection, ensuring structured and repeatable test procedures. By allowing configurable testing loops or wait periods, the system adapts to different testing scenarios, such as stress testing, performance validation, or compliance checks. The invention improves test reliability and resource management by standardizing test execution parameters, reducing manual intervention, and ensuring consistent test conditions. This approach is particularly useful in automated testing frameworks where precise control over test cycles is necessary for accurate validation and debugging.

Patent Metadata

Filing Date

Unknown

Publication Date

December 24, 2019

Inventors

Alexey Kostinsky
Tomer Levy
Paul S. Cheses
Danny Naiger
Theodore Z. Schoenborn
Christopher P. Mozak
Nagi Aboulenein
James M. Shehadi

Want to explore more patents?

Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.

Citation & reuse

Analysis on this page is generated by Patentable — an AI-powered patent intelligence platform. AI-generated summaries, explanations, FAQs, and analysis may be reused with attribution and a visible link back to the canonical URL below. Patent abstracts and claims are USPTO public domain.

Cite as: Patentable. “INTERFERENCE TESTING” (10516439). https://patentable.app/patents/10516439

© 2026 Nomic Interactive Technology LLC. Machine-readable context available at /api/llm-context/10516439. See llms.txt for full attribution policy.