Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method of data transformation of an input data word of 2 N sections, where N is an integer, comprising the steps of: supplying said input data word to a set of N sequential layers of 2 to 1 multiplexers disposed from an input layer to an output layer, wherein: each multiplexer has a first input receiving data of a first corresponding multiplexer of a prior layer, a second input receiving data of a second different corresponding multiplexer of the prior layer, a control input and an output, each multiplexer providing an output corresponding to a selected one of said first input or said second input dependent upon a signal at said control input, each of the N sequential layers including 2 N 2 to 1 multiplexers; supplying a same control signal to each control input of each multiplexer of a layer; and outputting transformed data from said outputs of said multiplexers of said output layer.
This invention relates to a method for transforming input data using a layered multiplexer architecture. The problem addressed is efficient data transformation, particularly for operations requiring bit-level manipulation or reordering. The method processes an input data word divided into 2^N sections, where N is an integer, through N sequential layers of 2-to-1 multiplexers. Each layer contains 2^(N-1) multiplexers, with each multiplexer receiving inputs from two corresponding multiplexers in the prior layer. The first input of each multiplexer comes from a first corresponding multiplexer in the prior layer, while the second input comes from a second, different corresponding multiplexer in the prior layer. A control signal determines whether the multiplexer selects the first or second input. The same control signal is applied to all multiplexers within a given layer, ensuring uniform selection across the layer. The transformed data is output from the multiplexers in the final output layer. This architecture enables efficient bit-level transformations, such as bit reversal or permutation, by systematically routing data through the multiplexer layers based on the control signals. The method is particularly useful in applications requiring fast, parallel data manipulation, such as digital signal processing or cryptographic operations.
2. The method of claim 1 wherein: said step of supplying a same control signal to each control input of each multiplexer of a layer comprises the steps of: precalculating an N bit shuffle pattern, precalculating an N bit replicate pattern, precalculating an N bit rotate pattern, and supplying to said control input of each multiplexer of a layer a selected one of 1) a corresponding bit of said precalculated shuffle pattern, 2) a corresponding bit of said precalculated replicate pattern, 3) a corresponding bit of said rotate pattern, 4) an exclusive OR of said corresponding bit of said precalculated shuffle pattern and said corresponding bit of precalculated replicate pattern, 5) an exclusive OR of said corresponding bit of said precalculated shuffle pattern and said corresponding bit of precalculated rotate pattern, and 6) an exclusive OR of said corresponding bit of said precalculated replicate pattern and said corresponding bit of precalculated rotate pattern.
This invention relates to digital signal processing, specifically to methods for controlling multiplexers in a layered architecture to perform data manipulation operations. The problem addressed is the efficient implementation of complex data transformations, such as shuffling, replication, and rotation, using a configurable multiplexer network. The method involves precalculating three N-bit patterns: a shuffle pattern, a replicate pattern, and a rotate pattern. These patterns define how data is rearranged, duplicated, or shifted within the system. Each multiplexer in a layer receives a control signal derived from one of these patterns or a combination thereof. The control signal can be a direct bit from any of the precalculated patterns or an exclusive OR (XOR) of two patterns. This allows for flexible and programmable data manipulation by selecting different combinations of the patterns. The approach enables dynamic reconfiguration of the multiplexer network to perform various operations without requiring hardware changes, improving efficiency and adaptability in digital signal processing applications.
3. The method of claim 1 , wherein: said input data word consists of 64 sections; and said N sequential layers consists of 6 layers.
A method for processing input data involves dividing the input data into 64 sections and applying a neural network with 6 sequential layers to transform the data. The neural network processes the input data through each layer, where each layer applies a set of operations to extract features or perform computations. The 64-section division allows for parallel processing or structured data handling, while the 6-layer architecture enables hierarchical feature extraction or multi-stage computation. This approach is useful in applications requiring high-dimensional data transformation, such as deep learning, signal processing, or data compression, where structured input and layered processing improve efficiency and accuracy. The method ensures that the input data is systematically broken down and processed through multiple stages, enhancing the network's ability to capture complex patterns or relationships within the data.
4. The method of claim 1 , wherein: said input data word consists of 64 sections of 8 bits each section; and said first input, said second input and said output of each of said 2 to 1 multiplixers consists of 8 bits.
This invention relates to a digital data processing system designed to handle high-speed data operations, specifically focusing on efficient data routing and multiplexing. The system addresses the challenge of managing large data words in a structured and scalable manner, ensuring optimal performance in applications requiring rapid data manipulation. The method involves processing an input data word divided into 64 sections, each consisting of 8 bits. This structured division allows for parallel processing, enhancing throughput and efficiency. The system employs 2-to-1 multiplexers to route data between inputs and outputs, where each multiplexer input and output also consists of 8 bits. This ensures compatibility with standard data bus architectures and simplifies integration into existing digital systems. The multiplexers are configured to selectively route data from one of two 8-bit inputs to an 8-bit output based on a control signal, enabling dynamic data routing. The 64-section structure of the input data word allows for granular control over data flow, making the system adaptable to various processing tasks. The use of 8-bit sections aligns with common digital signal processing standards, ensuring broad applicability. This approach improves data handling efficiency by leveraging parallel processing and modular design, making it suitable for applications in telecommunications, signal processing, and high-performance computing. The system's scalability and compatibility with standard data formats enhance its versatility in diverse digital processing environments.
5. The method of claim 1 , wherein: said set of N sequential layers of 2 to 1 multiplexers form a butterfly network.
A butterfly network is a parallel computing architecture used for efficient data processing, particularly in applications requiring high-speed sorting, searching, or parallel computation. The problem addressed by this invention is the need for scalable and efficient data routing in parallel processing systems, where traditional networks may suffer from bottlenecks or inefficiencies in data distribution. The invention describes a method for constructing a butterfly network using a set of N sequential layers of 2-to-1 multiplexers. Each layer consists of multiplexers that route data between processing elements, allowing for parallel data transfer and efficient communication. The multiplexers in each layer are interconnected in a specific pattern to form a complete butterfly network, enabling high-speed data routing with minimal latency. This structure allows for efficient sorting, searching, and parallel computation tasks by enabling simultaneous data paths and reducing communication overhead. The butterfly network is particularly useful in parallel computing systems, such as those used in high-performance computing, data centers, or specialized hardware accelerators. By using 2-to-1 multiplexers in a layered configuration, the network ensures that data can be routed efficiently between multiple processing elements, improving overall system performance and scalability. The invention provides a method for constructing such a network, ensuring optimal data flow and minimizing bottlenecks in parallel processing applications.
6. The method of claim 1 , wherein: said set of N sequential layers of 2 to 1 multiplexers form an inverse butterfly network.
A method for signal processing involves using a set of N sequential layers of 2-to-1 multiplexers arranged to form an inverse butterfly network. The inverse butterfly network is a structured arrangement of multiplexers that processes input signals in a manner that reverses the operations of a forward butterfly network, commonly used in digital signal processing and fast Fourier transform (FFT) algorithms. Each layer of multiplexers selectively routes or combines signals based on control inputs, enabling efficient signal decomposition or reconstruction. The inverse butterfly network is particularly useful in applications requiring inverse operations, such as inverse FFT, signal reconstruction, or data demultiplexing. The method leverages the hierarchical structure of the network to achieve high-speed signal processing with reduced hardware complexity compared to traditional approaches. The multiplexers in each layer are interconnected in a way that ensures proper signal routing and combination, maintaining signal integrity throughout the processing pipeline. This configuration allows for scalable and efficient implementation in digital circuits, making it suitable for real-time signal processing applications.
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January 7, 2020
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