Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A processor comprising: a processor core circuitry; and a micro-op cache communicably coupled to the processor core circuitry, the micro-op cache comprising: a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache; and a micro-op data array to store multiple micro-ops, wherein data array entries in the micro-op data array are indexed according to bank number of a plurality of physical cache banks and to a set within one physical cache bank of the plurality of physical cache banks, and wherein allocation to the micro-op data array is according to sequential bank numbers of the plurality of physical cache banks.
This invention relates to processor architecture, specifically improving micro-op cache efficiency in modern processors. The problem addressed is the latency and complexity in accessing micro-operations (micro-ops) stored in a micro-op cache, which can bottleneck processor performance. Traditional micro-op caches use a set-associative structure, where entries are indexed by set and way, but this can lead to inefficient data access patterns and bank conflicts when multiple physical cache banks are involved. The invention describes a processor with a micro-op cache that optimizes data access by decoupling the tag and data arrays. The micro-op tag array uses a conventional set-associative indexing scheme, where entries are indexed by set and way. However, the micro-op data array is indexed differently—by bank number and set within a physical cache bank. This allows for more efficient allocation and retrieval of micro-ops. The data array is organized into multiple physical cache banks, and micro-ops are allocated sequentially across these banks. This sequential allocation reduces bank conflicts and improves access latency by ensuring that consecutive micro-ops are stored in adjacent banks, minimizing access delays. The design also allows for parallel access to multiple banks, further enhancing performance. The overall result is a more efficient micro-op cache that reduces latency and improves processor throughput.
2. The processor of claim 1 , wherein a next sequential bank number after a last cache bank of the plurality of physical cache banks comprises a first bank number associated with a first cache bank of the plurality of physical cache banks.
This invention relates to cache memory systems in computing architectures, specifically addressing the challenge of efficiently managing cache bank addressing to improve performance and reduce conflicts. The system includes a plurality of physical cache banks, each assigned a unique bank number for addressing. The key innovation involves configuring the addressing scheme such that the next sequential bank number after the last cache bank in the sequence wraps around to the first bank number of the first cache bank. This circular addressing approach ensures that bank selection remains balanced and avoids concentration of accesses in specific banks, which can lead to contention and performance degradation. The system may also include mechanisms to dynamically adjust bank assignments or handle bank conflicts, further optimizing cache utilization. By implementing this circular addressing method, the system reduces bank conflicts, improves cache hit rates, and enhances overall processing efficiency. The invention is particularly useful in high-performance computing environments where cache memory access patterns are critical to system performance.
3. The processor of claim 2 , further comprising a cache controller coupled to the micro-op cache, the cache controller to: store, in a register of the processor, identification of a final cache bank of the plurality of physical cache banks to which a final micro-op of a first entry was allocated in the micro-op data array; and allocate, to a next cache bank that sequentially follows the final cache bank of the plurality of physical cache banks, a first micro-op of a second entry to the micro-op data array, wherein allocation of the second entry sequentially follows allocation of the first entry.
This invention relates to processor architectures, specifically improving micro-op cache management in out-of-order execution processors. The problem addressed is inefficient micro-op cache allocation, which can lead to performance bottlenecks due to suboptimal bank utilization and increased latency when fetching micro-operations (micro-ops) from the cache. The invention describes a processor with a micro-op cache divided into multiple physical cache banks. A cache controller manages micro-op allocation across these banks. When storing a sequence of micro-op entries, the controller tracks the final cache bank used for the last micro-op of a first entry. For the next entry in the sequence, the controller allocates its first micro-op to the next sequential cache bank following the previously used final bank. This ensures a predictable, ordered allocation pattern, reducing bank conflicts and improving cache efficiency. The cache controller also maintains a register to store the identification of the final cache bank used for each entry. This allows the processor to maintain allocation order across multiple entries, ensuring that micro-ops are distributed evenly across the cache banks. The sequential allocation strategy minimizes bank contention and optimizes cache access patterns, particularly in high-performance processors where micro-op fetch latency is critical. The invention enhances cache performance by leveraging spatial locality and reducing bank collisions.
4. The processor of claim 2 , wherein allocation to the micro-op data array is to begin allocation to a physical cache bank of the plurality of physical cache banks other than a first physical cache bank of the plurality of physical cache banks in at least some cache entry allocations.
This invention relates to a processor with a micro-op cache system designed to improve performance by optimizing cache bank allocation. The problem addressed is inefficient cache utilization, where certain physical cache banks may become overloaded while others remain underutilized, leading to performance bottlenecks. The solution involves dynamically allocating micro-operations (micro-ops) to multiple physical cache banks within a micro-op data array, ensuring that allocations are distributed across different banks rather than concentrating solely on a single bank. Specifically, the processor begins allocation to a physical cache bank other than the first bank in at least some cache entry allocations, promoting load balancing and reducing contention. This approach helps mitigate hotspots, improves cache efficiency, and enhances overall processor performance by ensuring more uniform distribution of micro-op storage across available cache banks. The system may include mechanisms to track bank usage and dynamically adjust allocation strategies based on real-time demand, further optimizing cache performance. The invention is particularly useful in high-performance computing environments where efficient cache management is critical.
5. The processor of claim 1 , wherein the micro-op tag array comprises a plurality of index pointers, each index pointer of the plurality of index pointers to point to a bank number and set within a physical cache bank of the plurality of physical cache banks of the micro-op data array.
This invention relates to a processor architecture with an improved micro-op cache system. The problem addressed is the inefficiency in accessing micro-operations (micro-ops) stored in a micro-op cache, particularly in systems where micro-ops are distributed across multiple physical cache banks. Traditional approaches may suffer from latency or complexity when retrieving micro-ops due to the need to track their locations across different banks. The invention describes a processor with a micro-op tag array that includes a plurality of index pointers. Each index pointer in the tag array is configured to point to a specific bank number and set within a physical cache bank of the micro-op data array. The micro-op data array is divided into multiple physical cache banks, and the tag array's index pointers enable efficient lookup of micro-op locations. This allows the processor to quickly determine which physical bank and set contains a particular micro-op, reducing access latency and improving overall performance. The system ensures that micro-ops can be retrieved with minimal delay, even when distributed across multiple banks, by maintaining precise location information in the tag array. This approach optimizes cache access and enhances the efficiency of micro-op retrieval in modern processor architectures.
6. The processor of claim 5 , wherein each physical cache bank of the plurality of physical cache banks of the micro-op data array is partitioned into a plurality of regions, each region spanning multiple consecutively-numbered sets, and wherein each index pointer of the plurality of index pointers is to point to a set within an identified region of the plurality of regions.
This invention relates to a processor architecture with an optimized micro-op data array cache. The problem addressed is improving cache efficiency and reducing access latency in processors that handle micro-operations (micro-ops), which are low-level instructions processed by the CPU. The solution involves partitioning each physical cache bank of the micro-op data array into multiple regions, where each region spans multiple consecutively-numbered sets. Additionally, index pointers are used to point to specific sets within these regions, allowing for more flexible and efficient data access. This partitioning and indexing scheme helps manage micro-op data more effectively, reducing conflicts and improving cache hit rates. The design is particularly useful in high-performance processors where micro-op handling is a critical bottleneck. By organizing the cache into regions and using index pointers, the system can better distribute micro-op data, minimizing access delays and enhancing overall processor performance. The invention focuses on optimizing the micro-op data array's structure to handle workloads more efficiently, ensuring faster execution and better resource utilization.
7. The processor of claim 1 , wherein the micro-op data array is sized to be at least thirty percent smaller than the micro-op tag array.
This invention relates to processor architecture, specifically optimizing memory usage in micro-op (micro-operation) storage systems. The problem addressed is the inefficient allocation of memory resources in processors, particularly when storing micro-ops, which are low-level instructions derived from higher-level machine code. Traditional designs often use similarly sized arrays for micro-op data and tags, leading to wasted space and higher power consumption. The invention improves this by implementing a micro-op data array that is at least thirty percent smaller than the micro-op tag array. The micro-op tag array stores identifiers or metadata for the micro-ops, while the micro-op data array holds the actual instruction data. By reducing the size of the data array relative to the tag array, the design minimizes memory overhead without compromising functionality. This reduction in size lowers power consumption and improves overall processor efficiency. The processor includes a micro-op cache that stores micro-ops in the data array and their corresponding tags in the tag array. The data array is optimized to store only the essential instruction data, while the tag array retains the necessary metadata for quick access and management. The size difference ensures that the data array does not consume excessive memory, balancing performance and resource usage. This approach is particularly beneficial in high-performance processors where memory efficiency is critical.
8. An integrated circuit comprising: a micro-op cache comprising a micro-op tag array and a micro-op data array; and a cache controller coupled to the micro-op cache, wherein to allocate a first entry to the micro-op cache, the cache controller is to: allocate indexing metadata of the first entry to the micro-op tag array according to a plurality of sets of ways of set-associative cache; and allocate a plurality of micro-ops to the micro-op data array according to an index within the micro-op data array, the index comprising bank number of a plurality of physical cache banks and a set within one physical cache bank of the plurality of physical cache banks of the micro-op data array, wherein allocation to the micro-op data array is according to sequential bank numbers of the plurality of physical cache banks.
The invention relates to an integrated circuit with an improved micro-op cache design for efficient instruction processing. The micro-op cache includes a micro-op tag array and a micro-op data array, managed by a cache controller. The cache controller allocates entries to the micro-op cache using a set-associative scheme for the tag array, while the data array is organized into multiple physical cache banks. When allocating a new entry, the controller assigns indexing metadata to the tag array based on the set-associative structure. Simultaneously, the controller distributes the micro-operations (micro-ops) across the data array using an index that includes both a bank number and a set within a specific bank. The allocation follows a sequential bank numbering scheme to optimize access patterns. This design enhances cache efficiency by leveraging set-associative tag management while ensuring micro-ops are stored in a structured, banked data array, reducing access latency and improving throughput in instruction processing pipelines. The invention addresses the challenge of balancing cache complexity and performance in modern processors by decoupling tag and data array management while maintaining coherent indexing.
9. The integrated circuit of claim 8 , wherein a sequential bank number after a last cache bank of the plurality of physical cache banks comprises a first bank number of a first cache bank of the plurality of physical cache banks.
This invention relates to integrated circuits with cache memory systems, specifically addressing the challenge of efficiently managing cache bank addressing in multi-bank cache architectures. The system includes a plurality of physical cache banks, each assigned a unique bank number for addressing. A key feature is the handling of bank numbers after the last physical cache bank, where the next sequential bank number wraps around to the first bank number of the first physical cache bank. This circular addressing scheme ensures continuous and predictable bank numbering, simplifying memory access and reducing complexity in cache management. The system may also include mechanisms to determine the number of physical cache banks and dynamically adjust addressing based on available resources. This approach improves cache performance by maintaining a consistent addressing structure, preventing address conflicts, and optimizing memory access patterns. The invention is particularly useful in high-performance computing environments where efficient cache utilization is critical.
10. The integrated circuit of claim 9 , wherein, upon further allocation to the micro-op cache after a period of micro-op cache hits, the cache controller is further to: store, in a register, identification of a final cache bank of the plurality of physical cache banks associated with a final micro-op of a most-recent-hit entry in the micro-op data array; and allocate, to a next cache bank that sequentially follows the final cache bank of the plurality of physical cache banks, a first micro-op of a second entry to the micro-op data array, wherein allocation of the second entry sequentially follows the final cache bank identified in the register.
This invention relates to integrated circuits with micro-op caches, addressing the problem of efficient micro-operation (micro-op) allocation to optimize cache performance. The system includes a micro-op cache with multiple physical cache banks and a cache controller that manages micro-op storage and retrieval. The controller monitors cache hits and, after a period of successful hits, identifies the final cache bank associated with the last micro-op of the most recently accessed entry. This bank is stored in a register. When allocating a new entry to the cache, the controller places the first micro-op of the new entry into the next sequential cache bank following the stored final bank. This sequential allocation strategy improves cache efficiency by reducing access latency and conflicts, ensuring smoother micro-op retrieval. The system dynamically adapts to usage patterns, enhancing performance in integrated circuits where micro-op caching is critical, such as in processors handling complex instruction sets. The invention optimizes cache bank utilization by leveraging hit history to guide future allocations, minimizing redundant accesses and improving overall throughput.
11. The integrated circuit of claim 8 , wherein, to allocate the plurality of micro-ops to the micro-op data array, the cache controller is to begin allocation to a physical cache bank of the plurality of physical cache banks other than a first physical cache bank of the plurality of physical cache banks.
This invention relates to integrated circuits with micro-op caching systems, specifically addressing the challenge of efficiently allocating micro-operations (micro-ops) to a micro-op data array in a multi-banked cache structure. The system includes a cache controller and a micro-op data array divided into multiple physical cache banks. The controller allocates micro-ops to the array by initially bypassing the first physical cache bank, instead beginning allocation in a different bank. This approach helps balance cache usage, reduce contention, and improve performance by distributing micro-ops more evenly across the available banks. The controller may also manage allocation based on bank availability, ensuring that micro-ops are directed to the most suitable bank at any given time. The system may further include mechanisms to track micro-op dependencies and prioritize allocation to minimize stalls. The invention is particularly useful in high-performance processors where efficient micro-op caching is critical for maintaining throughput and reducing latency.
12. The integrated circuit of claim 8 , wherein the micro-op tag array comprises a plurality of index pointers, each index pointer of the plurality of index pointers to point to a bank number and set within a cache bank of the plurality of physical cache banks of the micro-op data array.
This invention relates to integrated circuits, specifically to a micro-op tag array within a micro-op cache system. The problem addressed is efficient management of micro-operations (micro-ops) in a processor pipeline, particularly in accessing and retrieving micro-ops from a micro-op data array stored across multiple physical cache banks. The micro-op tag array includes a plurality of index pointers, each pointing to a specific bank number and set within a cache bank of the micro-op data array. This allows the system to quickly locate and retrieve micro-ops by using the index pointers to navigate the distributed cache banks, improving access speed and reducing latency. The micro-op data array is divided into multiple physical cache banks, and the tag array's index pointers ensure that micro-ops are correctly mapped to their respective storage locations. This design enhances the efficiency of micro-op retrieval in high-performance processors by optimizing the addressing mechanism within the cache hierarchy. The system ensures that micro-ops are stored and accessed in a structured manner, reducing the overhead associated with searching across multiple cache banks. The invention is particularly useful in out-of-order execution processors where rapid access to micro-ops is critical for maintaining pipeline efficiency.
13. The integrated circuit of claim 12 , wherein each physical cache bank of the plurality of physical cache banks of the micro-op data array is partitioned into a plurality of regions, each region spanning multiple consecutively-numbered sets, and wherein each index pointer of the plurality of index pointers is to point to a set within an identified region of the plurality of regions.
This invention relates to an integrated circuit with an improved micro-op (micro-operation) data array cache structure. The problem addressed is optimizing cache access efficiency in processors by reducing latency and improving hit rates in micro-op caches, which are critical for performance in modern pipelined architectures. The integrated circuit includes a micro-op data array with multiple physical cache banks, each partitioned into multiple regions. Each region spans multiple consecutively-numbered sets, allowing for more flexible and efficient data placement. The cache uses a plurality of index pointers, each pointing to a specific set within an identified region. This partitioning and indexing scheme enables faster access to micro-operations by reducing the search space and improving locality of reference. The regions and index pointers work together to enhance cache performance. By organizing the cache banks into regions, the system can more effectively manage data distribution, reducing conflicts and improving hit rates. The index pointers allow direct access to specific sets within regions, minimizing the time required to locate micro-operations. This design is particularly useful in high-performance processors where micro-op cache efficiency directly impacts instruction execution speed. The invention builds on prior techniques by introducing a hierarchical structure within the cache banks, combining region-based partitioning with precise indexing to optimize access patterns. This approach addresses the challenge of maintaining low-latency access in large micro-op caches while improving overall system throughput.
14. The integrated circuit of claim 8 , wherein the micro-op data array is sized to be at least thirty percent smaller than the micro-op tag array.
This invention relates to integrated circuits, specifically to the design of micro-op (micro-operation) storage arrays in processors. The problem addressed is the inefficiency in memory usage for storing micro-ops, which are low-level instructions executed by the processor. Traditional designs often allocate equal or similar storage sizes for micro-op data and tag arrays, leading to unnecessary memory consumption and higher power requirements. The invention improves upon this by implementing an integrated circuit with a micro-op data array that is at least thirty percent smaller in size than the micro-op tag array. The micro-op data array stores the actual micro-op instructions, while the micro-op tag array stores metadata or identifiers associated with those instructions. By reducing the size of the data array relative to the tag array, the design optimizes memory usage, reducing both the physical footprint and power consumption of the integrated circuit. This size reduction is achieved without compromising performance, as the tag array remains sufficiently large to handle the necessary metadata operations. The invention may also include additional features such as a micro-op cache and a micro-op queue to further enhance efficiency in instruction processing. The overall result is a more compact and energy-efficient processor design.
15. A method comprising: allocating, by a cache controller of a processor, indexing metadata of a first entry to a micro-op tag array of a micro-op cache according to a plurality of sets of ways of set-associative cache; and allocating, by the cache controller, a plurality of micro-ops of the first entry to a micro-op data array of the micro-op cache, wherein allocating the plurality of micro-ops is according to an index comprising bank number of a plurality of physical cache banks and a set within one physical cache bank of the plurality of physical cache banks of the micro-op data array, and wherein allocating the plurality of micro-ops to the micro-op data array comprises sequentially allocating each micro-op of the plurality of micro-ops across the plurality of physical cache banks according to a sequential bank number.
This invention relates to optimizing micro-operation (micro-op) caching in a processor by efficiently allocating micro-ops and their metadata in a set-associative micro-op cache. The problem addressed is improving cache performance by reducing access latency and conflicts in a multi-banked cache structure. The method involves a cache controller managing a micro-op cache with separate metadata and data arrays. The metadata of a micro-op entry is allocated to a micro-op tag array using a set-associative indexing scheme, which organizes entries into multiple sets and ways to minimize conflicts. The micro-ops themselves are allocated to a micro-op data array, which is physically divided into multiple banks. The allocation uses an index combining a bank number and a set within a bank, ensuring micro-ops are distributed across banks sequentially by bank number. This sequential distribution balances the load across banks, reducing contention and improving access efficiency. The method ensures that metadata and micro-op data are coherently mapped, optimizing cache access and reducing latency in instruction execution.
16. The method of claim 15 , wherein the sequential bank number after a last cache bank of the plurality of physical cache banks comprises a first bank number of a first physical cache bank of the plurality of physical cache banks.
This invention relates to cache memory systems, specifically addressing the challenge of efficiently managing cache bank access to reduce conflicts and improve performance. The method involves organizing a plurality of physical cache banks in a circular manner, where each bank is assigned a sequential bank number. When accessing a cache line, the system determines a target bank number based on an address and a hash function. If the target bank number exceeds the last bank number in the sequence, it wraps around to the first bank number, ensuring continuous and predictable access patterns. This circular addressing scheme helps distribute access requests evenly across the cache banks, minimizing contention and improving memory access efficiency. The method is particularly useful in multi-core or high-performance computing environments where cache conflicts can significantly impact system performance. By dynamically adjusting the bank selection process, the system avoids bottlenecks and maintains high throughput. The technique can be applied to various cache architectures, including direct-mapped, set-associative, or fully associative caches, to enhance their overall efficiency.
17. The method of claim 16 , further comprising: storing, in a register, identification of a final cache bank of the plurality of physical cache banks of the micro-op data array to which a final micro-op of the first entry was allocated; and allocating, to a next cache bank that sequentially follows the final cache bank of the plurality of physical cache banks, a first micro-op of a second entry to the micro-op data array, wherein allocating the second entry sequentially follows allocating the first entry.
This invention relates to cache memory management in micro-op data arrays, specifically addressing the challenge of efficiently allocating micro-operations (micro-ops) across multiple physical cache banks to optimize performance and reduce latency. The method involves tracking the allocation of micro-ops within a micro-op data array that consists of multiple physical cache banks. When a first entry of micro-ops is allocated to the array, the final cache bank used for that entry is identified and stored in a register. For the subsequent entry, the first micro-op is allocated to the next sequential cache bank following the final bank of the previous entry. This sequential allocation ensures a predictable and organized distribution of micro-ops across the cache banks, improving cache utilization and reducing conflicts. The method enhances performance by maintaining a structured allocation pattern, which helps in minimizing access delays and improving overall system efficiency. The approach is particularly useful in high-performance computing environments where efficient cache management is critical for maintaining low-latency operation.
18. The method of claim 15 , wherein allocating the plurality of micro-ops to the micro-op data array comprises beginning allocation to a physical cache bank of the plurality of physical cache banks other than a first physical cache bank of the plurality of physical cache banks.
This invention relates to optimizing micro-operation (micro-op) allocation in a processor cache system to improve performance and reduce conflicts. The problem addressed is inefficient micro-op distribution in multi-banked cache architectures, leading to bottlenecks and contention when multiple micro-ops target the same cache bank. The solution involves a method for dynamically allocating micro-ops to a plurality of physical cache banks, where the allocation process begins with a cache bank other than the first bank in the sequence. This approach distributes micro-op requests more evenly across the cache banks, reducing contention and improving throughput. The method may also include tracking micro-op dependencies and prioritizing allocation based on execution readiness, ensuring that dependent micro-ops are scheduled in an order that minimizes stalls. Additionally, the system may monitor cache bank utilization and dynamically adjust allocation strategies to avoid hotspots. The technique is particularly useful in out-of-order execution processors where micro-op scheduling efficiency directly impacts performance. By starting allocation from a non-first bank, the method helps balance the load across all cache banks, leading to more efficient resource utilization and faster instruction completion.
19. The method of claim 15 , wherein allocating the indexing metadata to the micro-op tag array comprises storing an index pointer for each of a plurality of micro-ops, the index pointer to point to a bank number and set within a physical cache bank of the plurality of physical cache banks of the micro-op data array.
This invention relates to a method for managing micro-operations (micro-ops) in a processor cache system, specifically addressing the challenge of efficiently allocating and retrieving indexing metadata for micro-ops to optimize cache access and performance. The method involves storing an index pointer for each micro-op in a micro-op tag array, where the index pointer directs to a specific bank number and set within a physical cache bank of a micro-op data array. The micro-op data array is divided into multiple physical cache banks, each containing multiple sets, and the index pointer ensures that the micro-op can be quickly located within the correct bank and set. This approach improves cache efficiency by reducing search time and enhancing parallel access to micro-op data. The method is part of a broader system for managing micro-ops, which includes generating micro-ops from instructions, storing them in the micro-op data array, and retrieving them for execution. The indexing metadata allocation ensures that micro-ops are stored and accessed in an organized manner, minimizing latency and improving overall processor performance. The system may also include mechanisms for handling cache conflicts and maintaining coherence between different cache levels.
20. The method of claim 19 , further comprising: partitioning each physical cache bank of the plurality of physical cache banks into a plurality of regions, each region spanning multiple consecutively-numbered sets; and configuring each index pointer to point to a set within an identified region of the plurality of regions.
A method for managing cache memory in a computing system involves partitioning each physical cache bank into multiple regions, where each region spans multiple consecutively-numbered sets. The method also includes configuring index pointers to point to specific sets within these identified regions. This approach improves cache efficiency by organizing data access patterns into distinct regions, reducing conflicts and enhancing performance. The partitioning allows for better utilization of cache resources by grouping related data sets, while the configurable index pointers enable dynamic allocation and management of cache memory. This technique is particularly useful in systems where cache performance is critical, such as high-performance computing or real-time processing applications. By structuring the cache into regions and directing index pointers to specific sets within those regions, the method optimizes data retrieval and storage operations, leading to improved overall system performance. The method can be applied in various computing environments, including multi-core processors, embedded systems, and specialized hardware accelerators, to enhance cache efficiency and reduce latency.
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March 3, 2020
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