Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An integrated circuit, comprising: a clock generator providing a clock signal; a block having a block boundary, wherein the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree; and a plurality of sub-blocks disposed within the block boundary of the block, wherein each sub-block of the plurality of sub-blocks comprises: first block circuitry and second block circuitry, wherein the first block circuitry is configured to receive a first clock signal and provide one or more first output signals based on the first clock signal, and wherein the second block circuitry is configured to receive a second clock signal and provide one or more first and second output signals based on the second clock signal; and lock-step checker circuitry configured to provide a lock-step error signal based on the first and second clock signals and the one or more first and second output signals.
This invention relates to integrated circuits with clock distribution and error detection mechanisms. The system addresses the challenge of ensuring synchronization and error detection in digital circuits where multiple sub-blocks operate on different clock signals. The integrated circuit includes a clock generator that produces a clock signal, which is distributed to a block via a clock-tree network. Within the block, multiple sub-blocks are arranged, each containing two distinct circuit sections: first block circuitry and second block circuitry. The first block circuitry processes a first clock signal to generate output signals, while the second block circuitry processes a second clock signal to produce its own output signals. Each sub-block also includes lock-step checker circuitry that monitors both clock signals and their corresponding output signals. The checker circuitry detects discrepancies between the outputs of the two circuit sections, generating a lock-step error signal if a mismatch is found. This design ensures that the sub-blocks operate correctly and synchronously, even when different clock signals are used, by continuously verifying consistency between the outputs of the two circuit sections. The system is particularly useful in applications requiring high reliability, such as safety-critical systems or fault-tolerant computing.
2. The integrated circuit of claim 1 , wherein the block comprises functional safety (FuSa) block circuitry that provides the clock signal along the clock-tree to each sub-block of the plurality of sub-blocks.
This invention relates to integrated circuits with enhanced functional safety (FuSa) features, specifically addressing the need for reliable clock signal distribution in safety-critical systems. The integrated circuit includes a block containing functional safety circuitry that distributes a clock signal through a clock-tree network to multiple sub-blocks within the circuit. The FuSa block circuitry ensures that the clock signal is delivered consistently and safely to each sub-block, mitigating risks of clock failures that could compromise system integrity. This design is particularly important in applications where clock signal integrity is critical, such as automotive, aerospace, or industrial control systems, where failures could lead to catastrophic consequences. The FuSa block circuitry may include redundancy, error detection, or other safety mechanisms to maintain clock signal reliability. By integrating these safety features directly into the clock distribution network, the invention enhances overall system robustness and compliance with functional safety standards. The solution ensures that all sub-blocks receive a fault-tolerant clock signal, reducing the likelihood of timing-related errors and improving system dependability.
3. The integrated circuit of claim 1 , wherein the clock-tree comprises a main clock-tree that is disposed within the block boundary of the block, and wherein the main clock-tree feeds the clock signal to each sub-block of the plurality of sub-blocks.
This invention relates to integrated circuit (IC) design, specifically addressing clock distribution challenges in large-scale ICs with multiple sub-blocks. The problem solved is inefficient clock signal distribution, which can lead to timing errors, power inefficiency, and increased latency in complex IC architectures. The invention describes an integrated circuit with a hierarchical clock-tree structure. The clock-tree includes a main clock-tree disposed within the boundary of a primary block, which distributes a clock signal to multiple sub-blocks. Each sub-block receives the clock signal directly from the main clock-tree, ensuring synchronized timing across the IC. The main clock-tree is designed to minimize skew and jitter, improving overall system performance. The hierarchical structure allows for scalable clock distribution, reducing power consumption and simplifying design complexity. The invention also ensures that the clock signal remains stable and consistent across all sub-blocks, enhancing reliability in high-performance applications. This approach optimizes clock distribution in large ICs, particularly those with multiple interconnected sub-blocks, improving efficiency and reducing design constraints.
4. The integrated circuit of claim 1 , wherein each sub-block of the plurality of sub-blocks has a divergent node that receives the clock signal from within the block boundary of the block via the clock-tree and diverges the clock signal into the first clock signal and the second clock signal.
The invention relates to integrated circuit design, specifically addressing clock distribution challenges in large-scale circuits. Traditional clock trees often suffer from signal integrity issues, such as skew and jitter, due to long signal paths and high fan-out requirements. This invention improves clock distribution by structuring the circuit into multiple sub-blocks, each with a dedicated clock distribution mechanism. The integrated circuit includes a block with a clock-tree that distributes a clock signal within its boundary. Each sub-block within the block has a divergent node that receives the clock signal from the block's clock-tree. The divergent node splits the clock signal into two distinct clock signals: a first clock signal and a second clock signal. This division allows for more precise control over clock distribution within each sub-block, reducing skew and improving synchronization across the circuit. The sub-blocks may operate independently or in coordination, depending on the design requirements. This approach enhances timing performance and power efficiency by optimizing clock delivery paths and minimizing unnecessary signal propagation delays. The invention is particularly useful in high-performance computing, digital signal processing, and other applications requiring low-latency, high-reliability clock distribution.
5. The integrated circuit of claim 1 , wherein each sub-block of the plurality of sub-blocks provides the first clock signal along a first clock-tree disposed within a sub-block boundary of each sub-block, and wherein each sub-block of the plurality of sub-blocks provides the second clock signal along a second clock-tree disposed within the sub-block boundary of each sub-block.
This invention relates to integrated circuits with improved clock distribution networks. The problem addressed is the inefficiency and complexity of traditional clock distribution systems, which often suffer from skew, power consumption, and routing congestion when distributing multiple clock signals across large integrated circuits. The invention describes an integrated circuit with a hierarchical clock distribution architecture. The circuit includes multiple sub-blocks, each containing its own clock generation or distribution circuitry. Within each sub-block, a first clock signal is distributed via a first clock-tree network, and a second clock signal is distributed via a second clock-tree network. Both clock-trees are confined within the boundaries of their respective sub-blocks, ensuring localized clock distribution. This modular approach reduces clock skew, minimizes power consumption, and simplifies routing by isolating clock distribution paths within each sub-block. The sub-blocks may be arranged in a grid or other configuration, with each sub-block independently managing its clock signals. This design allows for scalable and efficient clock distribution across large integrated circuits, particularly in systems requiring multiple clock domains or high-performance processing. The invention improves clock signal integrity and reduces design complexity compared to traditional global clock distribution networks.
6. The integrated circuit of claim 5 , wherein the first clock-tree and the second clock-tree are separate and isolated within each sub-block of the plurality of sub-blocks from the clock-tree of the block.
This invention relates to integrated circuit design, specifically addressing clock distribution challenges in large-scale integrated circuits. The problem solved is the need to isolate clock signals within sub-blocks of an integrated circuit to prevent interference and improve timing accuracy. In conventional designs, clock signals distributed across an entire block can introduce noise, skew, and synchronization issues, particularly in high-performance or mixed-signal circuits. The invention describes an integrated circuit with a hierarchical clock distribution structure. The circuit includes a main block divided into multiple sub-blocks, each containing its own isolated clock-tree. The first and second clock-trees within each sub-block are separate and isolated from the main clock-tree of the block. This isolation ensures that clock signals in one sub-block do not interfere with those in another, reducing noise and improving timing precision. The sub-blocks may contain functional units such as processors, memory controllers, or analog circuits, each requiring independent clock control. The isolated clock-trees allow for fine-grained clock management, enabling dynamic frequency scaling, power gating, or asynchronous operation between sub-blocks. This design is particularly useful in systems-on-chip (SoCs) or multi-core processors where clock synchronization and power efficiency are critical. The isolation also simplifies testing and debugging by localizing clock-related issues to specific sub-blocks.
7. The integrated circuit of claim 5 , wherein the first clock-tree distributes the first clock signal to the first block circuitry disposed within each sub-block of the plurality of sub-blocks, and wherein the second clock-tree distributes the second clock signal to second block circuitry disposed within each sub-block of the plurality of sub-blocks.
This invention relates to integrated circuits with multiple clock distribution networks. The problem addressed is the efficient distribution of multiple clock signals within an integrated circuit, particularly in designs with modular or sub-block architectures. Traditional clock distribution networks often struggle to provide independent clock signals to different functional blocks within sub-blocks without excessive power consumption or signal skew. The invention describes an integrated circuit containing a plurality of sub-blocks, each with first and second block circuitry. A first clock-tree network distributes a first clock signal specifically to the first block circuitry within each sub-block, while a second clock-tree network distributes a second clock signal to the second block circuitry within each sub-block. This allows independent clocking of different functional units within the same sub-block, enabling power optimization and reduced skew. The clock-trees are designed to minimize signal propagation delays and ensure synchronized operation across the sub-blocks. The invention may also include additional clock-trees for further clock domains, depending on the circuit's complexity. The modular design allows for scalable and efficient clock distribution in large-scale integrated circuits.
8. The integrated circuit of claim 7 , wherein the second block circuitry is a duplicate of the first block circuitry.
The invention relates to integrated circuits designed to enhance reliability and fault tolerance. The problem addressed is the susceptibility of integrated circuits to failures, which can disrupt operations in critical applications. The solution involves an integrated circuit with redundant block circuitry to improve fault tolerance. The integrated circuit includes at least two block circuitries, where the second block circuitry is a duplicate of the first. This redundancy ensures that if one block fails, the duplicate can continue functioning, maintaining system reliability. The first block circuitry performs a specific function, and the second block circuitry, being identical, can replicate that function. This duplication allows for error detection and correction, as the outputs of both blocks can be compared to identify discrepancies. If a mismatch is detected, the system can switch to the redundant block or trigger a recovery mechanism. The redundant design is particularly useful in applications where uninterrupted operation is essential, such as in aerospace, automotive, or medical devices. By duplicating critical circuitry, the integrated circuit minimizes the risk of failure and enhances overall system robustness. The redundancy can be implemented at various levels, from simple functional blocks to entire processing units, depending on the required reliability level. This approach ensures that the integrated circuit remains operational even in the presence of faults, improving safety and performance in demanding environments.
9. The integrated circuit of claim 5 , wherein the first block circuitry receives the first clock signal from the first clock-tree, and wherein the second block circuitry receives the second clock signal from the second clock-tree.
This invention relates to integrated circuits with multiple clock domains, addressing synchronization and power efficiency challenges in modern semiconductor designs. The integrated circuit includes at least two distinct block circuitries, each operating with its own dedicated clock signal. The first block circuitry receives a first clock signal from a first clock-tree network, while the second block circuitry receives a second clock signal from a second clock-tree network. These clock-trees are independently designed and distributed to ensure proper timing and synchronization for their respective circuit blocks. The separation of clock domains allows for optimized power management, reduced interference, and improved performance by isolating timing-critical operations. This configuration is particularly useful in systems requiring multiple clock frequencies or phases, such as processors, communication circuits, or mixed-signal designs. The independent clock distribution minimizes skew and jitter between domains, enhancing overall system reliability and efficiency. The invention may also include additional circuitry to manage clock synchronization or power gating, ensuring seamless operation across different clock domains.
10. The integrated circuit of claim 9 , wherein the lock-step checker circuitry receives the first clock signal from the first clock tree and receives the second clock signal from the second clock tree.
The integrated circuit includes a lock-step checker circuit designed to verify the synchronization and consistency of two clock signals in a dual-clock system. The circuit operates by comparing the timing and phase of a first clock signal from a first clock tree with a second clock signal from a second clock tree. This ensures that both clock domains remain aligned, preventing timing errors in critical operations. The lock-step checker circuit monitors for discrepancies between the two clock signals, such as phase shifts or frequency mismatches, and generates an error signal if a mismatch is detected. This is particularly useful in systems where multiple clock domains must operate in lock-step, such as in redundant processing units or fault-tolerant designs. The circuit helps maintain data integrity and system reliability by ensuring that operations in different clock domains remain synchronized. The design may include additional features, such as configurable thresholds for error detection or self-testing capabilities, to enhance robustness. The overall system may also include clock generation and distribution circuitry to provide the first and second clock signals to the lock-step checker. This approach is valuable in applications requiring high reliability, such as aerospace, automotive, or industrial control systems.
11. The integrated circuit of claim 10 , wherein the lock-step checker circuitry operates as a logical point of convergence, and wherein one or more faults occurring on the first clock-tree within each sub-block are detected by the lock-step checker circuitry.
This invention relates to integrated circuit (IC) design, specifically addressing fault detection in clock-tree networks. The problem being solved is the challenge of identifying faults in clock distribution networks, which are critical for synchronous circuit operation but difficult to monitor due to their distributed nature. The IC includes multiple sub-blocks, each with a first clock-tree for distributing clock signals. A lock-step checker circuit is integrated to serve as a logical point of convergence for fault detection. This circuit monitors the clock-trees within each sub-block, detecting faults such as timing errors or signal integrity issues. The lock-step checker ensures that the clock signals across sub-blocks remain synchronized and free of faults, improving reliability in synchronous digital circuits. The design allows for centralized fault detection while maintaining distributed clock distribution, reducing the complexity of fault isolation in large-scale ICs. The solution is particularly useful in high-performance or safety-critical applications where clock signal integrity is paramount.
12. The integrated circuit of claim 11 , wherein the one or more faults comprise a stuck-at fault that refers to a stuck-at clock error related to the clock signal not toggling and being stuck at a logic value of 1 or 0.
This invention relates to integrated circuits with fault detection capabilities, specifically addressing stuck-at clock faults where a clock signal fails to toggle and remains stuck at a logic high (1) or low (0) state. Such faults can disrupt circuit operation by preventing proper synchronization of digital signals. The integrated circuit includes a fault detection mechanism that identifies these stuck-at clock errors by monitoring the clock signal for expected toggling behavior. If the clock signal remains constant at either logic level, the system detects the fault and may trigger corrective actions or alerts. The circuit may also include additional fault detection features, such as identifying other types of faults like stuck-at faults in data or control signals, ensuring comprehensive error detection. The invention aims to improve reliability in digital systems by detecting and mitigating clock-related faults that could otherwise lead to system failures or incorrect operations. The fault detection mechanism operates autonomously, continuously monitoring the clock signal to ensure proper toggling and flagging deviations from expected behavior. This approach enhances system robustness, particularly in safety-critical applications where clock signal integrity is essential.
13. The integrated circuit of claim 12 , wherein the one or more faults comprises a transient fault that refers to a transient clock error related to an extra edge on the clock signal or a transient clock error related to a missed edge on the clock signal.
This invention relates to integrated circuits with fault detection and correction mechanisms, specifically addressing transient clock errors. The technology domain involves integrated circuits that rely on precise clock signals for synchronization, where errors such as extra or missed clock edges can disrupt operation. The problem solved is the detection and correction of transient faults in clock signals, which can lead to data corruption or system malfunctions. The integrated circuit includes a clock signal generator that produces a reference clock signal and a fault detection module that monitors the clock signal for anomalies. The fault detection module identifies transient faults, including extra clock edges (where an additional pulse occurs) or missed clock edges (where a pulse is absent). Upon detecting such faults, the circuit implements corrective measures, such as resynchronization or error recovery, to maintain system stability. The fault detection module may use comparison logic to verify clock signal integrity against expected timing patterns or employ redundancy checks to confirm signal accuracy. The system ensures reliable operation in environments where transient clock errors are likely, such as high-speed or noisy electronic systems. The invention improves fault tolerance and reduces the risk of data loss or system failures caused by clock signal irregularities.
14. The integrated circuit of claim 1 , wherein each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into the first clock signal and the second clock signal from within a sub-block boundary of each sub-block.
This invention relates to integrated circuit (IC) clock distribution networks, specifically addressing challenges in power efficiency and signal integrity in large-scale IC designs. The problem solved involves distributing clock signals across multiple sub-blocks within a block while minimizing power consumption and signal distortion. Traditional clock distribution networks often suffer from high power dissipation and timing inaccuracies due to long signal paths and impedance mismatches. The invention describes an IC with a hierarchical clock distribution system. A block within the IC contains multiple sub-blocks, each receiving a clock signal from within the block boundary via a clock-tree network. Within each sub-block, the clock signal is further divided into two distinct clock signals—referred to as the first and second clock signals—from within the sub-block boundary. This hierarchical approach ensures localized clock signal distribution, reducing power loss and improving timing accuracy. The sub-blocks independently manage their clock signals, allowing for fine-grained control over clock distribution and reducing the impact of signal degradation over long distances. This design is particularly useful in high-performance ICs where precise timing and low power consumption are critical.
15. An integrated circuit, comprising: a main clock generator providing a main clock signal; a reference clock generator providing a reference clock signal; a block having a block boundary, wherein the block receives the main clock signal from the main clock generator and provides the main clock signal along a main clock-tree, and receives the reference clock signal from the reference clock generator and provides the reference clock signal along a reference clock-tree; and a plurality of sub-blocks disposed within the block boundary of the block, wherein each sub-block of the plurality of sub-blocks, receives the main clock signal from within the block boundary of the block via the main clock-tree, and receives the reference clock signal from within the block boundary of the block via the reference clock-tree, and compares the main clock signal to the reference clock signal so as to check for one or more errors associated with the main clock signal.
This invention relates to integrated circuits with clock signal verification mechanisms. The problem addressed is ensuring the integrity of clock signals in integrated circuits, particularly detecting errors in the main clock signal by comparing it to a reference clock signal. The solution involves an integrated circuit with a main clock generator producing a main clock signal and a reference clock generator producing a reference clock signal. A block within the circuit receives both clock signals and distributes them internally via separate clock-trees: a main clock-tree for the main clock signal and a reference clock-tree for the reference clock signal. Multiple sub-blocks are placed within the block's boundary, each receiving both clock signals from within the block. Each sub-block compares the main clock signal to the reference clock signal to detect errors in the main clock signal. This design allows for distributed error checking across the integrated circuit, improving reliability by verifying clock signal integrity at multiple points within the circuit. The reference clock signal serves as a reliable benchmark for detecting discrepancies in the main clock signal, ensuring accurate timing and reducing the risk of system failures due to clock errors.
16. The integrated circuit of claim 15 , wherein the reference clock signal is asynchronous with respect to the main clock signal.
The invention relates to integrated circuits designed for clock signal management, specifically addressing synchronization challenges between multiple clock domains. The problem solved is the need to ensure reliable operation when different clock signals, such as a reference clock and a main clock, operate asynchronously. Asynchronous clock signals can lead to timing errors, metastability, or data corruption in digital systems. The invention provides an integrated circuit with a clock synchronization mechanism that handles asynchronous reference and main clock signals. The circuit includes a phase detector to compare the phases of the two clock signals, a control logic to adjust the timing based on the phase difference, and a clock generator to produce a synchronized output. The asynchronous nature of the reference and main clock signals means they do not share a fixed phase relationship, requiring robust synchronization to prevent errors. The integrated circuit ensures proper alignment of data transfers and operations between the two clock domains, improving system stability and performance. This solution is particularly useful in applications where multiple independent clock sources must interact, such as in communication systems, processors, or mixed-signal circuits. The invention enhances reliability by mitigating risks associated with asynchronous clock interactions.
17. The integrated circuit of claim 15 , wherein each sub-block of the plurality of sub-blocks has a divergent node that receives the main clock signal from within the block boundary of the block via the main clock-tree and diverges the main clock signal into a first clock signal and a second clock signal.
This invention relates to integrated circuit design, specifically addressing clock distribution challenges in large-scale circuits. The problem solved is the efficient and synchronized distribution of clock signals across multiple sub-blocks within an integrated circuit block to minimize skew and power consumption. The integrated circuit includes a block with a main clock-tree that distributes a main clock signal within the block boundary. The block is divided into multiple sub-blocks, each containing a divergent node. Each divergent node receives the main clock signal from the main clock-tree and splits it into two distinct clock signals: a first clock signal and a second clock signal. This divergence allows for localized clock distribution within each sub-block, reducing the load on the main clock-tree and improving signal integrity. The divergent nodes ensure that the clock signals are distributed with minimal delay and skew, enhancing overall circuit performance. The design also supports power optimization by reducing unnecessary clock signal propagation across the entire block.
18. The integrated circuit of claim 17 , wherein each sub-block of the plurality of sub-blocks provides the first clock signal along a first clock-tree disposed within a sub-block boundary of each sub-block, and wherein each sub-block of the plurality of sub-blocks provides the second clock signal along a second clock-tree disposed within the sub-block boundary of each sub-block.
This invention relates to integrated circuits with improved clock distribution networks. The problem addressed is the inefficiency and complexity of traditional clock distribution systems, which often suffer from skew, power consumption, and routing congestion. The solution involves dividing the integrated circuit into multiple sub-blocks, each containing its own independent clock distribution network. Each sub-block receives and distributes two distinct clock signals: a first clock signal and a second clock signal. The first clock signal is routed through a first clock-tree structure entirely within the boundaries of each sub-block, while the second clock signal is routed through a second clock-tree structure also confined within the same sub-block boundaries. This modular approach allows for localized clock management, reducing skew, optimizing power efficiency, and simplifying routing. The sub-blocks may be arranged in a grid or other configuration, with each sub-block handling its own clock distribution independently of others. This design enables better scalability and adaptability for different integrated circuit designs and applications.
19. The integrated circuit of claim 18 , wherein the first clock-tree and the second clock-tree are separate and isolated within each sub-block of the plurality of sub-blocks from the main clock-tree and the reference clock-tree of the block.
This invention relates to integrated circuit (IC) design, specifically addressing clock distribution challenges in large-scale ICs. The problem solved is the need for efficient, isolated clock distribution within sub-blocks of an IC to prevent interference and improve timing accuracy. The IC includes a main clock-tree and a reference clock-tree for distributing clock signals across the entire block. Within each sub-block of the plurality of sub-blocks, there are separate and isolated first and second clock-trees. These sub-block clock-trees are isolated from the main and reference clock-trees of the block, ensuring that clock signals within each sub-block operate independently. This isolation prevents clock skew, noise, and interference between sub-blocks and the main block, improving overall timing performance and reliability. The sub-block clock-trees are designed to distribute clock signals locally within their respective sub-blocks, allowing for precise timing control and reduced latency. The isolation ensures that any disturbances in one sub-block do not propagate to others, maintaining signal integrity. This architecture is particularly useful in high-performance ICs where clock synchronization and noise immunity are critical.
20. The integrated circuit of claim 18 , wherein the first clock-tree distributes the first clock signal to first block circuitry disposed within each sub-block of the plurality of sub-blocks, and wherein the second clock-tree distributes the second clock signal to second block circuitry disposed within each sub-block of the plurality of sub-blocks.
This invention relates to integrated circuit (IC) clock distribution systems, specifically addressing the challenge of efficiently distributing multiple clock signals to different circuit blocks within a partitioned IC layout. The IC includes a plurality of sub-blocks, each containing distinct first and second block circuitry. A first clock-tree network distributes a first clock signal to the first block circuitry within each sub-block, while a second clock-tree network distributes a second clock signal to the second block circuitry within each sub-block. This dual-clock-tree architecture enables independent clocking of different functional units, improving power efficiency and performance by allowing separate clock domains to operate at different frequencies or phases. The design ensures that each sub-block receives its required clock signals without interference, supporting modular and scalable IC designs. The invention optimizes clock distribution by minimizing skew and reducing power consumption, particularly in large-scale ICs with complex timing requirements. The clock-trees are structured to maintain signal integrity across the sub-blocks, facilitating synchronized operation of the first and second block circuitry within each sub-block. This approach is useful in applications requiring multi-domain clocking, such as processors, communication chips, or mixed-signal ICs.
21. The integrated circuit of claim 18 , wherein each sub-block of the plurality of sub-blocks has first block circuitry and second block circuitry, wherein the first block circuitry receives the first clock signal from the first clock-tree and provides one or more first output signals based on the first clock signal, and wherein the second block circuitry receives the second clock signal from the second clock-tree and provides one or more second output signals based on the second clock signal.
An integrated circuit includes multiple sub-blocks, each containing two types of circuitry: first block circuitry and second block circuitry. The first block circuitry receives a first clock signal from a first clock-tree and generates one or more output signals based on this clock signal. The second block circuitry receives a second clock signal from a second clock-tree and generates one or more output signals based on this second clock signal. The integrated circuit is designed to distribute clock signals efficiently across different sub-blocks, ensuring synchronized operation while allowing independent clock domains. This architecture supports complex timing requirements, such as those in high-performance computing or communication systems, where different functional blocks may require different clock frequencies or phases. The separation of clock trees and dedicated circuitry for each sub-block helps reduce skew and improve power efficiency by isolating clock domains. This design is particularly useful in applications requiring precise timing control, such as digital signal processing, microprocessors, or mixed-signal integrated circuits.
22. The integrated circuit of claim 21 , wherein each sub-block of the plurality of sub-blocks has lock-step checker circuitry that receives the first clock signal from the first clock-tree, receives the one or more first output signals from the first block circuitry, receives the second clock signal from the second clock-tree, receives the one or more second output signals from the second block circuitry, and provides a lock-step error signal based on the first clock signal, the one or more first output signals, the second clock signal, and the one or more second output signals.
An integrated circuit includes multiple sub-blocks, each containing functional circuitry and associated clock-tree networks. The sub-blocks are designed to operate in a lock-step mode, where identical operations are performed simultaneously across redundant circuitry to detect errors. Each sub-block includes lock-step checker circuitry that monitors the synchronization and consistency of signals between redundant blocks. The checker circuitry receives a first clock signal from a first clock-tree and a second clock signal from a second clock-tree, ensuring both clock domains are aligned. It also receives output signals from both the primary and redundant block circuitry, comparing these signals to detect mismatches. If discrepancies are found, the checker generates a lock-step error signal, indicating a potential fault in the system. This design enhances fault detection in safety-critical applications by continuously verifying that redundant circuits produce identical results under identical conditions. The lock-step checker circuitry operates independently within each sub-block, allowing localized error detection without requiring global synchronization. This approach improves reliability in systems where redundant processing is used to mitigate hardware failures.
23. The integrated circuit of claim 15 , wherein each sub-block of the plurality of sub-blocks has a distributed clock checker that receives the main clock signal, receives the reference clock signal, and provides a clock error signal.
The invention relates to integrated circuits with distributed clock error detection. The problem addressed is ensuring reliable clock synchronization across multiple sub-blocks within an integrated circuit, where clock signal integrity is critical for proper operation. The invention provides an integrated circuit with a plurality of sub-blocks, each containing a distributed clock checker. The clock checker in each sub-block receives both a main clock signal and a reference clock signal. By comparing these signals, the clock checker generates a clock error signal if a discrepancy is detected. This allows for localized error detection within each sub-block, improving fault isolation and system reliability. The main clock signal is distributed to the sub-blocks, while the reference clock signal serves as a benchmark for comparison. The clock error signal can trigger corrective actions or alerts to maintain system stability. This distributed approach enhances fault tolerance by enabling individual sub-blocks to detect and respond to clock errors independently, reducing the risk of cascading failures. The invention is particularly useful in high-performance computing, telecommunications, and other applications where precise timing is essential.
24. An integrated circuit, comprising: a main clock generator providing a main clock signal; a reference clock generator providing a reference clock signal; a block having a block boundary, wherein the block: receives the main clock signal from the main clock generator and provides the main clock signal along a main clock-tree, and receives the reference clock signal from the reference clock generator and provides the reference clock signal along a reference clock-tree; and a plurality of sub-blocks disposed within the block boundary of the block, wherein each sub-block of the plurality of sub-blocks: receives the main clock signal from within the block boundary of the block via the main clock-tree, receives the reference clock signal from within the block boundary of the block via the reference clock-tree, and diverges the main clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block, wherein the block further comprises a clock checker that: receives the main clock signal from within the block boundary of the block via the main clock-tree, receives the reference clock signal from within the block boundary of the block via the reference clock-tree, and compares the main clock signal to the reference clock signal so as to check for one or more errors associated with the main clock signal.
This invention relates to integrated circuits with improved clock signal distribution and error detection. The problem addressed is ensuring reliable clock signal integrity in complex integrated circuits, where clock distribution errors can lead to system failures. The solution involves a hierarchical clock distribution system with dual clock trees and error checking. The integrated circuit includes a main clock generator producing a main clock signal and a reference clock generator producing a reference clock signal. A primary block receives both clock signals and distributes them internally via separate main and reference clock trees. Within this block, multiple sub-blocks receive both clock signals from the block's internal clock trees. Each sub-block further divides the main clock signal into two separate clock signals for internal use. Additionally, the block includes a clock checker that monitors both the main and reference clock signals. By comparing these signals, the clock checker detects errors in the main clock signal, such as phase shifts, frequency deviations, or signal degradation. This dual-clock architecture with integrated error detection enhances system reliability by identifying clock distribution issues before they cause operational failures. The hierarchical distribution ensures efficient clock signal propagation while maintaining the ability to verify signal integrity at multiple levels.
25. The integrated circuit of claim 24 , wherein the reference clock signal is asynchronous with respect to the main clock signal.
The invention relates to integrated circuits designed to manage clock signals, specifically addressing synchronization challenges between different clock domains. The integrated circuit includes a main clock signal generator and a reference clock signal generator, where the reference clock signal operates asynchronously with respect to the main clock signal. This asynchronous relationship ensures that the reference clock signal does not share a fixed phase or frequency relationship with the main clock signal, preventing potential synchronization issues that could arise from direct coupling or phase-locked operation. The integrated circuit may further include a synchronization module that facilitates communication or data transfer between the two clock domains, ensuring reliable operation despite their independent timing. The reference clock signal can be used for timing-critical functions, such as error detection, system monitoring, or secondary processing tasks, while the main clock signal drives primary operations. By maintaining asynchrony, the design avoids clock domain crossing problems, reduces jitter, and improves overall system stability. The invention is particularly useful in applications requiring precise timing control, such as digital signal processing, communication systems, or embedded systems with multiple independent clock sources.
26. The integrated circuit of claim 24 , further comprising: a shared clock checker that receives the main clock signal, receives the reference clock signal, receives a data input signal, provides a clock error signal, and provides a data output signal, wherein a first sub-block of the plurality of sub-blocks includes a first synchronizer that receives the data output signal from the shared clock checker and provides a first sync output signal, and wherein a second sub-block of the plurality of sub-blocks includes a second synchronizer that receives the first sync output signal from the first synchronizer and provides a second sync output signal to the shared clock checker as the data input signal.
This invention relates to integrated circuits with clock synchronization and error detection. The problem addressed is ensuring reliable data transfer between sub-blocks operating on different clock domains, particularly when clock signals may be misaligned or corrupted. The integrated circuit includes a shared clock checker that monitors both a main clock signal and a reference clock signal to detect timing errors. The checker processes a data input signal and generates a clock error signal if discrepancies are found, while also producing a corrected data output signal. The circuit further includes multiple sub-blocks, each with synchronizers that handle data passing between them. A first sub-block contains a synchronizer that receives the data output from the shared clock checker and generates a synchronized output. A second sub-block contains another synchronizer that takes this synchronized output and provides a second synchronized signal back to the shared clock checker as the data input. This feedback loop ensures continuous synchronization and error detection across the sub-blocks, improving system reliability in mixed-clock environments. The design is particularly useful in applications requiring high-speed data transfer with minimal latency and robust error handling.
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March 10, 2020
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