Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An arithmetic circuit comprising: first to N-th, N being an integer equal to or larger than two, element circuits each of which includes: input circuits configured to input first operand data and second operand data; and an element data selector configured to select the first operand data or the second operand data of any one of the first to N-th element circuits on the basis of a request element signal; and a data bus, provided in common to the first to N-th element circuits, configured to supply the first operand data or the second operand data input by each of the first to N-th element circuits to the element data selector of each of the first to N-th element circuits, wherein: each of the first to N-th element circuits has a corresponding element number, each of the first to N-th element circuits includes: an operand selector configured to: select, when a control signal is in a first state, the first operand data to output to the data bus, and select, when the control signal is in a second state, on the basis of an operand switch signal that indicates whether or not a shift amount, which is common for the first to N-th element circuits, is larger than the corresponding element number, the first operand data or the second operand data to output to the data bus, and the element data selector in each of the first to N-th element circuits: selects, when the control signal is in the first state, on the basis of a first request element signal included in the second operand data, the first operand data of any one of the first to N-th element circuits, and selects, when the control signal is in the second state, on the basis of a second request element signal that is generated by adding the corresponding element number to the shift amount, the first operand data or the second operand data selected by the operand selector of any one of the first to N-th element circuits.
This invention relates to an arithmetic circuit designed to efficiently select and process operand data across multiple element circuits. The circuit addresses the challenge of managing data selection in parallel arithmetic operations, particularly in systems requiring dynamic operand shifting or element-specific data access. The circuit includes N element circuits, where N is an integer of two or more, each with input circuits for receiving first and second operand data. Each element circuit also includes an operand selector that outputs either the first operand data or the second operand data to a shared data bus, depending on a control signal. When the control signal is in a first state, the operand selector outputs the first operand data. When the control signal is in a second state, the operand selector selects between the first and second operand data based on an operand switch signal, which indicates whether a common shift amount exceeds the element circuit's corresponding element number. The shared data bus supplies the selected operand data to an element data selector in each element circuit. In the first control state, the element data selector uses a first request element signal embedded in the second operand data to select the first operand data from any of the N element circuits. In the second control state, the element data selector uses a second request element signal, generated by adding the element number to the shift amount, to select the operand data from any of the N element circuits. This design enables flexible and efficient data routing in parallel arithmetic operations, supporting both direct and shifted operand access.
2. The arithmetic circuit according to claim 1 , further comprising: a valid bit adder configured to add up, when the control signal is in a third state, valid bits included in the second operand data input by the first to N-th element circuits, wherein each of the first to N-th element circuits includes a sum selector configured to output, when the control signal is in the third state, a sum output by the valid bit adder instead of a part of an output of the corresponding element data selector.
This invention relates to arithmetic circuits, specifically those designed to handle data with variable precision or validity flags. The problem addressed is efficiently processing data where certain elements may be invalid or require special handling, such as in floating-point arithmetic or data compression. The circuit includes multiple element circuits (first to N-th) that process input data elements. Each element circuit has a data selector that chooses between different output paths based on a control signal. The control signal can be in multiple states, including a third state that triggers a special operation. In this third state, a valid bit adder sums up valid bits from the second operand data across all element circuits. Each element circuit then outputs this summed value instead of its usual partial result. This allows the circuit to aggregate validity information or perform conditional operations without requiring external processing. The valid bit adder ensures that only valid data elements contribute to the sum, enabling efficient handling of partial data or error conditions. This approach reduces the need for additional logic outside the arithmetic circuit, improving performance and reducing complexity. The invention is particularly useful in systems where data validity must be tracked dynamically, such as in signal processing, cryptography, or error correction applications. By integrating validity checks into the arithmetic operations, the circuit simplifies system design and enhances reliability.
3. The arithmetic circuit according to claim 2 , wherein: each of the first to N-th element circuits includes a mask selector configured to select output of the corresponding element data selector or all-zero data, the arithmetic circuit further comprises a compress decoder configured to generate, when the control signal is in a fourth state, on the basis of valid bits included in the second operand data input by each of the first to N-th element circuits, compress decode signals each of which includes a mask signal and an element data selection signal for each of the first to N-th element circuits, and each of the first to N-th element circuits includes: a first compress selector configured to select, when the control signal is in the fourth state, the corresponding element data selection signal, instead of the request element signal; and a second compress selector configured to output the corresponding mask signal to the corresponding mask selector and cause the corresponding mask selector to select the all-zero data.
This invention relates to an arithmetic circuit designed for efficient data processing, particularly in scenarios involving compression and masking operations. The circuit processes first and second operand data, where the second operand data includes valid bits indicating active elements. The circuit comprises N element circuits, each configured to process a corresponding element of the operand data. Each element circuit includes a data selector that chooses between element data and all-zero data based on a request element signal. A mask selector in each element circuit further selects between the data selector's output or all-zero data. The circuit also includes a compress decoder that, when activated by a control signal in a fourth state, generates compress decode signals based on the valid bits of the second operand data. These signals include mask signals and element data selection signals for each element circuit. In this mode, a first compress selector in each element circuit overrides the request element signal with the corresponding element data selection signal, while a second compress selector directs the mask signal to the mask selector, causing it to output all-zero data. This design enables efficient compression and masking operations by dynamically controlling data flow and masking based on operand validity, improving processing efficiency in arithmetic circuits.
4. The arithmetic circuit according to claim 1 , wherein: each of the first to N-th element circuits includes a mask selector configured to select output of the corresponding element data selector or all-zero data, the arithmetic circuit further comprises a compress decoder configured to generate, when the control signal is in a fourth state, on the basis of valid bits included in the second operand data input by each of the first to N-th element circuits, compress decode signals each of which includes a mask signal and an element data selection signal for each of the first to N-th element circuits, and each of the first to N-th element circuits includes: a first compress selector configured to select, when the control signal is in the fourth state, the corresponding element data selection signal, instead of the request element signal; and a second compress selector configured to output the corresponding mask signal to the corresponding mask selector and cause the corresponding mask selector to select the all-zero data.
This invention relates to an arithmetic circuit designed for efficient data processing, particularly in systems requiring selective masking and compression of data elements. The circuit addresses the challenge of handling variable-length data streams or sparse data, where certain elements may need to be ignored or zeroed out during arithmetic operations. The circuit includes multiple element circuits, each capable of processing individual data elements from a first and second operand. Each element circuit contains a mask selector that can choose between the output of an element data selector or all-zero data, allowing for selective masking of elements. The circuit also includes a compress decoder that, when activated by a control signal in a fourth state, generates compress decode signals based on valid bits in the second operand. These signals include mask signals and element data selection signals for each element circuit. The first compress selector in each element circuit then uses the element data selection signal instead of a request element signal when the control signal is in the fourth state. The second compress selector outputs the mask signal to the mask selector, causing it to select all-zero data for masked elements. This design enables efficient compression and masking operations, improving performance in applications like sparse matrix computations or data filtering.
5. The arithmetic circuit according to claim 1 , wherein the first to N-th element circuits are first to N-th Single Instruction Multiple Data (SIMD) arithmetic elements respectively including: a first operand register to which the first operand data is input; a second operand register to which the second operand data is input; an arithmetic operator configured to receive inputs of the first operand data and second operand data and perform an arithmetic operation on the first operand data and second operand data; and a result register configured to store an arithmetic result output by the arithmetic operator.
This invention relates to an arithmetic circuit designed for efficient parallel processing, specifically utilizing Single Instruction Multiple Data (SIMD) architecture to enhance computational throughput. The circuit addresses the challenge of performing multiple arithmetic operations simultaneously on different data sets while maintaining low latency and high efficiency. The circuit comprises N SIMD arithmetic elements, each configured to process a pair of operand data inputs in parallel. Each SIMD arithmetic element includes a first operand register for storing the first input data, a second operand register for storing the second input data, an arithmetic operator that performs the specified arithmetic operation on the two operands, and a result register to store the output of the arithmetic operation. The SIMD architecture allows the same instruction to be applied across multiple data elements, significantly improving processing speed for tasks such as vector operations, matrix computations, and other parallelizable arithmetic tasks. The circuit is particularly useful in applications requiring high-performance computing, such as digital signal processing, machine learning, and scientific simulations, where parallel processing of large data sets is essential. The design ensures that each arithmetic element operates independently, enabling scalable and efficient parallel execution of arithmetic operations.
6. A control method for an arithmetic circuit including: first to N-th, N being an integer equal to or larger than two, Single Instruction Multiple Data (SIMD) arithmetic elements each of which includes: a first operand register to which first operand data is input; a second operand register to which second operand data is input; an arithmetic operator configured to receive inputs of the first operand data and the second operand data and perform an arithmetic operation on the first operand data and the second operand data; a result register configured to store an arithmetic result output by the arithmetic operator; and an element data selector configured to select the first operand data or the second operand data of any one of the first to N-th SIMD arithmetic elements on the basis of a request element signal; and a data bus, provided in common to the first to N-th SIMD arithmetic elements, configured to supply the first operand data or the second operand data input by each of the first to N-th SIMD arithmetic elements to the element data selector of each of the first to N-th SIMD arithmetic elements, the control method comprising: an operand selector in each of the first to N-th SIMD arithmetic elements: selecting when a control signal is in a first state, the first operand data to output to the data bus, and selecting, when the control signal is in a second state, on the basis of an operand switch signal that indicates whether or not a shift amount, which is common for the first to N-th SIMD arithmetic elements, is larger than a corresponding element number that each of the first N-th SIMD arithmetic elements has, the first operand data or the second operand data to output to the data bus, and the element data selector in each of the first to N-th SIMD arithmetic elements: selecting, when the control signal is in the first state, on the basis of a first request element signal included in the second operand data, the first operand data of any one of the first to N-th SIMD arithmetic elements, and selecting, when the control signal is in the second state, on the basis of a second request element signal that is generated by adding the corresponding element number to the shift amount, the first operand data or the second operand data selected by the operand selector of any one of the first to N-th SIMD arithmetic elements.
This invention relates to a control method for an arithmetic circuit with Single Instruction Multiple Data (SIMD) arithmetic elements. The problem addressed is efficient data sharing and selection among multiple SIMD elements to optimize arithmetic operations. The circuit includes N SIMD arithmetic elements, each with operand registers, an arithmetic operator, a result register, and an element data selector. A common data bus connects all elements, allowing them to share operand data. The control method involves two states: in the first state, an element selects its first operand data for output to the bus based on a request element signal. In the second state, the selection depends on an operand switch signal that compares a common shift amount with each element's number. If the shift amount exceeds the element number, the second operand data is selected; otherwise, the first operand data is chosen. The element data selector then retrieves data from another element based on either a first request element signal (first state) or a second request element signal (second state), which is derived by adding the shift amount to the element number. This method enables flexible and efficient data sharing across SIMD elements, improving arithmetic processing performance.
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March 17, 2020
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