Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A signal supply circuit used for a display panel comprising a plurality of subpixels each comprising a memory, the signal supply circuit comprising: a latch circuit receiving a serial data as a first video data, a register circuit outputting a latch pulse to the latch circuit, a parallel conversion circuit converting the serial data latched by the latch circuit to a parallel digital data, an allocation circuit allocating the parallel digital data to each of the subpixels, and an input adaptive control circuit receiving identification information of the display panel from outside the display panel, wherein in a first mode, the register circuit outputs n cyclic latch pulses to the latch circuit for receiving the first video data in a unit of n bits from outside the display panel, when a unit of m bits corresponds to the subpixels in the first mode, the allocation circuit cuts parallel digital data that does not correspond to the subpixels and supplies parallel digital data for the unit of m bits corresponding to the subpixels based on the identification information from the input adaptive control circuit, and wherein n>m.
This invention relates to a signal supply circuit for a display panel with subpixels, each containing memory. The circuit addresses the challenge of efficiently transmitting and processing video data for display panels with varying subpixel configurations. The circuit includes a latch circuit that receives serial data as video input, a register circuit that generates latch pulses for the latch circuit, a parallel conversion circuit that transforms the latched serial data into parallel digital data, and an allocation circuit that distributes this data to individual subpixels. An input adaptive control circuit receives panel identification information to adapt the data processing. In a first mode, the register circuit outputs n cyclic latch pulses to capture video data in n-bit units from an external source. When the subpixels require m-bit units (where n > m), the allocation circuit trims excess parallel digital data and supplies only the relevant m-bit data to the subpixels, based on the identification information from the input adaptive control circuit. This ensures compatibility with different display panel configurations by dynamically adjusting data allocation. The system optimizes data transmission and processing efficiency by avoiding unnecessary data handling for subpixels that do not require full n-bit units.
2. The signal supply circuit of claim 1 , wherein dummy video data is included in the first video data of the first mode.
A signal supply circuit is designed to provide video data to a display device, particularly for use in electronic devices such as smartphones, tablets, or other portable displays. The circuit operates in multiple modes, including a first mode where it supplies video data to a display panel. In this first mode, the circuit includes dummy video data within the first video data stream. The dummy video data is inserted to ensure proper timing, synchronization, or signal integrity, which is critical for maintaining display quality and preventing artifacts. The inclusion of dummy data helps compensate for variations in signal processing delays or to meet specific display panel requirements. The circuit may also include additional features such as signal conditioning, timing control, or data formatting to ensure reliable video output. The dummy data may be structured to match the format of the active video data or may be a predefined pattern to facilitate synchronization. This approach improves display performance by ensuring consistent signal delivery and reducing potential errors in the video output.
3. The signal supply circuit of claim 1 , further comprising a second mode, wherein the second mode is a mode which receives second video data corresponding to the subpixels in a unit of n bits from outside, and supplies digital data for the subpixels to the subpixels, and the digital data is obtained by change to a unit of k bits corresponding to the subpixels based on the second video data.
This invention relates to a signal supply circuit for video display systems, specifically addressing the challenge of efficiently processing and supplying digital data to subpixels in a display. The circuit operates in a first mode where it receives first video data corresponding to subpixels in a unit of m bits from an external source and converts this data into digital data for the subpixels in a unit of k bits. The conversion involves adjusting the bit depth to match the requirements of the subpixels. In a second mode, the circuit receives second video data corresponding to subpixels in a unit of n bits from an external source and similarly converts this data into digital data for the subpixels in a unit of k bits. The conversion process ensures that the digital data supplied to the subpixels is optimized for display, regardless of the input bit depth. This dual-mode operation allows the circuit to handle different input data formats while maintaining consistent output for the subpixels, enhancing flexibility and compatibility with various video sources. The invention improves the efficiency and adaptability of signal processing in display systems by dynamically adjusting the bit depth of video data to match the subpixel requirements.
4. The signal supply circuit of claim 1 , further comprising: a data input adaptive control circuit which obtains at least a command and a data sectional signal from external serial data; and a serial data processing circuit which separates the first video data transmitted from the outside into parallel data in accordance with the data sectional signal from the input adaptive control circuit.
This invention relates to signal supply circuits for processing video data, particularly in systems where external serial data must be converted into parallel video data for display or further processing. The problem addressed is the need for efficient and adaptive handling of serial data inputs, including extracting commands and data sections, and converting high-speed serial video data into parallel data for use in display devices or other systems. The signal supply circuit includes a data input adaptive control circuit that receives external serial data and extracts at least a command and a data sectional signal. The data sectional signal indicates the boundaries of video data segments within the serial stream. A serial data processing circuit then uses this information to separate the incoming first video data into parallel data, ensuring proper synchronization and alignment of the video data for downstream processing. The adaptive control circuit dynamically adjusts to variations in the serial data format, allowing compatibility with different input standards or configurations. This ensures reliable data extraction and conversion, even in environments where the serial data structure may vary. The invention improves the flexibility and robustness of video data handling in electronic systems.
5. The signal supply circuit of claim 4 , further comprising a mode control circuit which switches an operation mode in accordance with the command.
A signal supply circuit is designed to provide a stable and controlled signal output, particularly in applications where signal integrity and adaptability are critical. The circuit addresses the challenge of maintaining signal quality under varying operating conditions by incorporating a mode control circuit. This mode control circuit dynamically adjusts the operation mode of the signal supply circuit in response to external commands. The adjustment may involve altering signal characteristics such as amplitude, frequency, or timing to optimize performance for different operational scenarios. The mode control circuit ensures that the signal supply circuit can adapt to changing requirements without compromising stability or accuracy. This adaptability is particularly useful in systems where the signal supply must accommodate different modes of operation, such as power-saving modes, high-performance modes, or specialized operational states. By integrating the mode control circuit, the signal supply circuit enhances its versatility and reliability in diverse applications, including communication systems, power management, and signal processing. The circuit's ability to switch operation modes in response to commands allows for seamless integration into systems requiring dynamic signal adjustments.
6. A display device comprising: a plurality of subpixels arranged on a display area of a display panel and each comprising a memory; a serial data processing circuit arranged on the display panel and which is supplied with serial data, applies parallel conversion to serial video data included in the serial data, and outputs parallel video data; a data conversion circuit which obtains the output parallel video data by latching the parallel video data and allocating the latched data to corresponding subpixels of the display panel in an allocation process; and an input adaptive control circuit which controls the parallel conversion operation of the serial data processing circuit and latch timing and a form of the allocation process of the data conversion circuit in accordance with type information of a layout of the subpixels of the display panel and a mode of the serial video data included in the serial data, wherein the serial data processing circuit comprises register circuits and latch circuits, the register circuits circulate at least a cyclic latch pulse, a number of the cyclic latch pulse is determined in accordance with the mode of the serial video data, the latch circuits output the parallel video data to the data conversion circuit based on each latch cyclic latch pulse from the register circuits, the data conversion circuit comprises an allocation circuit, the allocation circuit changes and outputs the output parallel video data in accordance with the type information of the layout of the subpixels of the display panel and a mode table of the serial video data included in the serial data, and the mode table indicates that the mode of the serial video data is one of: a 4 bit-data mode, a 3 bit-data mode, a 1 bit-data mode.
A display device includes a display panel with subpixels, each containing memory, arranged in a specific layout. The device processes serial video data by converting it into parallel video data using a serial data processing circuit. This circuit includes register and latch circuits that circulate a cyclic latch pulse, with the number of pulses determined by the mode of the serial video data (e.g., 4-bit, 3-bit, or 1-bit data modes). The latch circuits then output the parallel video data to a data conversion circuit, which latches the data and allocates it to the corresponding subpixels based on their layout. An input adaptive control circuit adjusts the parallel conversion operation, latch timing, and allocation process according to the subpixel layout type and the serial video data mode. The allocation circuit within the data conversion circuit modifies the output parallel video data to match the subpixel arrangement and the specified mode. This system ensures efficient data handling and display output by dynamically adapting to different subpixel configurations and data formats.
7. The display device of claim 6 , wherein the number of bits of the serial video data included in the serial data is eight, and the data conversion circuit cuts output parallel video data that does not correspond to the subpixels and outputs the allocated output parallel video data in a unit less than 8 bits.
This invention relates to a display device that processes serial video data for display on a screen with subpixels. The problem addressed is efficiently converting serial video data into parallel video data while accounting for subpixel arrangements that may not require all bits of the input data. The display device includes a data conversion circuit that receives serial video data, typically 8 bits per pixel, and converts it into parallel video data for driving the display. The circuit is designed to handle cases where the subpixel configuration does not require all 8 bits of the input data. In such cases, the circuit selectively outputs only the relevant bits of the parallel video data, effectively discarding unused bits. This ensures that the display driver receives only the necessary data, improving efficiency and reducing unnecessary processing. The invention is particularly useful in displays where subpixels are arranged in a way that does not fully utilize the input data bits, such as in certain color filter configurations or subpixel rendering techniques. The data conversion circuit dynamically adjusts the output based on the subpixel requirements, ensuring accurate and efficient display operation.
8. The display device of claim 6 , wherein the serial video data of the serial data is Obit-data mode including red (R), green (G), blue (B) and a dummy (DUM), 3 bit-data mode including red (R), green (G) and blue (B), or 1 bit-data mode including 1 and 0.
A display device is designed to process and display video data in various serial data formats. The device addresses the challenge of handling different types of serial video data, ensuring compatibility and proper display across multiple input formats. The serial video data may include Obit-data mode, which consists of red (R), green (G), blue (B), and a dummy (DUM) bit. Alternatively, the data may be in a 3-bit mode, containing only red (R), green (G), and blue (B) components, or a 1-bit mode, representing binary values of 1 and 0. The display device is configured to interpret and process these different data modes, ensuring accurate color representation and display functionality. This flexibility allows the device to support a wide range of input sources and applications, enhancing its versatility in various display environments. The device may also include additional components, such as a timing controller and a data driver, to manage the timing and distribution of the video data for proper display output. The system ensures that the video data is correctly decoded and displayed, regardless of the input format, improving compatibility and user experience.
9. The display device of claim 6 , wherein the serial data includes address data indicating a write destination of the parallel video data.
A display device includes a serial interface for receiving serial data and parallel video data, where the serial data includes address data specifying the write destination of the parallel video data. The device converts the serial data into parallel data and writes it to a memory based on the address data. The parallel video data is then processed and displayed. This system improves data transfer efficiency by embedding address information within the serial data stream, reducing the need for separate control signals. The display device may include a timing controller that decodes the serial data to extract the address and synchronizes the write operation with the parallel video data. The address data ensures that the parallel video data is correctly mapped to the intended memory locations, preventing misalignment or errors in the display output. This approach is particularly useful in high-resolution displays where precise timing and accurate data placement are critical. The invention simplifies the interface design by integrating address information into the serial data, reducing hardware complexity and improving reliability.
10. The display device of claim 6 , wherein when the display panel comprises an array of red (R), green (G) and blue (B) subpixels, and the mode of the serial video data is a 4 bit-data mode including red (R), green (G), blue (B) and dummy (DUM) video data items, the data conversion circuit discards the dummy (DUM) video data item and outputs the red (R), green (G) and blue (B) video data items as the output parallel video data in the allocation process.
A display device includes a display panel with an array of red (R), green (G), and blue (B) subpixels and a data conversion circuit. The display panel receives serial video data in a 4-bit mode, which includes red (R), green (G), blue (B), and dummy (DUM) video data items. The data conversion circuit processes this serial video data by discarding the dummy (DUM) data item and outputting only the R, G, and B video data items as parallel video data. This conversion ensures that the display panel receives the correct color data for each subpixel, maintaining proper image display. The data conversion circuit performs this allocation process to filter out unnecessary dummy data, optimizing the data transmission and display accuracy. The display device is designed to handle different video data modes efficiently, ensuring compatibility with various input signals while maintaining high-quality image output.
11. The display device of claim 6 , wherein when the display panel comprises an array of red (R), green (G) and blue (B) subpixels, and the mode of the serial video data is a 3 bit-data mode including red (R), green (G) and blue (B) video data items, the data conversion circuit outputs the red (R), green (G) and blue (B) video data items as the output parallel video data in the allocation process.
This invention relates to display devices, specifically those that process serial video data for display on a panel with red, green, and blue (RGB) subpixels. The problem addressed is efficiently converting serial video data into parallel data for display, particularly when the data is in a compressed 3-bit mode containing RGB video data items. The display device includes a data conversion circuit that processes serial video data and outputs parallel video data for the display panel. In cases where the display panel has an array of RGB subpixels and the serial video data is in a 3-bit mode containing separate R, G, and B data items, the data conversion circuit directly outputs these R, G, and B data items as the parallel video data during the allocation process. This ensures accurate and efficient data mapping to the corresponding subpixels without additional processing steps. The invention optimizes data handling in display systems where video data is transmitted in a compact format, reducing latency and improving display performance. The solution is particularly useful in applications requiring high-speed data processing, such as high-resolution or high-refresh-rate displays.
12. The display device of claim 6 , wherein when the display panel comprises an array of red (R), green (G), blue (B) and white (W) subpixels, and the mode of the serial video data is a 3 bit-data mode including red (R), green (G) and blue (B) video data items, the data conversion circuit generates a video data item corresponding to white (W) from the red (R), green (G) and blue (B) video data items, and outputs the red (R), green (G), blue (B) and white (W) video data items as the output parallel video data in the allocation process.
A display device includes a display panel with an array of red (R), green (G), blue (B), and white (W) subpixels and a data conversion circuit. The display panel is configured to receive serial video data in a 3-bit mode, where the data includes only red, green, and blue video data items. The data conversion circuit processes this input by generating a white (W) video data item from the red, green, and blue video data items. The circuit then outputs parallel video data that includes all four color components (R, G, B, and W) in a specific allocation process. This allows the display to utilize the white subpixels for improved brightness and efficiency while maintaining compatibility with standard 3-bit RGB input signals. The solution addresses the challenge of efficiently driving a display with additional white subpixels when the input data lacks a dedicated white channel, enhancing display performance without requiring changes to the input signal format.
13. The display device of claim 6 , wherein when the display panel comprises an array of red (R), green (G) and blue (B) subpixels, and the mode of the serial video data is a 1 bit-data mode including 1 and 0, the data conversion circuit outputs 1 bit of serial video data as the output parallel video data in the allocation process.
This invention relates to display devices, specifically those with an array of red (R), green (G), and blue (B) subpixels, and addresses the challenge of efficiently processing serial video data in a 1-bit data mode. The display device includes a data conversion circuit that converts serial video data into parallel video data for driving the display panel. In the 1-bit data mode, where the serial video data consists of binary values (1 or 0), the data conversion circuit outputs 1 bit of the serial video data as the parallel video data during the allocation process. This ensures compatibility with low-bit-depth video signals while maintaining efficient data handling. The display device may also include a timing controller that generates control signals to manage the data conversion process, ensuring proper synchronization between the serial input and parallel output. The invention optimizes data processing for displays operating in minimal bit-depth modes, reducing complexity while ensuring accurate pixel rendering.
14. The display device of claim 6 , wherein the serial data is supplied from a video data supply device to the serial data processing circuit wirelessly or via a line.
A display device includes a serial data processing circuit that receives and processes serial data to generate display signals for driving a display panel. The serial data processing circuit converts the serial data into parallel data, performs error detection and correction, and generates timing control signals to synchronize the display panel. The display device also includes a display panel driver circuit that receives the processed data and timing signals to drive the display panel. The serial data is supplied from a video data supply device to the serial data processing circuit either wirelessly or via a wired connection. The video data supply device may include a video source, such as a computer, media player, or broadcast receiver, that generates or transmits the serial data. The display device may be part of a television, monitor, or other display system. The serial data processing circuit ensures reliable data transmission and accurate display timing, addressing issues related to data integrity and synchronization in display systems. The wired or wireless transmission allows for flexible connectivity between the video data supply device and the display device.
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March 17, 2020
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