Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory device, comprising: a memory array comprising a first sector and a second sector, each of the first sector and the sector comprising a respective plurality of memory cells arranged in rows and columns, a respective plurality of word lines, and a respective plurality of local bit lines; a plurality of main bit lines selectively coupled to local bit lines; a first sense amplifier and a second sense amplifier; and a routing circuit arranged between the plurality of main bit lines and the first sense amplifier and the second sense amplifier, wherein the routing circuit comprises: a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier; a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier; a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier; a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier; a lower coupling circuit coupling a second lower main bit line to a second input of the first sense amplifier; and an upper coupling circuit coupling a second upper main bit line to a second input of the second sense amplifier.
The invention relates to memory devices, specifically addressing the challenge of efficiently routing data between memory arrays and sense amplifiers to improve read and write operations. The memory device includes a memory array divided into at least two sectors, each containing multiple memory cells organized in rows and columns, along with corresponding word lines and local bit lines. A set of main bit lines is selectively coupled to the local bit lines to facilitate data transfer. The device features two sense amplifiers and a routing circuit that connects the main bit lines to these amplifiers. The routing circuit includes multiple switches and coupling circuits that enable flexible routing of data from different main bit lines to the sense amplifiers. Specifically, lower and upper switches connect a first lower and upper main bit line to the first inputs of both sense amplifiers, while lower and upper coupling circuits connect a second lower and upper main bit line to the second inputs of the respective sense amplifiers. This configuration allows for efficient data routing, reducing latency and improving performance in memory access operations. The design ensures that data from different sectors can be routed to the appropriate sense amplifiers without interference, enhancing overall memory device functionality.
2. The memory device according to claim 1 , wherein at least one of the first lower main bit line or the second lower main bit line is coupled to the local bit lines of the first sector.
A memory device includes a memory array divided into sectors, each sector containing multiple local bit lines connected to a first lower main bit line and a second lower main bit line. The memory device is designed to improve data access efficiency and reduce power consumption by selectively coupling local bit lines to the main bit lines. In this configuration, at least one of the first or second lower main bit lines is directly connected to the local bit lines of a first sector. This allows for targeted data access within the sector, minimizing unnecessary power usage by isolating operations to specific sectors rather than the entire memory array. The design enhances performance by reducing signal interference and improving data transfer rates. The memory device may also include additional sectors with similar configurations, enabling scalable and efficient memory management. The selective coupling mechanism ensures that only the relevant sectors are activated during read or write operations, optimizing energy efficiency and operational speed. This approach is particularly useful in high-density memory systems where minimizing power consumption and maximizing data throughput are critical.
3. The memory device according to claim 1 , wherein at least one of the first upper main bit line or the second upper main bit line is coupled to the local bit lines of the second sector.
A memory device includes a memory array divided into multiple sectors, each sector containing memory cells arranged in rows and columns. The device uses a hierarchical bit line structure with upper main bit lines and local bit lines to improve signal integrity and reduce power consumption. The upper main bit lines are shared across multiple sectors, while the local bit lines connect to individual memory cells within a sector. This hierarchical structure allows for efficient data access and reduces the capacitive loading on the bit lines, improving read and write performance. The invention addresses the challenge of scaling memory devices by minimizing signal interference and power dissipation in high-density memory arrays. In this specific embodiment, at least one of the upper main bit lines is coupled to the local bit lines of a second sector, enabling shared access between sectors. This configuration enhances flexibility in data routing and reduces the need for redundant bit line structures, further optimizing the memory device's efficiency and scalability. The memory cells may be non-volatile, such as flash memory cells, or other types of memory cells requiring precise control of bit line connections. The hierarchical bit line architecture ensures reliable data transfer while maintaining low power consumption and high-speed operation.
4. A memory device comprising a memory array comprising a first sector and a second sector, each of the first sector and the sector comprising a respective plurality of memory cells arranged in rows and columns, a respective plurality of word lines, and a respective plurality of local bit lines; a plurality of main bit lines selectively coupled to local bit lines; a first sense amplifier and a second sense amplifier; and a routing circuit arranged between the plurality of main bit lines and the first sense amplifier and the second sense amplifier, wherein the routing circuit comprises: a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier; a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier; a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier; a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier; a lower coupling circuit coupling a second lower main bit line to a second input of the first sense amplifier; and an upper coupling circuit coupling a second upper main bit line to a second input of the second sense amplifier; and a control logic circuit configured to control the first lower switch, the second lower switch, the first upper switch, and the second upper switch so as to control coupling among the first sense amplifier, the second sense amplifier, the first lower main bit line, the second lower main bit lines, the first upper main bit line, and the second upper main bit line.
Memory devices often require efficient data sensing and routing to improve performance and reduce power consumption. A memory device includes a memory array divided into at least two sectors, each containing multiple memory cells organized in rows and columns, along with word lines and local bit lines. The device also includes multiple main bit lines that selectively connect to the local bit lines. Two sense amplifiers are used to read data from the memory cells. A routing circuit is positioned between the main bit lines and the sense amplifiers, enabling flexible data routing. The routing circuit includes lower and upper switches that connect the main bit lines to the sense amplifiers. Specifically, the first lower switch connects a first lower main bit line to the first sense amplifier, while the second lower switch connects the same main bit line to the second sense amplifier. Similarly, the first upper switch connects a first upper main bit line to the first sense amplifier, and the second upper switch connects it to the second sense amplifier. Additionally, a lower coupling circuit connects a second lower main bit line to the second input of the first sense amplifier, and an upper coupling circuit connects a second upper main bit line to the second input of the second sense amplifier. Control logic manages the switches to dynamically route data between the main bit lines and the sense amplifiers, optimizing data access and reducing interference. This design enhances memory performance by improving data sensing efficiency and minimizing power consumption.
5. The memory device according to claim 4 , wherein the control logic circuit is configured to operate in a first operating mode, wherein: the second lower switch and the first upper switch are open; and the first lower switch and the second upper switch are closed, wherein, in the first operating mode, the first lower main bit line and the first upper main bit line are coupled to the first input of the first sense amplifier and to the first input of the second sense amplifier, respectively.
This invention relates to memory devices, specifically addressing the challenge of efficiently managing data transfer and sensing operations in memory arrays. The device includes a memory array with multiple bit lines, sense amplifiers, and a control logic circuit that regulates the operation of switches to control data flow between the bit lines and the sense amplifiers. The memory device features a first lower main bit line and a first upper main bit line, each connected to a first input of a first sense amplifier and a second sense amplifier, respectively. The control logic circuit operates in a first mode where a second lower switch and a first upper switch are open, while a first lower switch and a second upper switch are closed. In this configuration, the first lower main bit line is coupled to the first input of the first sense amplifier, and the first upper main bit line is coupled to the first input of the second sense amplifier. This setup enables efficient data sensing and transfer by selectively connecting the bit lines to the sense amplifiers, optimizing memory access operations. The control logic ensures proper switching to maintain data integrity and improve performance in memory read and write operations.
6. The memory device according to claim 5 , wherein the control logic circuit is configured to operate in a second operating mode, wherein: the first lower switch and the second upper switch are open; and the second lower switch and the first upper switch are closed, wherein, in the second operating mode, the first lower main bit line and the first upper main bit line are coupled to the first input of the second sense amplifier and to the first input of the first sense amplifier, respectively.
This invention relates to memory devices, specifically to a memory device with improved sensing circuitry for reading data from memory cells. The problem addressed is efficient and accurate data sensing in memory arrays, particularly in configurations where multiple bit lines are involved. The memory device includes a first and second sense amplifier, each with first and second inputs. A first lower main bit line and a first upper main bit line are connected to the memory cells. The device also includes a first lower switch, a second lower switch, a first upper switch, and a second upper switch, which control the connections between the bit lines and the sense amplifiers. In a second operating mode, the first lower switch and the second upper switch are open, while the second lower switch and the first upper switch are closed. This configuration couples the first lower main bit line to the first input of the second sense amplifier and the first upper main bit line to the first input of the first sense amplifier. This arrangement allows for differential sensing between the bit lines, improving read accuracy and reducing interference between adjacent memory cells. The switching logic enables flexible routing of signals to optimize sensing operations based on the memory device's operational requirements.
7. The memory device according to claim 6 , further comprising: a first lower memory cell and a second lower memory cell respectively coupled to a first word line of the first sector and to a first local bit line and a second local bit line of the first sector; a first upper memory cell and a second upper memory cell respectively coupled to a second word line of the second sector and to a first local bit line and a second local bit line of the second sector; a row-decoder circuit controllable for selecting the word lines of the first sector and the second sector; and a column-decoder circuit controllable for selecting the local bit lines of the first sector and the second sector and for coupling the local bit lines selected to corresponding main bit lines.
This invention relates to a memory device architecture designed to improve data storage efficiency and access speed in multi-sector memory arrays. The device addresses the challenge of efficiently managing memory cells across multiple sectors while minimizing signal interference and optimizing data retrieval. The memory device includes at least two sectors, each containing multiple memory cells organized in rows and columns. Each sector has its own set of word lines and local bit lines. Specifically, a first sector contains a first lower memory cell and a second lower memory cell, each connected to a first word line of the first sector and to a first and second local bit line of the first sector. Similarly, a second sector contains a first upper memory cell and a second upper memory cell, each connected to a second word line of the second sector and to a first and second local bit line of the second sector. The device further includes a row-decoder circuit that selectively activates the word lines in both sectors, enabling access to specific rows of memory cells. A column-decoder circuit is also provided to select the local bit lines in each sector and to connect the selected local bit lines to corresponding main bit lines, facilitating data transfer between the memory cells and external circuitry. This architecture allows for independent and simultaneous access to memory cells in different sectors, enhancing overall memory performance and reducing latency.
8. The memory device according to claim 7 , wherein the first lower memory cells and the second lower memory cells are arranged symmetrically with respect to the first upper memory cells and the second upper memory cells, respectively, and wherein the first sector and the second sector are identical.
This invention relates to memory devices, specifically to the arrangement of memory cells within a memory array. The problem addressed is optimizing the layout of memory cells to improve performance, reliability, and manufacturing efficiency. The invention describes a memory device with a plurality of memory cells organized into sectors, where each sector contains upper and lower memory cells. The first and second lower memory cells are symmetrically arranged relative to the first and second upper memory cells, respectively. This symmetric arrangement ensures balanced electrical characteristics and reduces manufacturing variability. Additionally, the first and second sectors are identical in structure, which simplifies design and manufacturing processes while ensuring consistent performance across the memory array. The symmetric layout helps minimize signal interference and improves data integrity, particularly in high-density memory configurations. The identical sectors further enable uniform error correction and wear-leveling mechanisms, enhancing the device's longevity. This arrangement is particularly useful in non-volatile memory devices, such as flash memory, where precise cell placement and uniform electrical behavior are critical for reliable operation.
9. The memory device according to claim 7 , wherein, when the control logic circuit operates in the first operating mode, the control logic circuit is configured to control the column-decoder circuit to: couple the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively; and couple the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit lines, respectively; and wherein, when the control logic circuit operates in the first operating mode, the control logic circuit is further configured to control the row-decoder circuit to: select the first word line and the second word line so that the first sense amplifier carries out differential reading of the first lower memory cell and the second lower memory cell, and so that the second sense amplifier carries out differential reading of the first upper memory cell and the second upper memory cell.
This invention relates to a memory device with improved data reading efficiency, particularly in a memory architecture where multiple sectors share main bit lines. The problem addressed is optimizing data access in memory arrays with shared bit lines, which can lead to conflicts or inefficiencies during read operations. The memory device includes a memory array divided into at least two sectors, each sector containing local bit lines and memory cells. A column-decoder circuit and a row-decoder circuit are used to manage data access. In a first operating mode, the control logic circuit coordinates the column-decoder to couple local bit lines from different sectors to main bit lines in a specific configuration. Specifically, the first sector's local bit lines are connected to lower main bit lines, while the second sector's local bit lines are connected to upper main bit lines in a crossed manner. Simultaneously, the row-decoder selects word lines to enable differential reading of memory cells. The first sense amplifier performs differential reading between a first lower memory cell and a second lower memory cell, while the second sense amplifier performs differential reading between a first upper memory cell and a second upper memory cell. This configuration allows for efficient parallel data access and reduces conflicts in shared bit line architectures. The invention enhances read performance by leveraging differential sensing and optimized bit line routing.
10. The memory device according to claim 7 , wherein, when the control logic circuit operates in the second operating mode, the control logic circuit is configured to operate in a first configuration, wherein the control logic circuit controls the column-decoder circuit to: couple the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively; and couple the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit line, respectively; and wherein, when the control logic circuit operates in the first configuration, the control logic circuit is further configured to control the row-decoder circuit to select the first word line and the second word line so that the first sense amplifier carries out differential reading of the second lower memory cell and of the second upper memory cell, and so that the second sense amplifier carries out differential reading of the first lower memory cell and of the first upper memory cell.
This invention relates to memory devices, specifically to a memory device with improved data reading efficiency by utilizing differential reading techniques across multiple memory sectors. The problem addressed is the inefficiency in conventional memory devices where reading operations are performed sequentially, leading to slower access times and higher power consumption. The memory device includes multiple sectors, each with local bit lines and memory cells. A control logic circuit operates in different modes to manage data reading. In a second operating mode, the control logic circuit configures the column-decoder circuit to couple local bit lines from different sectors to main bit lines in a specific arrangement. Specifically, the first sector's local bit lines are connected to lower main bit lines, while the second sector's local bit lines are connected to upper main bit lines in a crossed manner. This configuration allows the row-decoder circuit to select word lines such that sense amplifiers perform differential reading. The first sense amplifier reads data from a lower memory cell in one sector and an upper memory cell in another sector, while the second sense amplifier reads data from a lower memory cell in the second sector and an upper memory cell in the first sector. This differential reading method enhances data accuracy and reduces read latency by comparing signals from paired memory cells simultaneously. The invention improves memory access efficiency by leveraging parallel differential reading across sectors.
11. The memory device according to claim 10 , wherein, when the control logic operates in the second operating mode, it is configured to operate in a second configuration, wherein the control logic circuit controls the row-decoder circuit to select one of the first word line and the second word line, and wherein the control logic circuit controls the column-decoder circuit to: if the first word line has been selected, couple the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively, so that the first lower memory cell and the second lower memory cell are coupled to the first input of the second sense amplifier and to the second input of the first sense amplifier, respectively; and if the second word line has been selected, couple the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit lines, respectively, so that the first upper memory cell and the second upper memory cell are coupled to the second input of the second sense amplifier and to the first input of the first sense amplifier, respectively; the memory device further comprising: a first reference circuit and a second reference circuit, which are configured to generate a reference electrical quantity controllable by the control logic circuit, wherein, when the control logic circuit operates in the second configuration, the control logic circuit is further configured to: if the first word line has been selected, couple the first reference circuit and the second reference circuit to the first input of the first sense amplifier and to the second input of the second sense amplifier, respectively, so that the first sense amplifier and the second sense amplifier carry out readings of a single-ended type of the second lower memory cell and the first lower memory cell, respectively; and if the second word line has been selected, couple the first reference circuit and the second reference circuit to the second input of the first sense amplifier and to the first input of the second sense amplifier, respectively, so that the first sense amplifier and the second sense amplifier carry out readings of a single-ended type of the second upper memory cell and the first upper memory cell, respectively.
A memory device includes a memory array with multiple sectors, each sector having memory cells connected to local bit lines. The device operates in different modes, including a second operating mode where a control logic circuit configures the memory device to perform single-ended read operations. In this mode, the control logic selects either a first or second word line and controls a row-decoder circuit to activate the selected word line. A column-decoder circuit then couples local bit lines from either the first or second sector to main bit lines, depending on which word line is selected. If the first word line is selected, the first and second local bit lines of the first sector are coupled to the first and second lower main bit lines, respectively, connecting the first and second lower memory cells to the second input of the first sense amplifier and the first input of the second sense amplifier. If the second word line is selected, the first and second local bit lines of the second sector are coupled to the second and first upper main bit lines, respectively, connecting the first and second upper memory cells to the first input of the first sense amplifier and the second input of the second sense amplifier. The device also includes first and second reference circuits that generate a reference electrical quantity controlled by the control logic. In the second configuration, the control logic couples the reference circuits to the sense amplifiers based on the selected word line. For the first word line, the first and second reference circuits are coupled to the first input of the first sense amplifier and the second input of the second sense amplifier, enabling single-ended reads of the second lower and first lower memory cells. For the second word line, the referen
12. The memory device according to claim 11 , wherein, when the control logic circuit operates in the second configuration, the control logic circuit is further configured to: if the first word line has been selected, control the row-decoder circuit so as to deselect the second word line and control the column-decoder circuit so as to couple the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit line, respectively; and if the second word line has been selected, control the row-decoder circuit so as to deselect the first word line and control the column-decoder circuit so as to couple the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively.
The invention relates to a memory device with improved control logic for managing bit line connections in a multi-sector memory array. The problem addressed is efficient routing and selection of bit lines in memory devices with multiple sectors to optimize data access and reduce interference. The memory device includes a memory array divided into at least two sectors, each with local bit lines and word lines. A control logic circuit operates in different configurations to manage row and column decoders. In a second configuration, the control logic dynamically adjusts bit line connections based on which word line is selected. If a first word line is selected, the control logic deselects a second word line and couples the local bit lines of a second sector to upper main bit lines in a specific arrangement. Conversely, if the second word line is selected, the control logic deselects the first word line and couples the local bit lines of a first sector to lower main bit lines. This selective coupling ensures proper data routing while minimizing conflicts and improving access efficiency. The row and column decoders are controlled to ensure only the relevant word lines and bit lines are active, reducing power consumption and improving performance. The invention enhances memory access flexibility and reliability in multi-sector memory architectures.
13. The memory device according to claim 1 , wherein the lower coupling circuit comprises: an additional lower switch, which is closed and arranged between the second lower main bit line and the second input of the first sense amplifier; and a lower balancing switch, which is connected in parallel to the additional lower switch and is open, and wherein the upper coupling circuit comprises: an additional upper switch, which is closed and is arranged between the second upper main bit line and the second input of the second sense amplifier; and an upper balancing switch, which is connected in parallel to the additional lower switch and is open.
A memory device includes a memory array with multiple bit lines and sense amplifiers for reading and writing data. The device addresses challenges in efficiently coupling and balancing bit lines during memory operations to improve performance and reliability. The memory device features lower and upper coupling circuits that connect main bit lines to sense amplifiers. The lower coupling circuit includes an additional lower switch, which is closed and connects a second lower main bit line to a second input of a first sense amplifier. A lower balancing switch is connected in parallel to the additional lower switch but remains open. Similarly, the upper coupling circuit includes an additional upper switch, which is closed and connects a second upper main bit line to a second input of a second sense amplifier. An upper balancing switch is connected in parallel to the additional upper switch but remains open. These configurations ensure selective coupling of bit lines to sense amplifiers while maintaining isolation when needed, optimizing data transfer and reducing interference during memory operations. The switches are controlled to manage signal paths, enhancing accuracy and speed in read and write operations. The design improves memory device efficiency by dynamically adjusting connections between bit lines and sense amplifiers.
14. The memory device according to claim 1 , wherein each memory cell comprises a respective storage element and a respective access element, which are electrically coupled, and wherein the storage element comprises a phase-change material.
This invention relates to memory devices, specifically those using phase-change memory (PCM) technology. The problem addressed is improving the efficiency and reliability of memory cells in PCM-based storage systems. Traditional memory cells often suffer from high power consumption, slow switching speeds, or limited endurance due to material degradation. The invention describes a memory device with memory cells that each include a storage element and an access element, electrically coupled together. The storage element is made of a phase-change material, which can switch between amorphous and crystalline states to represent binary data. The access element controls the electrical connection to the storage element, enabling read and write operations. The phase-change material allows for non-volatile storage, meaning data is retained even when power is removed. The electrical coupling between the storage and access elements ensures efficient data access while minimizing power loss. This design improves energy efficiency, speed, and durability compared to conventional memory technologies. The invention is particularly useful in high-density storage applications where low power consumption and fast switching are critical.
15. The memory device according to claim 14 , wherein the access element is formed by a MOSFET.
A memory device includes a memory cell with a storage element and an access element. The storage element stores data, while the access element controls access to the storage element during read and write operations. The access element is implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET), which selectively connects or disconnects the storage element from a bitline or wordline based on a control signal. The MOSFET-based access element enables precise and efficient data access, reducing power consumption and improving reliability. The memory device may be part of a larger memory array, where multiple memory cells are arranged in rows and columns, each controlled by separate wordlines and bitlines. The MOSFET access element ensures fast switching and minimal leakage current, enhancing overall memory performance. This design is particularly useful in high-density memory applications, such as DRAM or flash memory, where reliable and low-power access to stored data is critical. The MOSFET implementation allows for scalable fabrication, making it suitable for advanced semiconductor manufacturing processes.
16. An electronic apparatus comprising: a memory device according to claim 1 ; a controller; and a bus configured to electrically couple the controller and the memory device.
This invention relates to an electronic apparatus that integrates a memory device with a controller and a bus system. The memory device includes a memory array with memory cells, each having a storage element and a selection element. The storage element stores data, while the selection element controls access to the storage element. The memory device also features a peripheral circuit that manages operations like reading, writing, and erasing data. The controller in the apparatus is responsible for executing commands to manipulate data in the memory device. The bus system provides electrical connections between the controller and the memory device, enabling data transfer and command execution. The apparatus is designed to improve data storage efficiency and reliability by optimizing the interaction between the memory device, controller, and bus. The memory device's architecture ensures fast and accurate data access, while the controller's command execution enhances overall system performance. The bus system's design minimizes signal interference and ensures stable communication between components. This invention addresses challenges in electronic data storage, such as speed, reliability, and power consumption, by integrating these components into a cohesive system.
17. A method for reading a memory of a memory device, the memory comprising a first sector and a second sector, each of the first sector and the second sector comprising a respective plurality of memory cells arranged in rows and columns, a respective plurality of word lines, and a respective plurality of local bit lines, the memory device further comprising: a plurality of main bit lines selectively coupled to local bit lines; a first sense amplifier and a second sense amplifier; and a routing circuit arranged between the main bit lines and the first sense amplifier and the second sense amplifier, wherein the routing circuit comprises: a first lower switch arranged between a first lower main bit line and a first input of the first sense amplifier; a second lower switch arranged between the first lower main bit line and a first input of the second sense amplifier; a first upper switch arranged between a first upper main bit line and the first input of the first sense amplifier; a second upper switch arranged between the first upper main bit line and the first input of the second sense amplifier; a lower coupling circuit configured to couple a second lower main bit line to a second input of the first sense amplifier; and an upper coupling circuit configured to couple a second upper main bit line to a second input of the second sense amplifier, wherein the reading method comprises the step of controlling the first lower switch and the second lower switch and the first upper switch and the second upper switch so as to control couplings among the first sense amplifier, the second sense amplifier, the first lower main bit line, the second lower main bit line, the first upper main bit line, and the second upper main bit line.
The invention relates to memory devices, specifically methods for reading data from memory sectors with improved efficiency and flexibility. The problem addressed is the need for efficient data reading in memory devices with multiple sectors, where each sector contains memory cells arranged in rows and columns, word lines, and local bit lines. The memory device includes main bit lines selectively coupled to local bit lines, two sense amplifiers, and a routing circuit between the main bit lines and the sense amplifiers. The routing circuit comprises lower and upper switches that connect main bit lines to sense amplifier inputs, along with coupling circuits that link additional main bit lines to the sense amplifiers. The method involves controlling these switches to manage connections between the sense amplifiers and the main bit lines, enabling flexible and efficient data reading from different memory sectors. By dynamically configuring the routing circuit, the method allows for optimized data access, reducing latency and improving performance in memory operations. The invention is particularly useful in memory architectures requiring high-speed and adaptable read operations.
18. The reading method according to claim 17 , comprising carrying out a first set of operations, the first set of operations comprising: opening the second lower switch and the first upper switch; and closing the first lower switch and the second upper switch, wherein, as a result of the first set of operations, the first lower main bit line and the first upper main bit line are coupled to the first input of the first sense amplifier and to the first input of the second sense amplifier, respectively.
This invention relates to a method for reading data in a memory device, specifically addressing the challenge of efficiently coupling bit lines to sense amplifiers during read operations. The method involves a sequence of switch operations to selectively connect main bit lines to sense amplifier inputs. The process begins by opening a second lower switch and a first upper switch, while simultaneously closing a first lower switch and a second upper switch. This configuration couples a first lower main bit line to the first input of a first sense amplifier and a first upper main bit line to the first input of a second sense amplifier. The method ensures proper signal routing for accurate data sensing, improving read performance in memory systems. The invention is part of a broader system that includes multiple switches and sense amplifiers, where the described operations are part of a coordinated sequence to manage bit line connections during read cycles. The technique optimizes signal integrity and reduces interference, enhancing reliability in memory read operations.
19. The reading method according to claim 18 , comprising carrying out a second set of operations, the second set of operations comprising: opening the first lower switch and the second upper switch; and closing the second lower switch and the first upper switch, wherein, as a result of the second set of operations, the first lower main bit line and the first upper main bit line are coupled to the first input of the second sense amplifier and to the first input of the first sense amplifier, respectively.
This invention relates to a method for reading data in a memory system, specifically addressing the challenge of efficiently coupling bit lines to sense amplifiers during read operations. The method involves a sequence of switch operations to selectively connect main bit lines to sense amplifiers, enabling accurate data sensing. The process begins by opening a first lower switch and a second upper switch while closing a second lower switch and a first upper switch. This configuration couples a first lower main bit line to the first input of a second sense amplifier and a first upper main bit line to the first input of a first sense amplifier. The method ensures proper signal routing between memory cells and sense amplifiers, facilitating reliable data readout. The invention is particularly useful in memory architectures where multiple bit lines and sense amplifiers must be dynamically connected to optimize read performance and reduce interference. The switch operations are carefully coordinated to maintain signal integrity and minimize power consumption during the read process. This approach improves the efficiency and accuracy of data retrieval in memory systems, addressing limitations in conventional read methods that may suffer from signal degradation or excessive power usage.
20. The reading method according to claim 19 , wherein the memory device further comprises: a first memory cell and a second lower memory cell coupled to a first word line of the first sector and to a first local bit line and a second local bit line of the first sector, respectively; a first upper memory cell and a second upper memory cell coupled to a second word line of the second sector and to a first local bit line and a second local bit line of the second sector, respectively; a row-decoder circuit; and a column-decoder circuit, wherein the reading method further comprises: controlling the row-decoder circuit for selecting word lines of the first sector and the second sector; controlling the column-decoder circuit for selecting local bit lines of the first sector and the second sector; and coupling the local bit lines selected to corresponding main bit lines.
This invention relates to a memory device architecture and a method for reading data from a memory device with multiple sectors. The problem addressed is efficient data access in memory systems with multiple sectors, particularly in managing word lines and bit lines across different sectors. The memory device includes a first sector with a first memory cell and a second lower memory cell, both coupled to a first word line of the first sector and to a first and second local bit line of the first sector, respectively. A second sector includes a first upper memory cell and a second upper memory cell, both coupled to a second word line of the second sector and to a first and second local bit line of the second sector, respectively. The device also includes a row-decoder circuit and a column-decoder circuit. The reading method involves controlling the row-decoder circuit to select word lines in both sectors and controlling the column-decoder circuit to select local bit lines in both sectors. The selected local bit lines are then coupled to corresponding main bit lines, enabling data readout. This approach optimizes data access by coordinating row and column decoding across multiple sectors, improving efficiency in memory operations.
21. The reading method according to claim 20 , wherein the first set of operations further comprises: controlling the column-decoder circuit to couple the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively; and controlling the column-decoder circuit to couple the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit line, respectively; and controlling the row-decoder circuit to select the first word line and the second word line, and carrying out, by the first sense amplifier, differential reading of the first lower memory cell and the second lower memory cell and carrying out, by the second sense amplifier, differential reading of the first upper memory cell and the second upper memory cell.
This invention relates to a memory reading method for a semiconductor memory device, specifically addressing efficient data retrieval in a memory array with multiple sectors and differential sensing. The problem solved involves optimizing read operations in memory architectures where multiple sectors share main bit lines, requiring careful control of bit line coupling to avoid interference and ensure accurate data sensing. The method involves a memory array divided into at least two sectors, each with local bit lines and memory cells connected to word lines. The sectors are coupled to upper and lower main bit lines via a column-decoder circuit. The reading process begins by controlling the column-decoder to couple the first sector's local bit lines to the lower main bit lines and the second sector's local bit lines to the upper main bit lines in a cross-coupled manner. A row-decoder circuit then selects the word lines associated with the target memory cells. Differential sensing is performed simultaneously by two sense amplifiers: the first sense amplifier reads a pair of lower memory cells from the first sector, while the second sense amplifier reads a pair of upper memory cells from the second sector. This approach enables parallel differential reading, improving read efficiency and reducing access time in multi-sector memory arrays. The method ensures accurate data retrieval by isolating sectors during sensing and leveraging differential sensing to enhance noise immunity.
22. The reading method according to claim 21 , wherein the second set of operations further comprises carrying out a first subset of operations, the first subset of operations comprising: controlling the column-decoder circuit to couple the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively; and controlling the column-decoder circuit to couple the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit line, respectively; and controlling the row-decoder circuit to select the first word line and the second word line, and carrying out, by the first sense amplifier, differential reading of the second lower memory cell and of the second upper memory cell, and carrying out, by the second sense amplifier, differential reading of the first lower memory cell and of the first upper memory cell.
This invention relates to a method for reading data from a memory device, specifically addressing challenges in efficiently accessing memory cells in a memory array with multiple sectors. The method involves a memory architecture where memory cells are organized into sectors, each sector having local bit lines connected to main bit lines through a column-decoder circuit. The problem being solved is the efficient and accurate reading of memory cells across different sectors, particularly when differential reading is required to compare data from multiple cells. The method includes a second set of operations that further comprises a first subset of operations. In this subset, the column-decoder circuit is controlled to couple the first and second local bit lines of a first sector to the first and second lower main bit lines, respectively. Simultaneously, the first and second local bit lines of a second sector are coupled to the second and first upper main bit lines, respectively. The row-decoder circuit then selects the first and second word lines, enabling access to the relevant memory cells. A first sense amplifier performs differential reading of a second lower memory cell and a second upper memory cell, while a second sense amplifier performs differential reading of a first lower memory cell and a first upper memory cell. This approach ensures efficient and accurate data retrieval by leveraging differential sensing to improve reliability and speed in memory access operations.
23. The reading method according to claim 20 , wherein the second set of operations further comprises carrying out a second subset of operations, the second subset of operations comprising: controlling the row-decoder circuit to select one of the first word line and the second word line; and if the first word line has been selected, controlling the column-decoder circuit to couple the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively, wherein, as a result of the second subset of operations, the first lower memory cell and the second lower memory cell are coupled, respectively, to the first input of the second sense amplifier and to the second input of the first sense amplifier; if the second word line has been selected, controlling the column-decoder circuit to couple the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit line, respectively, wherein, as a result of the second subset of operations, the first upper memory cell and the second upper memory cell are coupled to the second input of the second sense amplifier and to the first input of the first sense amplifier, respectively; if the first word line has been selected, coupling a first reference circuit and a second reference circuit to the first input of the first sense amplifier and to the second input of the second sense amplifier, respectively, the first reference circuit and the second reference circuit being configured to generate a reference electrical quantity, and carrying out readings of a single-ended type of the second lower memory cell and the first lower memory cells respectively, by the first sense amplifier and the second sense amplifier; and if the second word line has been selected, coupling the first reference circuit and the second reference circuit to the second input of the first sense amplifier and to the first input of the second sense amplifier, respectively, and carrying out readings of a single-ended type of the second upper memory cell and the first upper memory cell by the first sense amplifier and the second sense amplifier, respectively.
This invention relates to a memory reading method for a non-volatile memory device, specifically addressing efficient data retrieval in a memory array with multiple sectors and sense amplifiers. The method involves selecting between two word lines (first or second) to access memory cells in either a first or second sector. When the first word line is selected, local bit lines in the first sector are coupled to lower main bit lines, connecting lower memory cells to sense amplifier inputs. Conversely, selecting the second word line couples local bit lines in the second sector to upper main bit lines, connecting upper memory cells to sense amplifier inputs. Reference circuits generate reference electrical quantities for single-ended read operations. For the first word line selection, the reference circuits connect to specific sense amplifier inputs to enable reading of lower memory cells. For the second word line selection, the reference circuits connect to different sense amplifier inputs to enable reading of upper memory cells. This approach optimizes memory access by dynamically routing signals based on word line selection, ensuring efficient single-ended reads from either sector. The method enhances data retrieval speed and accuracy in memory devices with shared sense amplifiers.
24. The reading method according to claim 23 , wherein the second subset of operations further comprises: if the first word line has been selected, deselecting the second word line and coupling the first local bit line and the second local bit line of the second sector to the second upper main bit line and the first upper main bit line, respectively; and if the second word line has been selected, deselecting the first word line and coupling the first local bit line and the second local bit line of the first sector to the first lower main bit line and the second lower main bit line, respectively.
This invention relates to a method for reading data from a memory device, specifically addressing the challenge of efficiently managing bit line connections in a memory array with multiple sectors. The method involves selecting a word line in a first sector and a word line in a second sector, where each sector has local bit lines connected to upper and lower main bit lines. The method further includes a second subset of operations that dynamically adjusts these connections based on which word line is selected. If the first word line is selected, the second word line is deselected, and the local bit lines of the second sector are coupled to the second upper main bit line and the first upper main bit line, respectively. Conversely, if the second word line is selected, the first word line is deselected, and the local bit lines of the first sector are coupled to the first lower main bit line and the second lower main bit line, respectively. This approach optimizes data read operations by ensuring proper bit line routing and minimizing interference between sectors during read cycles. The method improves memory access efficiency and reliability by dynamically reconfiguring bit line connections based on the selected word lines.
25. The reading method according to claim 17 , wherein the lower coupling circuit comprises: an additional lower switch arranged between the second lower main bit line and the second input of the first sense amplifier; and a lower balancing switch connected in parallel to the additional lower switch, and wherein the upper coupling circuit comprises: an additional upper switch arranged between the second upper main bit line and the second input of the second sense amplifier; and an upper balancing switch connected in parallel to the additional lower switch, wherein the reading method further comprises the steps of: keeping the additional lower switch and the additional upper switch closed; and keeping the lower balancing switch and the upper balancing switch open.
This invention relates to a method for reading data from a memory device, specifically addressing challenges in balancing and coupling signals in memory arrays. The method involves a memory architecture with multiple bit lines and sense amplifiers to detect stored data. The key innovation lies in the configuration of coupling circuits that connect main bit lines to sense amplifier inputs, ensuring accurate data reading by maintaining proper signal balance. The lower coupling circuit includes an additional lower switch positioned between a second lower main bit line and the second input of a first sense amplifier, along with a lower balancing switch connected in parallel to this additional switch. Similarly, the upper coupling circuit features an additional upper switch between a second upper main bit line and the second input of a second sense amplifier, with an upper balancing switch in parallel. During the reading process, the additional lower and upper switches remain closed to establish a direct connection, while the lower and upper balancing switches stay open to prevent unintended signal interference. This configuration ensures that the sense amplifiers receive stable and balanced signals, improving read accuracy and reliability in memory operations. The method is particularly useful in memory systems requiring precise signal management, such as those using differential sensing techniques.
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March 24, 2020
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