Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A computer program product for executing an instruction in a central processing unit, the computer program product comprising: a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for performing a method comprising: obtaining an instruction for execution, the instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation; a first register field to be used to designate a first register, the first register comprising a first operand; a second register field to be used to designate a second register, the second register comprising a second operand; and executing the instruction, the executing comprising: adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations; based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and placing the first result in the selected element of the first operand.
This invention relates to a computer program product for executing a Vector Checksum operation in a central processing unit (CPU). The problem addressed is the need for efficient computation of checksums, particularly in vector processing, where traditional methods may not fully leverage parallelism or may require multiple instructions to complete the task. The computer program product includes a non-transitory storage medium storing instructions for a method. The method involves obtaining an instruction for execution, where the instruction includes an opcode field identifying the Vector Checksum operation, a first register field designating a first register containing a first operand, and a second register field designating a second register containing a second operand. Upon execution, the instruction performs the following steps: adding together multiple elements of the second operand to obtain a first result, where the addition includes one or more end-around carry add operations. If an end-around carry add operation produces a sum with a carry out at a chosen position, this carry is added to a selected position in a selected element of the first operand. The final result is then placed in the selected element of the first operand. This approach optimizes checksum computation by combining multiple operations into a single instruction, reducing the number of cycles required and improving efficiency in vector processing environments. The use of end-around carry operations ensures accurate accumulation of values, particularly for large datasets or high-precision calculations.
2. The computer program product of claim 1 , wherein the chosen position is bit position zero, the selected position is bit position 31 , and the selected element of the first operand is element one of the first operand.
This invention relates to a computer program product for performing bit manipulation operations in a processor. The technology addresses the challenge of efficiently extracting and processing specific bits from operands in a computing system, particularly in scenarios where precise bit positioning is required for operations like bit rotation, shifting, or masking. The invention involves a method where a first operand is processed to extract a selected element, which is then used to determine a chosen position within a second operand. The extracted element from the first operand is specifically element one, and the selected position in the second operand is bit position 31. The chosen position in the second operand is bit position zero. The program product includes instructions for executing these operations, ensuring that the selected element from the first operand influences the manipulation of the second operand at the specified bit positions. This approach optimizes bit-level operations by leveraging predefined bit positions and operand elements, reducing computational overhead and improving processing efficiency. The method is particularly useful in applications requiring precise bit manipulation, such as cryptographic algorithms, data compression, or low-level system programming. The invention ensures accurate and efficient bit handling while maintaining compatibility with standard processor architectures.
3. The computer program product of claim 1 , wherein the executing further comprises placing zeros in one or more other elements of the first operand.
This invention relates to computer program products for performing arithmetic operations, specifically focusing on optimizing the handling of operands in computational tasks. The problem addressed involves efficiently managing data elements within operands to improve processing speed and resource utilization. The invention describes a method where, during the execution of an arithmetic operation involving a first operand, certain elements of this operand are set to zero. This step is part of a broader process that includes receiving a first operand and a second operand, each containing multiple elements, and executing an arithmetic operation between these operands. The operation may involve addition, subtraction, multiplication, or other arithmetic functions. By selectively zeroing out specific elements of the first operand, the system can streamline calculations, reduce unnecessary computations, and enhance overall performance. This technique is particularly useful in high-performance computing environments where minimizing computational overhead is critical. The invention may be applied in various fields, including scientific computing, financial modeling, and data processing, where efficient arithmetic operations are essential for achieving optimal results. The method ensures that only relevant elements are processed, thereby conserving computational resources and improving execution efficiency.
4. The computer program product of claim 1 , wherein the first operand comprises four elements, and wherein the method further comprises placing zeros in elements zero, two and three of the first operand.
This invention relates to a computer program product for processing operands in a computing system, specifically addressing the efficient handling of multi-element operands in arithmetic or logical operations. The problem being solved involves optimizing the storage and manipulation of operands with specific element configurations, particularly when certain elements need to be zeroed out to simplify computations or reduce memory usage. The invention describes a method where a first operand, comprising four elements, is processed by selectively placing zeros in elements zero, two, and three of the operand. This ensures that only the remaining element (element one) retains a non-zero value, which can streamline subsequent operations by reducing the number of active elements that need to be processed. The method may be part of a larger system for executing arithmetic or logical instructions, where operand manipulation is critical for performance or resource efficiency. The technique is particularly useful in scenarios where certain elements of an operand are irrelevant or need to be ignored, such as in vector processing, cryptographic operations, or data compression. By zeroing out specific elements, the system can avoid unnecessary computations, reduce power consumption, or simplify hardware implementation. The invention may also be applied in contexts where operands are dynamically modified during execution to meet specific computational requirements.
5. The computer program product of claim 4 , wherein the four elements of the first operand are word-sized elements.
A system and method for processing data in a computing environment involves manipulating operands composed of multiple elements, particularly focusing on word-sized elements. The technology addresses the challenge of efficiently handling operands with fixed-size components, such as those used in vector processing or parallel computation, where alignment and size constraints must be managed to optimize performance. The invention specifies that a first operand, which is part of a computational operation, consists of four word-sized elements. These elements are typically aligned to a specific boundary, such as a 32-bit or 64-bit word, to ensure compatibility with standard processor architectures. The system may perform operations like arithmetic, logical, or bitwise manipulations on these elements, leveraging their fixed size to enhance processing speed and reduce overhead. The method ensures that the elements are correctly formatted and aligned before processing, which is critical for avoiding errors and maintaining efficiency in high-performance computing tasks. This approach is particularly useful in applications requiring parallel data processing, such as scientific simulations, machine learning, or real-time data analysis, where the ability to handle multiple word-sized elements simultaneously is essential for achieving optimal performance.
6. The computer program product of claim 1 , wherein the plurality of elements of the second operand comprises a plurality of word-sized elements.
This invention relates to computer program products for processing data, specifically optimizing operations involving operands with word-sized elements. The problem addressed is the inefficiency in handling operands composed of multiple word-sized elements, which can lead to performance bottlenecks in data processing tasks. The invention improves upon prior art by structuring the second operand to include a plurality of word-sized elements, allowing for more efficient parallel processing and reduced computational overhead. This approach enhances the speed and efficiency of operations such as arithmetic, logical, or bitwise manipulations, particularly in systems where data is organized into fixed-size words. The invention may be applied in various computing environments, including general-purpose processors, specialized hardware accelerators, or embedded systems, where optimizing operand handling is critical for performance. By leveraging word-sized elements, the invention enables better utilization of hardware resources and reduces the complexity of data manipulation tasks. The solution is particularly beneficial in applications requiring high-throughput data processing, such as scientific computing, encryption, or real-time signal processing. The invention ensures compatibility with existing architectures while providing a scalable and efficient method for handling operands with word-sized elements.
7. The computer program product of claim 1 , wherein the instruction further comprises a third register field to be used to designate a third register, the third register comprising a third operand, and wherein the executing further comprises adding the first result to a selected element of the third operand to obtain a second result, the adding the first result using an end around carry add operation.
This invention relates to computer arithmetic operations, specifically improving efficiency in vector processing by enhancing instruction sets to support end-around carry addition. The problem addressed is the computational overhead and complexity in performing modular arithmetic, particularly in cryptographic and signal processing applications where end-around carry operations are frequently required. Traditional methods often involve multiple steps or additional hardware, leading to inefficiencies. The invention describes a computer program product that includes instructions for executing a vectorized arithmetic operation. The instruction includes a first register field designating a first register containing a first operand, a second register field designating a second register containing a second operand, and a third register field designating a third register containing a third operand. The execution involves performing a first arithmetic operation (e.g., multiplication) between the first and second operands to produce a first result. This result is then added to a selected element of the third operand using an end-around carry add operation, producing a second result. The end-around carry add operation ensures that any carry beyond the operand size wraps around, which is critical for modular arithmetic. This approach reduces the need for separate modular reduction steps, improving performance and simplifying instruction execution. The invention optimizes vector processing by integrating these operations into a single instruction, reducing latency and hardware complexity.
8. The computer program product of claim 7 , wherein the instruction further comprises an extension field to be used in designating one or more registers, and wherein the first register field is combined with a first portion of the extension field to designate the first register, the second register field is combined with a second portion of the extension field to designate the second register, and the third register field is combined with a third portion of the extension field to designate the third register.
This invention relates to computer instruction encoding, specifically for instructions that operate on multiple registers. The problem addressed is the efficient designation of registers in processor instructions, particularly when a single instruction involves three or more registers. Traditional encoding methods may require additional bits or complex addressing schemes, leading to inefficiencies in instruction size and processing. The invention provides a computer program product with an instruction that includes an extension field to designate registers. The instruction contains a first register field, a second register field, and a third register field, each combined with a portion of the extension field to specify the respective registers. The extension field is divided into segments, where each segment is paired with a register field to form a complete register identifier. This approach allows for flexible and compact register addressing, reducing the need for additional bits or separate addressing modes. The method ensures that the instruction can efficiently specify three registers while maintaining a balanced distribution of bits across the fields, optimizing instruction encoding and execution. This technique is particularly useful in processors where register access patterns are complex or where instruction size must be minimized.
9. The computer program product of claim 1 , wherein the executing further comprises adding the first result to a selected element of a third operand to obtain a second result, the adding the first result using an end around carry add operation, and wherein the placing comprises placing the second result in the selected element of the first operand.
This invention relates to computer arithmetic operations, specifically improving efficiency in processing data using end-around carry addition. The problem addressed is the need for faster and more efficient arithmetic operations in computing systems, particularly when handling large data sets or complex calculations. The invention involves a computer program product that performs an end-around carry add operation. This operation adds a first result to a selected element of a third operand to produce a second result. The end-around carry add operation ensures that any carry generated during the addition wraps around to the least significant bit of the result, which is useful in certain cryptographic and modular arithmetic applications. The second result is then placed in the selected element of the first operand, effectively updating the first operand with the new value. The invention optimizes arithmetic operations by leveraging end-around carry addition, which reduces the need for additional steps or intermediate storage, improving computational efficiency. This method is particularly beneficial in systems where modular arithmetic is frequently used, such as in cryptographic algorithms or digital signal processing. The approach minimizes latency and resource usage while maintaining accuracy in calculations.
10. The computer program product of claim 9 , wherein the third operand is included in the instruction.
A system and method for optimizing instruction execution in a processor involves dynamically determining operand values during instruction processing. The technology addresses inefficiencies in traditional instruction execution where operands are fetched before execution, leading to unnecessary memory access and processing delays. The invention introduces a mechanism where a third operand, which may be a constant or a dynamically computed value, is included directly within the instruction itself. This eliminates the need for separate operand fetching, reducing latency and improving performance. The system evaluates the instruction to determine whether the third operand is required and processes it accordingly, allowing for more efficient execution paths. The method also includes validating the operand's availability and ensuring compatibility with the instruction's execution requirements. By embedding the operand within the instruction, the system minimizes memory access overhead and accelerates processing, particularly in scenarios where operands are frequently reused or precomputed. This approach enhances processor efficiency and reduces power consumption by avoiding redundant memory operations.
11. A computer system for executing an instruction in a central processing unit, the computer system comprising: a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, said method comprising: obtaining an instruction for execution, the instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation; a first register field to be used to designate a first register, the first register comprising a first operand; a second register field to be used to designate a second register, the second register comprising a second operand; and executing the instruction, the executing comprising: adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations; based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and placing the first result in the selected element of the first operand.
This invention relates to a computer system for performing a Vector Checksum operation in a central processing unit (CPU). The problem addressed is the need for efficient computation of checksums, particularly for vectorized data, where traditional methods may not fully leverage parallel processing capabilities or may require multiple instructions to complete the operation. The computer system includes a memory and a processor that executes a specialized instruction. The instruction contains an opcode identifying the Vector Checksum operation, along with fields designating two registers. The first register holds a first operand, and the second register holds a second operand. The second operand consists of multiple elements that are summed together to produce a result. The summation process involves one or more end-around carry add operations, where the carry from a specific position in the sum is added to a selected position within an element of the first operand. The final result of the summation is then stored in the selected element of the first operand. This approach optimizes checksum computation by reducing the number of required operations and improving efficiency through parallel processing of vector elements. The end-around carry mechanism ensures accurate handling of overflow conditions, making the operation suitable for high-performance computing tasks.
12. The computer system of claim 11 , wherein the first operand comprises four elements, and wherein the method further comprises placing zeros in elements zero, two and three of the first operand.
This invention relates to a computer system configured to process operands in a specific manner, particularly focusing on handling a first operand with four elements. The system addresses the need for efficient data manipulation by selectively zeroing out certain elements of the operand to optimize computational operations. The first operand, which consists of four elements, undergoes a process where elements at positions zero, two, and three are set to zero. This modification ensures that only the remaining element (position one) retains its original value, enabling streamlined processing in subsequent operations. The system may further include additional components or methods to support this zeroing operation, such as memory management units or arithmetic logic units, to facilitate the efficient execution of these steps. By selectively zeroing specific elements, the system improves computational efficiency and reduces unnecessary processing overhead, particularly in applications requiring precise data manipulation. The invention is applicable in fields like digital signal processing, cryptography, or any domain where operand manipulation is critical for performance optimization.
13. The computer system of claim 11 , wherein the plurality of elements of the second operand comprises a plurality of word-sized elements.
This invention relates to computer systems designed to optimize data processing operations, particularly those involving vectorized instructions. The system addresses inefficiencies in handling operands of varying sizes, which can lead to performance bottlenecks in modern computing architectures. The invention focuses on a computer system that processes operands with a plurality of elements, where the second operand includes multiple word-sized elements. These elements are structured to facilitate efficient parallel processing, allowing the system to execute operations more effectively by leveraging the granularity of word-sized data units. The system may also include mechanisms to dynamically adjust operand sizes based on computational requirements, ensuring compatibility with different data types and processing demands. By organizing the second operand into word-sized elements, the system enhances throughput and reduces latency in vectorized operations, making it particularly useful in applications requiring high-performance data manipulation, such as scientific computing, machine learning, and real-time data analysis. The invention improves upon existing systems by providing a more flexible and efficient approach to operand handling, thereby optimizing overall system performance.
14. The computer system of claim 11 , wherein the instruction further comprises a third register field to be used to designate a third register, the third register comprising a third operand, and wherein the executing further comprises adding the first result to a selected element of the third operand to obtain a second result, the adding the first result using an end around carry add operation.
This invention relates to computer systems and processing instructions for performing arithmetic operations with carry handling. The problem addressed is the need for efficient and flexible arithmetic operations in processors, particularly those involving multiple operands and carry propagation. The system includes a processor configured to execute an instruction that processes multiple operands stored in registers. The instruction includes a first register field designating a first register containing a first operand, a second register field designating a second register containing a second operand, and a third register field designating a third register containing a third operand. The processor performs an arithmetic operation, such as an addition, between the first and second operands to produce a first result. This first result is then added to a selected element of the third operand using an end-around carry add operation, producing a second result. The end-around carry add operation ensures that any carry generated during the addition wraps around to the least significant bit, which is useful in certain modular arithmetic applications. The system allows for efficient multi-operand arithmetic operations with controlled carry propagation, improving performance in applications requiring such operations, such as cryptography or modular arithmetic computations. The use of register fields and end-around carry addition provides flexibility and efficiency in handling multiple operands in a single instruction.
15. The computer system of claim 11 , wherein the executing further comprises adding the first result to a selected element of a third operand to obtain a second result, the adding the first result using an end around carry add operation, and wherein the placing comprises placing the second result in the selected element of the first operand.
This invention relates to computer systems that perform arithmetic operations, specifically focusing on efficient handling of carry operations in data processing. The problem addressed is the need for optimized arithmetic computations, particularly when dealing with carry propagation in operations like addition, which can impact performance and power efficiency in computing systems. The system includes a processor configured to execute instructions that involve arithmetic operations. During execution, the processor generates a first result by performing an arithmetic operation on a first operand. This first result is then added to a selected element of a third operand using an end-around carry add operation, producing a second result. The end-around carry add operation ensures that any carry generated during the addition wraps around to the least significant bit, which is useful in certain modular arithmetic or circular buffer applications. The second result is then placed back into the selected element of the first operand, effectively updating the operand with the new value. This approach allows for efficient in-place modification of data elements while maintaining correct carry handling, which is particularly beneficial in applications requiring frequent arithmetic updates, such as cryptographic operations or signal processing. The system ensures that the arithmetic operations are performed with minimal overhead, improving overall computational efficiency.
16. A computer-implemented method of executing an instruction in a central processing unit, the computer-implemented method comprising: obtaining, by a processor, an instruction for execution, the instruction comprising: at least one opcode field to provide an opcode, the opcode identifying a Vector Checksum operation; a first register field to be used to designate a first register, the first register comprising a first operand; a second register field to be used to designate a second register, the second register comprising a second operand; and executing the instruction, the executing comprising: adding together a plurality of elements of the second operand to obtain a first result, wherein the adding comprises performing one or more end around carry add operations; based on performing an end around carry add operation and producing a sum, adding a carry out of a chosen position of the sum, if any, to a selected position in a selected element of the first operand; and placing the first result in the selected element of the first operand.
This invention relates to a computer-implemented method for executing a Vector Checksum operation in a central processing unit (CPU). The method addresses the need for efficient checksum calculations, particularly in vector processing, where traditional summation methods may not account for carry propagation across vector elements, leading to incomplete or incorrect results. The method involves obtaining an instruction for execution, where the instruction includes an opcode identifying the Vector Checksum operation, along with fields designating two registers. The first register contains a first operand, and the second register contains a second operand. Upon execution, the method adds together multiple elements of the second operand to produce a first result. This addition process includes performing one or more end-around carry add operations, where the carry from a specific position of the sum is added to a selected position within a chosen element of the first operand. The final result is then stored in the selected element of the first operand. This approach ensures accurate checksum calculations by properly handling carry propagation, which is critical for applications requiring data integrity, such as error detection in communication protocols or data verification in storage systems. The method optimizes performance by leveraging vector processing capabilities while maintaining correctness in checksum computations.
17. The computer-implemented method of claim 16 , wherein the first operand comprises four elements, and further comprising placing zeros in elements zero, two and three of the first operand.
This invention relates to a computer-implemented method for processing operands in a computational system, specifically addressing the need for efficient data manipulation in numerical computations. The method involves handling a first operand composed of four elements, where elements zero, two, and three are set to zero. This selective zeroing of elements optimizes computational efficiency by reducing unnecessary operations, particularly in scenarios requiring specific data structures or memory alignment. The method may be part of a broader system for performing arithmetic or logical operations, where the first operand interacts with a second operand to produce a result. The zeroing of specific elements ensures that only relevant data is processed, minimizing computational overhead and improving performance in applications such as digital signal processing, cryptography, or parallel computing. The technique is particularly useful in systems where operand alignment or padding is critical for hardware acceleration or software optimization. By strategically zeroing non-relevant elements, the method enhances processing speed and resource utilization while maintaining data integrity.
18. The computer-implemented method of claim 16 , wherein the plurality of elements of the second operand comprises a plurality of word-sized elements.
This invention relates to computer-implemented methods for processing operands in a computing system, specifically addressing the efficient handling of operands with word-sized elements. The method involves performing operations on a first operand and a second operand, where the second operand comprises multiple word-sized elements. Word-sized elements are data units that match the native word size of the processor, enabling optimized processing. The method ensures that the second operand is structured in a way that allows for efficient parallel or sequential operations, improving computational performance. This approach is particularly useful in applications requiring fast data manipulation, such as cryptographic operations, data compression, or numerical computations. By organizing the second operand into word-sized elements, the method reduces overhead and enhances processing speed, making it suitable for high-performance computing environments. The invention focuses on optimizing operand handling to leverage the processor's native capabilities, thereby improving efficiency and reducing latency in data processing tasks.
19. The computer-implemented method of claim 16 , wherein the instruction further comprises a third register field to be used to designate a third register, the third register comprising a third operand, and wherein the executing further comprises adding the first result to a selected element of the third operand to obtain a second result, the adding the first result using an end around carry add operation.
This invention relates to computer-implemented methods for performing arithmetic operations using specialized instruction sets. The method addresses the need for efficient and flexible arithmetic computations in processors, particularly for operations involving multiple operands and carry handling. The method involves executing an instruction that includes a first register field designating a first register containing a first operand and a second register field designating a second register containing a second operand. The instruction further includes a third register field designating a third register containing a third operand. During execution, the method performs an arithmetic operation between the first and second operands to produce a first result. This first result is then added to a selected element of the third operand using an end-around carry add operation, producing a second result. The end-around carry add operation ensures that any carry generated during the addition wraps around, allowing for modular arithmetic or other specialized calculations. This approach enhances computational efficiency by reducing the need for multiple separate instructions and leveraging hardware-accelerated operations. The method is particularly useful in applications requiring complex arithmetic, such as cryptography, digital signal processing, or scientific computing.
20. The computer-implemented method of claim 16 , wherein the executing further comprises adding the first result to a selected element of a third operand to obtain a second result, the adding the first result using an end around carry add operation, and wherein the placing comprises placing the second result in the selected element of the first operand.
This invention relates to computer-implemented methods for performing arithmetic operations, specifically using end-around carry addition in a processing system. The method addresses the challenge of efficiently handling arithmetic operations that require carry propagation, particularly in systems where traditional carry mechanisms are inefficient or impractical. The method involves executing an arithmetic operation to produce a first result, which is then added to a selected element of a third operand using an end-around carry add operation. This operation ensures that any carry generated during the addition wraps around to the least significant bit of the operand, which is useful in certain modular arithmetic or circular buffer applications. The resulting second result is then placed in the selected element of the first operand, effectively updating the operand with the new value. The method is particularly useful in systems where modular arithmetic is required, such as in cryptographic operations or digital signal processing, where traditional carry mechanisms may not be suitable. By using an end-around carry add operation, the method ensures that the arithmetic operation is performed correctly while maintaining efficiency and simplicity. The method can be implemented in hardware or software, depending on the specific requirements of the system.
Unknown
March 31, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.