Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A shift register unit, comprising a pull-up node control module, a pull-down node control module, a gate driving signal output terminal and a gate driving signal output module, wherein the gate driving signal output module is connected to a pull-up node, a pull-down node, a non-inverting clock signal input terminal and the gate driving signal output terminal respectively; and the pull-down node control module is connected to the pull-down node and an inverting clock signal input terminal respectively; wherein the shift register unit is a N-th stage in multiple stages of shift register units comprised in a gate driving circuit, the gate driving circuit is connected to four clock signal output terminals, the second clock signal is delayed 0.25 clock cycle compared to the first clock signal, a fourth clock signal is delayed 0.25 clock cycle compared to the third clock signal, and a duty ratio of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is 0.5, and the first clock signal has a phase inverted to that of the third clock signal; and the non-inverting clock signal is provided to the present stage of shift register unit by the first clock signal input terminal, and the inverting clock signal is provided to the present stage of shift register unit by a third clock signal input terminal; wherein the shift register unit further comprising: a noise reduction module connected to a noise reduction control signal output terminal and the gate driving signal output terminal respectively, the noise reduction control signal output terminal is connected to a pull-down node of a (N+2)-th stage of shift register unit; the noise reduction module is configured to control the gate driving signal output terminal to be input a low level when the noise reduction control signal is active, in an output off maintenance phase, the noise reduction control signal and the inverting clock signal have phases inverted to each other, wherein the noise reduction module further comprises: a first noise reduction transistor, whose gate is connected to the pull-down node of the (N+2)-th stage of shift register unit, first electrode is connected to the gate driving signal output terminal, and second electrode is input the low level, wherein the non-inverting clock signal is provided to the (N+2)-th stage of shift register unit by the third clock signal input terminal, and the inverting clock signal is provided to the (N+2)-th stage of shift register unit by the first clock signal input terminal.
A shift register unit for gate driving circuits in display technologies addresses timing and noise issues in display panel control. The unit includes a pull-up node control module, a pull-down node control module, a gate driving signal output terminal, and a gate driving signal output module. The output module connects to a pull-up node, pull-down node, non-inverting clock signal input, and the output terminal. The pull-down node control module connects to the pull-down node and an inverting clock signal input. The shift register unit is part of a multi-stage gate driving circuit with four clock signals. The second and fourth clock signals are delayed by 0.25 cycles relative to the first and third signals, respectively, with all signals having a 0.5 duty ratio and the first and third signals being phase-inverted. The non-inverting clock signal is sourced from the first clock signal input, while the inverting clock signal comes from the third clock signal input. The unit also includes a noise reduction module connected to a noise reduction control signal output terminal and the gate driving signal output terminal. This module controls the output terminal to receive a low level when the noise reduction control signal is active, ensuring stable operation during the output off maintenance phase. The noise reduction module features a first noise reduction transistor with its gate connected to the pull-down node of the (N+2)-th stage shift register unit, its first electrode to the output terminal, and its second electrode receiving a low level. The (N+2)-th stage receives its non-inverting clock signal from the third clock signal input and its inverting clock signal from the first clock signal input, with the noise reduction control signal and inverting clock signal being ph
2. The shift register unit according to claim 1 , wherein the pull-down node control module is configured to control a potential of the pull-down node to be the same as a potential of the inverting clock signal in the output off maintenance phase; the non-inverting clock signal and the inverting clock signal have phases inverted to each other.
A shift register unit is designed for use in electronic circuits, particularly in display drivers or timing control systems, where precise clock signal management is required. The problem addressed is maintaining stable and synchronized signal transitions during the output off maintenance phase, ensuring reliable operation of the shift register. The shift register unit includes a pull-down node control module that regulates the potential of a pull-down node to match the potential of an inverting clock signal during the output off maintenance phase. The inverting clock signal and a non-inverting clock signal are phase-inverted versions of each other, meaning they are 180 degrees out of phase. This synchronization ensures that the pull-down node accurately follows the inverting clock signal, preventing signal distortion or timing errors. The pull-down node control module ensures that the pull-down node's potential remains consistent with the inverting clock signal, which is critical for maintaining the correct timing and stability of the shift register's output. This design helps avoid signal interference and ensures proper sequencing of clock signals, which is essential for applications requiring precise timing control, such as in display scan drivers or sequential logic circuits. The phase-inverted relationship between the non-inverting and inverting clock signals allows for efficient signal management and reduces power consumption by minimizing unnecessary transitions.
3. The shift register unit according to claim 1 , wherein the noise reduction control signal output terminal is further connected to a pull-down node of a (N+m)-th stage of shift register unit, where m is a positive integer less than 2.
This invention relates to shift register units used in display driver circuits, particularly for reducing noise in display panels. The problem addressed is noise interference in shift register circuits, which can degrade signal integrity and affect display performance. The invention provides a shift register unit with an improved noise reduction control signal output terminal that connects to a pull-down node of a subsequent shift register stage. Specifically, the noise reduction control signal output terminal is connected to the pull-down node of an (N+m)-th stage, where m is a positive integer less than 2, meaning it connects to either the next stage (N+1) or the stage after that (N+2). This connection helps suppress noise by stabilizing the pull-down node, which is critical for maintaining proper signal levels in the shift register stages. The shift register unit includes a pull-up control module, a pull-down control module, and an output module, where the pull-up control module controls the charging of a pull-up node, the pull-down control module controls the discharging of a pull-down node, and the output module generates an output signal based on the states of these nodes. The noise reduction control signal output terminal enhances the pull-down control module's function by providing an additional connection to a subsequent stage, ensuring more reliable noise suppression. This design is particularly useful in high-resolution displays where noise sensitivity is a significant concern.
4. The shift register unit according to claim 3 , wherein m is equal to 1; the noise reduction module comprises: a second noise reduction transistor, whose gate is connected to a pull-down node of a (N+1)-th stage of shift register unit, first electrode is connected to the gate driving signal output terminal, and second electrode is input the low level; the non-inverting clock signal is provided to the (N+1)-th stage of shift register unit by the second clock signal input terminal, and the inverting clock signal is provided to the (N+1)-th stage of shift register unit by a fourth clock signal input terminal.
This invention relates to shift register circuits used in display driver circuits, specifically addressing noise reduction in gate driving signals. The problem solved is the presence of noise in the output signals of shift register units, which can degrade the performance of display panels. The invention describes a noise reduction module integrated into a shift register unit to mitigate this issue. The noise reduction module includes a second noise reduction transistor. The gate of this transistor is connected to the pull-down node of the next stage (N+1) in the shift register unit. The first electrode of the transistor is connected to the gate driving signal output terminal, while the second electrode receives a low-level signal. This configuration ensures that when the pull-down node of the next stage is activated, the transistor turns on, pulling the gate driving signal output to a low level, thereby reducing noise. Additionally, the shift register unit receives clock signals from two input terminals. The non-inverting clock signal is provided to the (N+1)-th stage via the second clock signal input terminal, while the inverting clock signal is provided via a fourth clock signal input terminal. This arrangement helps synchronize the noise reduction process with the clock signals, ensuring efficient noise suppression. The invention improves the reliability and stability of gate driving signals in display applications.
5. A driving method of a shift register unit of claim 1 , the driving method comprising: controlling a potential of a pull-down node to be the same as a potential of an inverting clock signal in an output off maintenance phase; controlling a noise reduction control signal and the inverting clock signal to have phases inverted to each other in the output off maintenance phase; controlling, by the noise reduction module, the gate driving signal output terminal to be input a low level when the noise reduction control signal is active.
This invention relates to a driving method for a shift register unit, particularly for reducing noise in display driver circuits. The shift register unit is used in display panels to generate gate driving signals for controlling pixel switching. A common issue in such circuits is noise interference, which can degrade signal integrity and affect display quality. The invention addresses this by providing a noise reduction mechanism during the output off maintenance phase of the shift register unit. The method involves controlling the potential of a pull-down node to match the potential of an inverting clock signal during the output off maintenance phase. Additionally, the noise reduction control signal and the inverting clock signal are phase-inverted relative to each other in this phase. A noise reduction module is used to ensure that the gate driving signal output terminal receives a low level when the noise reduction control signal is active. This helps suppress noise and maintain stable signal levels. The shift register unit includes a pull-down module, a noise reduction module, and a pull-up module. The pull-down module controls the pull-down node based on the inverting clock signal. The noise reduction module, when activated by the noise reduction control signal, forces the output terminal to a low level, preventing noise from affecting the gate driving signal. The pull-up module generates the gate driving signal during the output phase. By coordinating these components, the method ensures reliable signal transmission while minimizing noise interference.
6. A gate driving circuit, comprising multiple stages of shift register units according to claim 1 .
A gate driving circuit includes multiple stages of shift register units connected in series. Each shift register unit has an input terminal, an output terminal, a clock signal terminal, and a reset terminal. The input terminal receives a start signal or an output signal from a previous stage. The clock signal terminal receives a clock signal to control the timing of signal propagation. The output terminal generates a gate driving signal to control a gate line in a display panel. The reset terminal receives a reset signal to reset the shift register unit. The shift register unit includes a pull-up control circuit, a pull-up circuit, a pull-down circuit, and a pull-down control circuit. The pull-up control circuit controls the pull-up circuit to output the gate driving signal based on the input signal and clock signal. The pull-down circuit resets the pull-up circuit and pull-up control circuit based on the reset signal. The pull-down control circuit maintains the pull-down circuit in an active state to prevent noise interference. The gate driving circuit operates in a progressive manner, where each stage outputs a gate driving signal after receiving a signal from the previous stage, enabling sequential scanning of gate lines in a display panel. The design ensures stable signal output and reduces power consumption by minimizing leakage current.
7. The gate driving circuit according to claim 6 , wherein the noise reduction control signal output terminal of the N-th stage of shift register unit is further connected to a pull-down node of a (N+m)-th stage of shift register unit, where m is a positive integer less than 2.
This invention relates to gate driving circuits for display panels, specifically addressing noise reduction in shift register units. The circuit includes multiple stages of shift register units, each with a noise reduction control signal output terminal. This terminal is connected to a pull-down node of a subsequent shift register unit, where the subsequent unit is separated by a fixed number of stages (m), with m being a positive integer less than 2. This means the noise reduction control signal from one stage directly influences the pull-down node of the next or the following stage, ensuring stable signal transmission and reducing noise interference. The connection helps maintain proper voltage levels at the pull-down nodes, preventing signal distortion and improving the reliability of the gate driving circuit. The design is particularly useful in high-resolution displays where precise timing and noise reduction are critical. The circuit operates by generating control signals that regulate the pull-down nodes, ensuring consistent performance across multiple stages of the shift register. This approach enhances the overall stability and efficiency of the gate driving circuit in display applications.
8. The gate driving circuit according to claim 7 , wherein m is equal to 1; the non-inverting clock signal is provided to the (N+1)-th stage of shift register unit by the second clock signal input terminal, and the inverting clock signal is provided to the (N+1)-th stage of shift register unit by a fourth clock signal input terminal.
A gate driving circuit for display panels, particularly for driving gate lines in liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays, addresses the need for efficient and reliable signal distribution to shift register stages. The circuit includes a shift register with multiple stages, where each stage generates a gate driving signal based on input clock signals. The invention improves signal integrity by ensuring that the (N+1)-th stage of the shift register receives both non-inverting and inverting clock signals from separate input terminals. Specifically, the non-inverting clock signal is supplied to the (N+1)-th stage via a second clock signal input terminal, while the inverting clock signal is provided through a fourth clock signal input terminal. This configuration enhances synchronization and reduces signal distortion, improving the overall performance of the gate driving circuit. The design simplifies the clock signal routing while maintaining precise timing control, making it suitable for high-resolution displays requiring stable and accurate gate line activation. The circuit operates with a single clock signal (m=1), ensuring compatibility with existing display driver architectures.
9. A display apparatus, comprising the gate driving circuit according to claim 6 .
A display apparatus includes a gate driving circuit designed to control the operation of a display panel. The gate driving circuit generates gate signals to sequentially activate rows of pixels in the display panel, ensuring proper timing and synchronization with data signals. The circuit may incorporate shift registers, level shifters, and output buffers to produce stable and accurate gate signals. Additionally, the gate driving circuit may include features such as noise reduction mechanisms, power efficiency optimizations, and fault detection to enhance display performance and reliability. The display apparatus may be used in various electronic devices, including televisions, monitors, smartphones, and tablets, where precise control of pixel activation is essential for high-quality image rendering. The gate driving circuit's design ensures compatibility with different display technologies, such as LCD, OLED, and AMOLED, while maintaining low power consumption and high-speed operation. This apparatus addresses the need for efficient and reliable gate signal generation in modern display systems, improving overall display quality and energy efficiency.
10. The display apparatus according to claim 9 , wherein the noise reduction control signal output terminal of the N-th stage of shift register unit is further connected to a pull-down node of a (N+m)-th stage of shift register unit, where m is a positive integer less than 2.
This invention relates to display apparatuses, specifically shift register circuits used in display panels to control noise reduction. The problem addressed is noise interference between adjacent stages of shift registers, which can degrade display quality. The invention provides a solution by introducing a noise reduction control signal that connects the output terminal of an N-th stage shift register unit to the pull-down node of an (N+m)-th stage shift register unit, where m is a positive integer less than 2. This connection helps suppress noise propagation between stages, improving signal integrity. The shift register units are cascaded, with each stage generating a scan signal and a noise reduction control signal. The noise reduction control signal is output from a noise reduction control signal output terminal and is used to control the pull-down node of a subsequent stage, reducing noise interference. The pull-down node in each stage is connected to a pull-down transistor, which helps stabilize the output signal by discharging residual voltage. The invention ensures that noise from one stage does not affect the operation of nearby stages, enhancing the overall performance of the display apparatus. The solution is particularly useful in high-resolution displays where noise reduction is critical for maintaining image quality.
11. The display apparatus according to claim 10 , wherein m is equal to 1; the non-inverting clock signal is provided to the (N+1)-th stage of shift register unit by the second clock signal input terminal, and the inverting clock signal is provided to the (N+1)-th stage of shift register unit by a fourth clock signal input terminal.
A display apparatus includes a shift register unit with multiple stages, where each stage generates a scan signal for driving display elements. The apparatus addresses the challenge of synchronizing clock signals in a shift register to ensure stable and accurate signal propagation. In this configuration, the shift register unit has a specific arrangement where the (N+1)-th stage receives a non-inverting clock signal from a second clock signal input terminal and an inverting clock signal from a fourth clock signal input terminal. This setup ensures proper timing and signal integrity, preventing signal distortion or delays that could degrade display performance. The design optimizes the clock signal distribution to maintain synchronization across stages, improving the reliability of the scan signals generated by the shift register. The apparatus is particularly useful in high-resolution displays where precise timing control is critical for consistent image quality. The configuration simplifies the clock signal routing while ensuring accurate signal propagation, reducing power consumption and enhancing overall display efficiency.
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March 31, 2020
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