Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A shift register comprising: a shift register processing circuit, a control circuit, and a first reset circuit, wherein a first terminal of the control circuit is coupled to an output terminal of the shift register processing circuit, a second terminal of the control circuit is coupled to an output terminal of the shift register, and a third terminal of the control circuit is coupled to a control signal terminal, wherein the shift register is configured to output a final gate line scan signal from the output terminal of the shift register and a starting point of the final gate line scan signal is later than a starting point of a gate line scan signal outputted from the output terminal of the shift register processing circuit, wherein a first terminal of the first reset circuit is directly coupled to the output terminal of the shift register, a second terminal of the first rest circuit is coupled to a reference signal terminal, a third terminal of the first reset circuit is coupled to a reset signal terminal, the reset signal terminal is coupled to an output terminal of a shift register processing circuit of a next stage shift register; and wherein the first reset circuit is configured to supply a reference signal of the reference signal terminal to the output terminal of the shift register when a reset signal is inputted to the reset signal terminal.
A shift register is used in display driving circuits to generate gate line scan signals for controlling pixel rows in a display panel. A conventional shift register may suffer from timing mismatches between the output of the processing circuit and the final gate line scan signal, leading to display artifacts. This invention addresses the problem by introducing a control circuit and a reset circuit to improve signal timing and stability. The shift register includes a processing circuit that generates an initial gate line scan signal, a control circuit that adjusts the timing of the final output signal, and a reset circuit that ensures proper signal reset. The control circuit receives the processing circuit's output, the shift register's output, and an external control signal to delay the final gate line scan signal relative to the initial signal. The reset circuit is directly connected to the shift register's output and receives a reference signal and a reset signal from the next-stage shift register. When a reset signal is received, the reset circuit forces the output to the reference signal level, ensuring clean signal transitions. This design improves synchronization between stages and reduces timing errors, enhancing display performance. The reset circuit's direct coupling to the output ensures rapid and reliable resetting, preventing signal distortion. The control circuit's ability to adjust the output timing allows for precise control over gate line activation, improving display uniformity.
2. The shift register according to claim 1 , wherein the control circuit is configured to output the gate line scan signal outputted from the output terminal of the shift register processing circuit to the output terminal of the shift register under a control of the control signal terminal.
A shift register circuit is used in display driver applications to sequentially drive gate lines in a display panel. A common challenge in shift register design is efficiently controlling the output of scan signals to the gate lines while maintaining synchronization and minimizing signal distortion. This invention addresses this by incorporating a control circuit within the shift register that selectively outputs the gate line scan signal from the shift register processing circuit to the output terminal of the shift register. The control circuit operates under the influence of a control signal, allowing precise timing and conditional activation of the scan signal output. The shift register processing circuit generates the scan signal, which is then routed through the control circuit to the output terminal. This design ensures that the scan signal is only transmitted to the gate lines when necessary, improving power efficiency and signal integrity. The control signal terminal provides external control over the output behavior, enabling dynamic adjustment based on system requirements. This approach enhances the flexibility and reliability of the shift register in display driving applications.
3. The shift register according to claim 1 , wherein a timing of the final gate line scan signal overlaps with a timing of the gate line scan signal, and a time period of the final gate line scan signal is shorter than that of the gate line scan signal.
A shift register circuit is used in display driver systems to control the timing of gate line scan signals that activate rows of pixels in a display panel. A common challenge in such systems is ensuring precise timing control while minimizing power consumption and signal interference. This invention addresses these issues by modifying the timing characteristics of the final gate line scan signal in a shift register. The shift register generates a sequence of gate line scan signals to sequentially activate display rows. The final gate line scan signal, which triggers the last row, is synchronized with the preceding gate line scan signals but has a shorter duration. This overlapping timing ensures that the final row is activated in coordination with the previous rows, while the reduced pulse width of the final signal minimizes unnecessary power consumption and reduces the risk of signal overlap or interference. The shift register may include multiple stages, each producing a gate line scan signal, with the final stage generating the shortened final gate line scan signal. This design improves display panel performance by maintaining precise timing control while optimizing power efficiency.
4. The shift register according to claim 1 , wherein a timing of an effective control signal of the control signal terminal overlaps with a timing of the gate line scan signal, and a time period of the effective control signal is shorter than that of the gate line scan signal.
This invention relates to shift registers used in display driver circuits, particularly for controlling gate line scan signals in display panels. The problem addressed is the need for precise timing control in shift registers to ensure accurate signal propagation while minimizing power consumption and signal interference. The shift register includes multiple stages, each with input and output terminals for receiving and transmitting scan signals. A control signal terminal is used to regulate the operation of each stage. The key improvement is that the effective control signal timing overlaps with the gate line scan signal timing, but the duration of the effective control signal is shorter than that of the gate line scan signal. This ensures that the control signal is active only when necessary, reducing power consumption and preventing signal distortion. The overlapping timing allows the shift register to maintain synchronization with the gate line scan signal, while the shorter duration of the effective control signal prevents unnecessary power dissipation and signal interference. This design is particularly useful in large-area display panels where precise timing control is critical for uniform display performance. The invention enhances the efficiency and reliability of shift register operations in display driver circuits.
5. The shift register according to claim 1 , wherein the control circuit comprises a first thin film transistor, wherein a gate of the first thin film transistor is coupled to the control signal terminal, a source of the first thin film transistor is coupled to the output terminal of the shift register processing circuit, and a drain of the first thin film transistor is coupled to the output terminal of the shift register.
A shift register circuit includes a control circuit that regulates signal output to prevent signal distortion. The control circuit comprises a thin film transistor (TFT) with a gate connected to a control signal terminal, a source connected to the output of a shift register processing circuit, and a drain connected to the output terminal of the shift register. The TFT acts as a switch, enabling or disabling signal transmission based on the control signal. When activated, the TFT allows the processed signal from the shift register processing circuit to pass to the output terminal. When deactivated, it blocks the signal, preventing unwanted signal propagation. This design ensures precise control over signal output, reducing distortion and improving signal integrity in display driver circuits or other sequential logic applications. The shift register processing circuit generates the output signal, while the control circuit's TFT-based switch provides dynamic signal management. This configuration is particularly useful in display technologies where accurate timing and signal stability are critical.
6. The shift register according to claim 1 , further comprising a filter circuit, wherein the filter circuit is coupled between the output terminal of the shift register processing circuit and the first terminal of the control circuit, and the filter circuit is configured to eliminate noise in the gate line scanning signal outputted from the output terminal of the shift register processing circuit, and then output the gate line scanning signal to the first terminal of the control circuit.
A shift register circuit is used in display driver applications to generate gate line scanning signals for driving display panels. A common challenge in such circuits is noise interference, which can degrade signal integrity and affect display performance. This invention addresses this problem by incorporating a filter circuit into the shift register design. The filter circuit is positioned between the output terminal of the shift register processing circuit and the control circuit. Its primary function is to eliminate noise from the gate line scanning signal generated by the shift register processing circuit before passing the cleaned signal to the control circuit. By filtering out noise, the circuit ensures that the gate line scanning signal remains stable and reliable, improving the overall performance of the display driver. The filter circuit operates by processing the signal to remove unwanted noise components while preserving the desired signal characteristics. This enhancement helps maintain accurate timing and signal quality, which is critical for proper display operation. The invention is particularly useful in applications where signal integrity is paramount, such as in high-resolution or high-refresh-rate displays.
7. The shift register according to claim 6 , wherein the filter circuit comprises a second thin film transistor; wherein a gate and a source of the second thin film transistor are coupled to the output terminal of the shift register processing circuit respectively, and a drain of the second thin film transistor is coupled to the first terminal of the control circuit.
A shift register circuit includes a filter circuit designed to improve signal integrity in display driver applications. The filter circuit incorporates a second thin film transistor (TFT) to manage signal transmission between the shift register processing circuit and the control circuit. The gate and source terminals of the second TFT are connected to the output terminal of the shift register processing circuit, while the drain terminal is linked to the first terminal of the control circuit. This configuration ensures controlled signal propagation, reducing noise and enhancing reliability in the shift register's operation. The filter circuit's design helps mitigate signal distortion, which is critical for maintaining precise timing in display scanning operations. The use of a TFT in the filter circuit allows for compact integration within the shift register, supporting high-resolution display applications where space and performance are key constraints. The overall system ensures stable signal transmission, improving the efficiency and accuracy of the shift register in driving display elements.
8. The shift register according to claim 1 , wherein the first reset circuit comprises a third thin film transistor, wherein a gate of the third thin film transistor is coupled to the reset signal terminal, a source of the third thin film transistor is coupled to the reference signal terminal, and a drain of the third thin film transistor is coupled to the output terminal of the shift register.
This invention relates to a shift register circuit, specifically an improvement in the reset functionality of a shift register using thin film transistors (TFTs). Shift registers are essential in display driver circuits for controlling pixel data signals, but conventional designs often suffer from signal integrity issues due to leakage currents or incomplete resetting, leading to display artifacts. The invention addresses these problems by incorporating a dedicated reset circuit within the shift register. The reset circuit includes a third thin film transistor (TFT) that actively resets the output terminal of the shift register. The gate of this TFT is connected to a reset signal terminal, allowing precise control over the reset timing. The source is coupled to a reference signal terminal, which provides a stable reference voltage for resetting the output. The drain is directly connected to the shift register's output terminal, ensuring direct and efficient resetting. This design ensures that the shift register output is fully reset to a known state, preventing residual signals from affecting subsequent operations. The use of a dedicated TFT for resetting improves signal integrity and reduces power consumption by minimizing unnecessary current flow. The circuit is particularly useful in display driver applications where accurate signal timing and low power operation are critical. The reset mechanism is integrated into the shift register structure, making it compact and suitable for high-density display panels.
9. The shift register according to claim 1 , wherein the shift register processing circuit comprises an input circuit, an output circuit, a second reset circuit and a pull-down control circuit; wherein a first terminal of the input circuit is coupled to a signal input terminal, a second terminal of the input circuit is coupled to a first node, the signal input terminal is coupled to an output terminal of a shift register processing circuit of a previous stage shift register; and the input circuit is configured to control an electric potential of the first node to be a first electric potential when an effective pulse signal is inputted to the signal input terminal; wherein a first terminal of the output circuit is coupled to a first clock signal terminal, a second terminal of the output circuit is coupled to the first node, a third terminal of the output circuit is coupled to the output terminal of the shift register processing circuit; and the output circuit is configured to supply a clock signal of the first clock signal terminal to the output terminal of the shift register processing circuit when the first node is at the first electric potential; wherein a first terminal of the second reset circuit is coupled with the reference signal terminal, a second terminal of the second reset circuit is coupled to the reset signal terminal, a third terminal of the second reset circuit is coupled to the first node, a fourth terminal of the second reset circuit is coupled to the output terminal of the shift register processing circuit, the reset signal terminal is coupled to the output terminal of the shift register processing circuit of the next stage shift register; and the second reset circuit is configured to supply the reference signal of the reference signal terminal to the first node and the output terminal of the shift register processing circuit when the reset signal is inputted to the reset signal terminal; and wherein a first terminal of the pull-down control circuit is coupled to a second clock signal terminal, a second terminal of the pull-down control circuit is coupled to the reference signal terminal, a third terminal of the pull-down control circuit is coupled to the first node, a fourth terminal of the pull-down control circuit is coupled to the output terminal of the shift register processing circuit; and the pull-down control circuit is configured to provide the reference signal of the reference signal terminal to the first node and the output terminal of the shift register processing circuit when a clock signal is inputted to the second clock signal terminal.
This invention relates to a shift register circuit used in display driver circuits, particularly for controlling signal propagation in sequential stages. The problem addressed is ensuring reliable signal transmission and reset operations in shift registers, which are critical for timing control in display panels. The shift register includes an input circuit, output circuit, second reset circuit, and pull-down control circuit. The input circuit receives an effective pulse signal from a previous stage shift register and sets a first node to a first electric potential. The output circuit then supplies a clock signal from a first clock signal terminal to the output terminal when the first node is at this potential, enabling signal propagation. The second reset circuit, triggered by a reset signal from the next stage shift register, supplies a reference signal to the first node and output terminal, ensuring proper reset operations. The pull-down control circuit further stabilizes the circuit by providing the reference signal to the first node and output terminal when a clock signal is received from a second clock signal terminal, preventing signal leakage and maintaining signal integrity. This design improves shift register reliability and performance in display driver applications.
10. The shift register according to claim 9 , wherein the shift register processing circuit further comprises a pull-down circuit, wherein a first terminal of the pull-down circuit is coupled to the second clock signal terminal, a second terminal of the pull-down circuit is coupled to the first node, a third terminal of the pull-down circuit is coupled to the signal input terminal, a fourth terminal of the pull-down circuit is coupled to the reference signal terminal, a fifth terminal of the pull-down circuit is coupled to the output terminal of the shift register processing circuit; and the pull-down circuit is configured to supply the reference signal of the reference signal terminal to the output terminal of the shift register processing circuit and turn on the signal input terminal and the first node when the clock signal is inputted to the second clock signal terminal.
A shift register circuit includes a pull-down circuit integrated into the shift register processing circuit to enhance signal control and stability. The pull-down circuit has five terminals: the first terminal connects to a second clock signal input, the second terminal connects to an internal node, the third terminal connects to a signal input, the fourth terminal connects to a reference signal (e.g., ground or a low voltage), and the fifth terminal connects to the output of the shift register processing circuit. When a clock signal is applied to the second clock signal terminal, the pull-down circuit actively routes the reference signal to the output terminal while simultaneously enabling the signal input and the internal node. This configuration ensures precise timing and signal integrity by preventing unwanted voltage fluctuations during clock transitions, improving the reliability of the shift register in display driver circuits or sequential logic applications. The pull-down circuit operates in synchronization with the clock signal to maintain proper signal levels, reducing noise and enhancing performance in high-speed or high-resolution systems.
11. A gate integrated driving circuit, comprising: a plurality of shift registers comprising the shift register according to claim 1 .
A gate integrated driving circuit includes a plurality of shift registers designed to control the timing and activation of gate lines in a display panel. Each shift register generates a scanning signal to sequentially drive the gate lines, ensuring proper pixel charging and display functionality. The shift registers are interconnected to propagate control signals through the circuit, allowing synchronized operation across multiple stages. The circuit may also include additional components such as pull-up and pull-down transistors, capacitors, and clock signal inputs to manage signal stability and timing accuracy. By integrating multiple shift registers into a single driving circuit, the design reduces the need for external control components, simplifies the overall display architecture, and improves manufacturing efficiency. The circuit is particularly useful in active-matrix display technologies, where precise timing control is essential for high-quality image rendering. The shift registers may be configured to operate in either forward or reverse scanning modes, providing flexibility in display panel design. The integrated driving circuit enhances reliability and reduces power consumption by minimizing signal interference and optimizing signal propagation paths.
12. The gate integrated driving circuit according to claim 11 , wherein there is a certain time interval between final output signals from output terminals of two adjacent shift registers to a coupled gate line.
A gate integrated driving circuit is designed to control gate lines in display panels, such as those used in liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays. The circuit includes multiple shift registers connected to gate lines, where each shift register generates an output signal to drive a corresponding gate line. A key feature of this circuit is the introduction of a time interval between the final output signals of two adjacent shift registers. This time interval ensures that the signals driving adjacent gate lines do not overlap, preventing potential interference or crosstalk between neighboring gate lines. The circuit may also include additional components, such as a control signal generator, to manage the timing and synchronization of the output signals. The time interval is adjustable based on the display's requirements, allowing for optimized performance and reduced power consumption. This design improves the reliability and stability of the display by minimizing signal conflicts and ensuring precise timing control over the gate lines.
13. A display device comprising the gate integrated driving circuit of claim 12 .
A display device includes a gate integrated driving circuit designed to control the gate lines of a display panel. The driving circuit integrates a shift register unit, a level shifter, and a buffer amplifier into a single chip, reducing the number of external components and simplifying the circuit design. The shift register unit generates sequential output signals to drive the gate lines, while the level shifter adjusts the voltage levels of these signals to meet the requirements of the display panel. The buffer amplifier then amplifies the adjusted signals to ensure stable and reliable transmission to the gate lines. This integrated approach minimizes signal distortion, reduces power consumption, and improves the overall efficiency of the display device. The driving circuit is particularly useful in high-resolution displays where precise timing and signal integrity are critical. By consolidating multiple functions into a single chip, the design also reduces manufacturing costs and enhances reliability. The display device incorporating this integrated driving circuit is suitable for applications such as smartphones, tablets, and other electronic devices requiring compact and efficient display solutions.
14. A driving method of the gate integrated driving circuit of claim 11 , the driving method comprising: applying a low level signal to a control signal terminal of an N th stage shift register after an N−1 stage shift register outputs a high level signal; and applying a high level signal to the control signal terminal of the N th stage shift register after a period to make a starting point of a final gate line scan signal outputted from an output terminal of the N th stage shift register later than a starting point of a gate line scan signal outputted from an output terminal of an N th stage shift register processing circuit.
This invention relates to a driving method for a gate integrated driving circuit used in display panels, particularly for controlling the timing of gate line scan signals in shift registers. The problem addressed is the synchronization of scan signal outputs between adjacent shift register stages to prevent overlapping or misalignment, which can cause display defects. The method involves controlling the timing of a control signal applied to an Nth stage shift register. After the preceding N-1 stage shift register outputs a high level signal, a low level signal is applied to the control signal terminal of the Nth stage. This delays the activation of the Nth stage. After a defined period, a high level signal is applied to the same control terminal, enabling the Nth stage to output its gate line scan signal. The key innovation is that the starting point of the final gate line scan signal from the Nth stage is intentionally delayed relative to the starting point of the gate line scan signal from an associated Nth stage processing circuit. This ensures proper sequencing and prevents signal conflicts during display panel operation. The method improves display uniformity and reduces defects by precisely controlling the timing of scan signal propagation through the shift register stages.
15. The driving method of the gate integrated circuit of claim 14 , wherein there is a certain time interval between final output signals from output terminals of two adjacent shift registers to a coupled gate line.
The invention relates to driving methods for gate integrated circuits, specifically addressing timing control in display panels to prevent signal interference between adjacent gate lines. The problem solved is the risk of signal overlap or crosstalk when driving multiple gate lines simultaneously or in rapid succession, which can degrade display quality. The method involves controlling the timing of output signals from shift registers connected to gate lines, ensuring a defined time interval between the final output signals of adjacent shift registers. This interval prevents overlapping signals from interfering with each other, maintaining proper gate line activation sequences. The shift registers are part of a gate driver circuit that sequentially activates gate lines in a display panel, such as in liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays. The time interval is adjusted based on signal propagation delays and panel characteristics to optimize performance while avoiding interference. This method enhances display reliability and image quality by ensuring precise timing control of gate line activation.
16. A driving method of the shift register of claim 1 , the driving method comprising: applying a low level signal to the control signal terminal at the starting point of the gate line scan signal outputted from the output terminal of the shift register processing circuit; and applying a high level signal to the control signal terminal after a period to make the starting point of the final gate line scan signal outputted from the output terminal of the shift register later than the starting point of the gate line scan signal outputted from the output terminal of the shift register processing circuit.
This invention relates to a driving method for a shift register circuit used in display panels, particularly addressing timing control issues in gate line scan signals. The method involves adjusting the timing of the starting point of the final gate line scan signal relative to the initial gate line scan signal output by the shift register processing circuit. Initially, a low-level signal is applied to the control signal terminal at the starting point of the gate line scan signal output from the shift register. After a predetermined period, a high-level signal is applied to the control signal terminal, causing the starting point of the final gate line scan signal to be delayed compared to the initial gate line scan signal. This timing adjustment ensures proper synchronization and prevents signal overlap or misalignment in the display panel's gate driving process. The method is designed to improve the stability and accuracy of the scan signal output, enhancing display performance by maintaining precise timing control over the gate lines. The shift register circuit itself includes multiple stages, each with input, output, and control terminals, and operates in conjunction with clock signals to generate sequential scan signals for driving the display panel's gate lines. The driving method optimizes the signal propagation delay to ensure consistent and reliable gate line activation.
17. The driving method according to claim 16 , wherein a timing of the final gate line scan signal overlaps with a timing of the gate line scan signal, and a time period of the final gate line scan signal is shorter than that of the gate line scan signal.
This invention relates to a driving method for a display panel, specifically addressing the issue of improving display quality and reducing power consumption by optimizing the timing of gate line scan signals. The method involves generating a final gate line scan signal that overlaps in timing with a standard gate line scan signal but has a shorter duration. This overlapping and shortened signal timing helps to mitigate display artifacts such as flicker or ghosting while ensuring efficient power usage. The technique is particularly useful in active matrix display panels, where precise control of gate line signals is critical for maintaining image stability and reducing energy consumption. By adjusting the duration of the final gate line scan signal relative to the standard signal, the method ensures that the display panel operates with improved uniformity and responsiveness. The approach can be applied to various display technologies, including liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays, where gate line timing plays a key role in pixel charging and discharging processes. The invention provides a solution for enhancing display performance without requiring significant hardware modifications, making it suitable for integration into existing display driver architectures.
18. The driving method according to claim 16 , wherein a timing of an effective control signal of the control signal terminal overlaps with a timing of the gate line scan signal, and a time period of the effective control signal is shorter than that of the gate line scan signal.
This invention relates to a driving method for a display device, specifically addressing the challenge of improving display performance by optimizing the timing of control signals in gate line scanning. The method involves generating a gate line scan signal to drive a gate line in a display panel, where the gate line scan signal includes an effective period and an ineffective period. A control signal is applied to a control signal terminal of a switching transistor, with the timing of the effective control signal overlapping the timing of the gate line scan signal. However, the duration of the effective control signal is shorter than that of the gate line scan signal. This ensures that the switching transistor is activated only during a specific portion of the gate line scan signal, reducing power consumption and preventing signal interference. The method also includes generating a data signal for the display panel, where the data signal is synchronized with the gate line scan signal to ensure proper pixel charging. The overlapping but shorter effective control signal timing improves display uniformity and reduces signal distortion, enhancing overall display quality. The invention is particularly useful in active matrix display technologies, such as liquid crystal displays (LCDs) or organic light-emitting diode (OLED) displays, where precise control of gate line signals is critical for optimal performance.
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April 7, 2020
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