Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: a differential data bus; and a transceiver circuit configured and arranged to send and receive data on the differential data bus, and including a differential driver configured and arranged to operate and communicate in a first communication mode and a second communication mode; a differential receiver configured and arranged to operate and communicate in the first communication mode and the second communication mode, wherein the differential receiver is configured to monitor the data on the differential bus and output a digital stream that is representative of differential signals on the differential data bus; and wherein the transceiver circuit includes sense circuitry, the transceiver circuit is configured and arranged to switch to the second communication mode in response to the sense circuitry detecting a signal edge of a signal input received at the differential driver by: the transceiver circuit and the sense circuitry pre-conditioning the differential receiver for transitioning to the second communication mode, wherein the pre-conditioning includes keeping voltage difference on the differential data bus in low and high state below a predefined value.
This invention relates to data communication systems and addresses the problem of efficiently and reliably transmitting data over a differential bus, particularly when transitioning between different communication modes. The apparatus includes a differential data bus and a transceiver circuit. The transceiver circuit is designed to send and receive data on this bus. It comprises a differential driver and a differential receiver, both capable of operating in a first and a second communication mode. The differential receiver monitors the data on the bus and outputs a digital stream representing the differential signals. A key feature is the transceiver circuit's ability to switch to the second communication mode. This switching is triggered by sense circuitry that detects a signal edge on an input signal received by the differential driver. During this transition, the transceiver circuit and the sense circuitry pre-condition the differential receiver for the second mode. This pre-conditioning involves ensuring that the voltage difference on the differential data bus, in both low and high states, remains below a specific predefined value. This process facilitates a smooth and reliable transition between communication modes.
2. The transceiver circuit of claim 1 , further including control circuitry configured and arranged to control an output impedance of the transceiver circuit to be within a predefined range of an impedance value at the first communication mode while a differential driver voltage on the differential data bus decreases to a voltage that overrides a predefined voltage, wherein the differential driver is configured to drive the differential driver voltage on the differential data bus to the voltage that overrides the predefined voltage.
A transceiver circuit is designed for high-speed data communication, particularly in systems where differential signaling is used to transmit data over a differential data bus. The circuit operates in multiple communication modes, including a first mode where data is transmitted at a specific impedance level to ensure signal integrity and minimize reflections. A key challenge in such systems is maintaining stable communication when the differential driver voltage on the bus decreases, which can lead to signal degradation or loss of synchronization. To address this, the transceiver circuit includes control circuitry that dynamically adjusts the output impedance of the transceiver. This adjustment ensures that the impedance remains within a predefined range of the optimal impedance value for the first communication mode, even as the differential driver voltage drops. The differential driver is configured to drive the voltage on the bus to a level that overrides a predefined threshold, which could indicate a transition to a different operating condition or a fault state. The control circuitry intervenes to stabilize the impedance, preventing signal distortion and maintaining reliable data transmission. This feature is particularly useful in applications where voltage fluctuations or transient conditions could otherwise disrupt communication. The solution enhances robustness in high-speed data links, ensuring consistent performance under varying voltage conditions.
3. The transceiver circuit of claim 1 , wherein the first communication mode includes a dominant state and the second communication mode includes a recessive state, and the differential driver is further configured and arranged to drive a differential driver voltage on the differential data bus to a voltage that overrides a predefined voltage, the predefined voltage being lower than a receiver switching voltage of the differential receiver.
This invention relates to transceiver circuits for differential data buses, addressing the challenge of ensuring reliable communication in systems where multiple communication modes must coexist. The transceiver circuit includes a differential driver and a differential receiver connected to a differential data bus. The differential driver is configured to operate in at least two communication modes: a first mode with a dominant state and a second mode with a recessive state. In the first mode, the driver is designed to override a predefined voltage on the bus, which is lower than the receiver's switching voltage. This ensures that the dominant state is clearly distinguishable from the recessive state, preventing misinterpretation by the receiver. The predefined voltage is set below the receiver's threshold to avoid false triggering while maintaining signal integrity. The differential receiver is configured to detect the differential driver voltage and determine the communication mode based on the voltage level. This design allows the transceiver to support multiple communication protocols or states without interference, improving reliability in mixed-mode communication systems. The invention is particularly useful in applications requiring robust data transmission in noisy environments or where different communication standards must coexist on the same bus.
4. The transceiver circuit of claim 3 , wherein the voltage that overrides the predefined voltage is lower than a receiver switching voltage of the differential receiver.
A transceiver circuit is designed to improve signal integrity in high-speed data communication systems, particularly in environments where signal degradation and noise interference are problematic. The circuit includes a differential receiver that converts differential input signals into a single-ended output signal. A key challenge in such systems is ensuring reliable signal detection while minimizing power consumption and avoiding false triggering due to noise or voltage fluctuations. The transceiver circuit incorporates a voltage override mechanism that adjusts the receiver's operating voltage to enhance signal detection accuracy. Specifically, the circuit includes a predefined voltage level that the receiver uses as a reference for signal comparison. However, under certain conditions, such as when the input signal strength is weak or when noise is present, the circuit overrides this predefined voltage with a lower voltage. This lower override voltage is carefully selected to be below the receiver's switching voltage, which is the threshold at which the differential receiver transitions between detecting a logic high and a logic low. By setting the override voltage lower than the switching voltage, the circuit ensures that the receiver remains in a stable state, reducing the risk of false triggering while maintaining sensitivity to valid input signals. This approach improves signal integrity and reliability in high-speed communication applications.
5. The transceiver circuit of claim 1 , wherein the differential driver is further configured and arranged to drive a differential driver voltage to: a voltage that overrides a predefined voltage in response to the signal edge and for a first period of time; and the predefined voltage that is greater than the voltage for a second period of time.
A transceiver circuit includes a differential driver configured to drive a differential driver voltage in response to a signal edge. The differential driver is further configured to drive the differential driver voltage to a voltage that overrides a predefined voltage for a first period of time following the signal edge. After this first period, the differential driver transitions the differential driver voltage to the predefined voltage, which is greater than the voltage used during the first period. This configuration ensures controlled signal transmission by initially overriding the predefined voltage to handle the signal edge and then stabilizing at the predefined voltage for reliable data transmission. The differential driver may be part of a larger transceiver system designed to optimize signal integrity and reduce noise during high-speed data communication. The predefined voltage is set to a level that ensures proper signal levels for the communication protocol being used, while the overriding voltage provides a temporary boost to handle transient conditions at the signal edge. This approach improves signal quality and reduces errors in high-speed communication systems.
6. The transceiver circuit of claim 5 , wherein the differential driver is configured and arranged to drive the differential driver voltage to the voltage that overrides the predefined voltage for the first period of time that is between 30-150 nanoseconds.
A transceiver circuit includes a differential driver that generates a differential signal for data transmission. The differential driver is configured to drive a differential driver voltage to a specific voltage level that overrides a predefined voltage for a controlled duration. This override occurs during a first period of time that ranges between 30 and 150 nanoseconds. The purpose of this override is to enhance signal integrity or performance during specific operating conditions, such as initialization, synchronization, or error recovery. The differential driver may be part of a larger transceiver system that includes additional components like amplifiers, filters, or control logic to manage signal transmission and reception. The predefined voltage is typically a default or nominal operating voltage, and the override ensures the signal meets required specifications during critical phases. The duration of the override is carefully selected to balance performance improvements with power efficiency and system stability. This technique is particularly useful in high-speed communication systems where precise voltage control is essential for reliable data transfer.
7. The transceiver circuit of claim 1 , wherein the differential driver is configured and arranged to drive a differential driver voltage on the differential data bus to a negative voltage for a period of time.
This invention relates to transceiver circuits for differential data buses, particularly addressing the challenge of improving signal integrity and power efficiency in high-speed data transmission. The transceiver circuit includes a differential driver that actively drives the differential data bus to a negative voltage level for a specified duration. This technique helps mitigate signal distortion, reduce power consumption, and enhance data transmission reliability by ensuring proper voltage levels during idle or transition states. The differential driver is designed to generate a differential voltage across the bus, where one of the differential lines is driven to a negative voltage while the other is maintained at a higher potential, creating a controlled voltage differential. This approach is particularly useful in applications requiring precise signal timing and low-power operation, such as in communication systems, data centers, and high-performance computing environments. The negative voltage drive helps prevent signal degradation caused by capacitive coupling or noise, ensuring cleaner signal transitions and reducing the risk of data errors. The circuit may also include additional components, such as termination resistors or bias circuits, to further optimize signal integrity and power efficiency. The overall design aims to provide a robust and energy-efficient solution for differential data transmission in modern electronic systems.
8. The transceiver circuit of claim 1 , further including sense circuitry configured and arranged to provide a signal to the differential receiver responsive to detecting the signal edge of the signal input received at the differential driver.
A transceiver circuit includes a differential driver and a differential receiver, where the differential driver is configured to receive a signal input and generate a differential output signal. The differential receiver is configured to receive the differential output signal and provide a corresponding output. The transceiver circuit further includes sense circuitry that detects the signal edge of the input signal received by the differential driver. Upon detecting the signal edge, the sense circuitry provides a signal to the differential receiver. This signal may be used to improve timing synchronization, reduce latency, or enhance signal integrity in high-speed communication systems. The sense circuitry operates in conjunction with the differential driver and receiver to ensure accurate signal transmission and reception, particularly in applications where precise timing and edge detection are critical, such as in high-frequency data links or serial communication protocols. The overall design aims to optimize signal processing efficiency while maintaining robustness against noise and distortion.
9. The transceiver circuit of claim 8 , wherein the signal provided to the differential receiver includes an offset to a receiver switching threshold and the differential receiver is configured and arranged to provide a second communication mode output in response to a differential driver voltage exceeding an offset receiver threshold.
This invention relates to transceiver circuits designed for differential signaling, addressing challenges in signal integrity and communication mode flexibility. The circuit includes a differential receiver that processes signals with an intentional offset to the receiver's switching threshold. This offset allows the receiver to distinguish between different communication modes based on the differential driver voltage. Specifically, when the differential driver voltage exceeds the offset receiver threshold, the receiver generates a second communication mode output, enabling dynamic adaptation to varying signal conditions. The differential receiver is configured to operate in multiple modes, enhancing versatility in data transmission and reception. The offset mechanism ensures reliable detection of signals even in noisy environments, improving overall system robustness. The transceiver circuit is particularly useful in applications requiring high-speed data transfer and adaptive communication protocols, such as in wired or wireless communication systems. The invention focuses on optimizing signal processing to support multiple operational states without requiring additional hardware, thereby simplifying design and reducing cost. The differential receiver's ability to respond to voltage thresholds with an offset ensures accurate mode switching, addressing common issues in signal distortion and interference.
10. The transceiver circuit of claim 8 , wherein the signal provided to the differential receiver is indicative of the transition of the transceiver circuit to the second communication mode, and the differential receiver is configured and arranged to output a receive data (RXD) signal at a level associated with the second communication mode in response.
A transceiver circuit is designed to operate in multiple communication modes, such as a first mode for high-speed data transfer and a second mode for lower-speed or alternative signaling. The circuit includes a differential receiver that processes incoming signals and generates a receive data (RXD) signal. When the transceiver transitions from the first mode to the second mode, the circuit provides a signal to the differential receiver that indicates this mode change. In response, the differential receiver adjusts its output level to match the requirements of the second communication mode, ensuring proper signal integrity and compatibility with the new operating conditions. This adjustment may involve modifying voltage levels, timing, or other signal characteristics to optimize performance in the second mode. The transceiver circuit may also include additional components, such as a transmitter and control logic, to manage mode transitions and signal processing. The differential receiver's ability to dynamically adapt to different communication modes enhances flexibility and reliability in varying operational environments.
11. The transceiver circuit of claim 8 , wherein the sense circuitry is further configured and arranged to monitor the signal input to the differential driver to identify the signal edge, the signal input including a transmit data (TXD) signal received at the transceiver circuit.
A transceiver circuit includes sense circuitry configured to monitor a signal input to a differential driver to identify a signal edge. The signal input includes a transmit data (TXD) signal received at the transceiver circuit. The differential driver generates a differential output signal based on the TXD signal. The sense circuitry detects transitions or edges in the TXD signal to synchronize operations or improve signal integrity. The transceiver circuit may also include a receiver configured to process incoming differential signals and convert them into a received data signal. The differential driver and receiver may be part of a high-speed communication interface, such as a serial data link, where precise timing and edge detection are critical for reliable data transmission. The sense circuitry may further include comparators, delay elements, or other timing circuits to accurately detect signal edges and ensure proper synchronization between transmitted and received signals. This configuration enhances signal integrity and reduces errors in high-speed data communication systems.
12. A method for operating a transceiver circuit comprising: detecting a signal edge of a signal input received at a differential driver of the transceiver circuit; and in response to detecting the signal edge, switching the transceiver circuit from a first communication mode to a second communication mode by pre-conditioning a differential receiver of the transceiver circuit for transitioning to the second communication mode, wherein the pre-conditioning includes keeping voltage difference on the differential data bus in low and high state below a predefined value, wherein the differential receiver is configured to monitor the data on the differential bus and output a digital stream that is representative of differential signals on the differential data bus, wherein pre-conditioning the differential receiver for the transition to the second communication mode includes providing a signal to the differential receiver responsive to detecting the signal edge of the signal as received at the differential driver, and controlling an output impedance of the transceiver circuit to be within a predefined range of an impedance value at the first communication mode and while a differential driver voltage decreases to a predefined voltage.
This invention relates to transceiver circuits used in communication systems, specifically addressing the challenge of efficiently transitioning between different communication modes while maintaining signal integrity. The method involves detecting a signal edge of an input signal received at a differential driver within the transceiver circuit. Upon detection, the transceiver circuit switches from a first communication mode to a second communication mode by pre-conditioning a differential receiver. This pre-conditioning ensures that the voltage difference on the differential data bus remains within a predefined range, avoiding excessive voltage swings that could disrupt communication. The differential receiver monitors data on the differential bus and outputs a digital stream representing the differential signals. The pre-conditioning process includes sending a signal to the differential receiver in response to the detected signal edge and controlling the transceiver circuit's output impedance to stay within a predefined range of the impedance value in the first communication mode. Additionally, the differential driver voltage is allowed to decrease to a predefined voltage during this transition. This approach ensures smooth and reliable mode switching while maintaining signal quality and minimizing disruptions in data transmission.
13. The method of claim 12 , further including controlling the output impedance of the transceiver circuit to be within the predefined range of the impedance value at the first communication mode and while driving the differential driver voltage on the differential data bus to: a first voltage for a first period of time in response to detecting the signal edge; and a second voltage that is greater than the first voltage for a second period of time after the first period of time, wherein the second voltage is predefined for switching the differential receiver from the first communication mode to the second communication mode.
This invention relates to transceiver circuits for differential data buses, particularly for managing impedance and voltage transitions between different communication modes. The problem addressed is ensuring reliable mode switching in differential signaling systems while maintaining signal integrity and minimizing power consumption. The method involves controlling the output impedance of a transceiver circuit to stay within a predefined range during a first communication mode. When a signal edge is detected, the differential driver voltage on the bus is adjusted in two stages. First, a lower voltage is applied for a short duration, followed by a higher voltage for a longer period. The higher voltage is specifically chosen to trigger a transition from the first communication mode to a second communication mode in the differential receiver. This approach ensures smooth and controlled mode switching without disrupting data transmission. The technique is particularly useful in systems where multiple communication modes are supported, such as in high-speed serial links or multi-mode transceivers. By carefully managing impedance and voltage levels, the method prevents signal reflections, reduces power consumption, and maintains signal integrity during mode transitions. The predefined voltage levels and timing ensure compatibility with the receiver's switching thresholds, enabling seamless operation across different modes.
14. An apparatus comprising: a differential data bus; and a transceiver circuit configured to send and receive data on the differential data bus, to detect a signal edge of a received signal input, and the transceiver circuit including a differential driver and a differential receiver to communicate on the differential data bus in a first communication mode and in a second communication mode; and the transceiver circuit being further configured to switch to the second communication mode in response detecting a signal edge of the signal input received at the differential driver by pre-conditioning the differential receiver, including keeping a voltage difference on the differential data bus in low and high state below a predefined value, for transitioning to the second communication mode, and respond to the signal edge of the signal input received at the differential driver of the transceiver circuit to expedite switching to the second communication mode edge when, during operation, the voltage difference on the differential data bus is below a switching threshold of the differential receiver.
This invention relates to a transceiver circuit for differential data bus communication, addressing the challenge of efficiently switching between communication modes while maintaining signal integrity. The apparatus includes a differential data bus and a transceiver circuit that sends and receives data on the bus. The transceiver circuit features a differential driver and a differential receiver, enabling communication in two modes. To expedite mode switching, the transceiver detects a signal edge of the received input and pre-conditions the differential receiver by maintaining the voltage difference on the bus below a predefined value. This pre-conditioning ensures a smooth transition to the second communication mode, particularly when the bus voltage difference is below the receiver's switching threshold. The transceiver responds to the detected signal edge to accelerate the mode switch, improving communication efficiency and reducing latency. The design ensures reliable data transmission while optimizing performance during mode transitions.
15. The apparatus of claim 14 , wherein the differential driver is to drive the differential data bus with a differential driver voltage that overrides a predefined voltage to facilitate the pre-conditioning.
A system for managing data transmission in electronic devices addresses the challenge of ensuring reliable signal integrity during high-speed data transfers. The system includes a differential driver configured to drive a differential data bus with a controlled voltage level. This voltage level is dynamically adjusted to override a predefined voltage setting, enabling pre-conditioning of the bus before data transmission. Pre-conditioning involves setting the bus to a specific voltage state to reduce signal distortion, improve timing margins, and enhance overall transmission quality. The differential driver operates by generating differential signals that are transmitted across the bus, with the ability to modulate the driver voltage to achieve the desired pre-conditioning effect. This adjustment ensures that the bus is optimized for subsequent data transfers, minimizing errors and improving performance in high-speed communication applications. The system is particularly useful in environments where signal integrity is critical, such as in high-performance computing, telecommunications, and data center networks. By dynamically controlling the driver voltage, the system adapts to varying operating conditions, ensuring consistent and reliable data transmission.
16. The apparatus of claim 14 , wherein the transceiver circuit is further configured to respond to the signal edge of the signal input by mitigating delay of a related signal that is indicative of the second communication mode.
This invention relates to communication systems, specifically to apparatuses that adapt to different communication modes. The problem addressed is the delay introduced when switching between communication modes, which can degrade performance. The apparatus includes a transceiver circuit that detects a signal edge in an input signal, indicating a transition between communication modes. Upon detecting this edge, the transceiver circuit mitigates delay in a related signal that corresponds to the second communication mode, ensuring faster and more reliable mode switching. The related signal may be a control signal, a clock signal, or another synchronization signal used in the second communication mode. By reducing delay in this signal, the apparatus improves the efficiency and responsiveness of the communication system during mode transitions. The transceiver circuit may also include additional components, such as a phase-locked loop (PLL) or a delay-locked loop (DLL), to further enhance signal synchronization and minimize latency. The invention is particularly useful in high-speed communication systems where rapid mode switching is critical, such as in wireless networks, data centers, or other digital communication environments.
17. The apparatus of claim 14 , wherein the transceiver circuit is further configured to respond to the signal edge of the signal input by minimizing a state-transition period manifested by the differential receiver.
A differential receiver circuit is used in high-speed communication systems to detect and process differential signals, which are less susceptible to noise and interference compared to single-ended signals. A key challenge in such systems is minimizing the time taken for the receiver to transition between states, known as the state-transition period, which can degrade performance and increase power consumption. This transition period occurs when the receiver detects a change in the input signal, such as a rising or falling edge. The invention describes an apparatus that includes a differential receiver and a transceiver circuit. The transceiver circuit is configured to detect the signal edge of the input signal and respond by actively reducing the state-transition period of the differential receiver. This is achieved through techniques such as adaptive biasing, dynamic threshold adjustment, or pre-emphasis, which optimize the receiver's response time. By minimizing the state-transition period, the apparatus improves signal integrity, reduces latency, and enhances overall system efficiency. The invention is particularly useful in high-speed data transmission applications, such as serial communication interfaces, where rapid and accurate signal detection is critical. The transceiver circuit may also include additional features, such as error correction or signal conditioning, to further enhance performance.
Unknown
April 7, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.