Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: a controller for a memory device, the controller configured to: set up a data path between the controller and the memory device to initialize an open mode; perform a plurality of program operations on the memory device in the open mode using the set up data path; and in response to exiting the open mode, perform a garbage collection operation on the memory device, wherein: the controller exits the open mode in response to a counter being incremented to a predetermined value, and the counter is incremented in response to the controller performing each program operation of the plurality of program operations.
This invention relates to memory device management, specifically optimizing garbage collection in memory controllers. The problem addressed is inefficient garbage collection in memory systems, which can lead to performance degradation and reduced lifespan of memory devices. The invention provides an apparatus with a memory controller that manages garbage collection based on program operation counts. The memory controller sets up a data path to initialize an open mode, allowing multiple program operations to be performed on the memory device. During open mode, the controller increments a counter for each program operation executed. Once the counter reaches a predetermined threshold, the controller exits open mode and triggers a garbage collection operation. This ensures garbage collection occurs at regular intervals based on program activity, rather than arbitrary or fixed schedules, improving efficiency and system performance. The invention also includes mechanisms to handle the transition between open and non-open modes seamlessly, ensuring data integrity and minimizing disruptions. This approach optimizes memory management by aligning garbage collection with actual usage patterns, reducing unnecessary operations and extending the lifespan of the memory device.
2. The apparatus of claim 1 , wherein the controller is configured to perform the plurality of program operations without interruption for a garbage collection operation.
A system for managing memory operations in a computing device includes a controller that executes multiple program operations without interruption for garbage collection. The system addresses the problem of performance degradation caused by frequent garbage collection pauses in memory management, which disrupts ongoing operations and reduces efficiency. The controller is designed to handle memory allocation and deallocation while ensuring that program execution continues uninterrupted, maintaining system responsiveness and throughput. This is achieved through optimized memory management techniques that minimize or eliminate the need for traditional garbage collection pauses. The system is particularly useful in environments where low-latency and high-performance computing are critical, such as real-time applications, embedded systems, or high-frequency trading platforms. By avoiding interruptions from garbage collection, the system ensures consistent performance and reliability, improving overall system efficiency and user experience. The controller may employ advanced algorithms or hardware-assisted mechanisms to dynamically manage memory without causing delays, ensuring seamless operation of concurrent processes.
3. The apparatus of claim 1 , wherein the controller is configured to exit the open mode in response to a trigger event, the trigger event comprising one or more of: an amount of data stored by a single level cell (SLC) block satisfying a threshold; an amount of data being accumulated for the garbage collection operation satisfying a threshold; and a failure of one or more of the plurality of program operations.
This invention relates to a data storage apparatus, specifically a controller for managing memory operations in a solid-state storage device. The problem addressed is optimizing data storage efficiency and reliability by dynamically adjusting operational modes based on system conditions. The apparatus includes a controller that operates in an open mode, where data is written to a single-level cell (SLC) block without immediate garbage collection. The controller monitors system conditions and exits the open mode in response to a trigger event. These trigger events include: the amount of data stored in the SLC block reaching a predefined threshold, the accumulated data for garbage collection reaching a threshold, or a failure in one or more program operations. When triggered, the controller transitions to a different mode, such as performing garbage collection or error recovery, to maintain storage efficiency and reliability. The system ensures that data is managed efficiently while preventing excessive wear or errors in the storage medium.
4. The apparatus of claim 3 , wherein the SLC block comprises one or more of a host write block and a fold destination block.
The invention relates to data storage systems, specifically solid-state drives (SSDs) using single-level cell (SLC) blocks for improved performance and endurance. The problem addressed is optimizing data management in SLC blocks to enhance write efficiency and longevity. The apparatus includes an SLC block that can function as either a host write block or a fold destination block. As a host write block, it directly receives and stores data from a host system, improving write speeds. As a fold destination block, it consolidates data from multiple pages in a multi-level cell (MLC) or triple-level cell (TLC) block, reducing write amplification and extending the lifespan of the storage device. The SLC block dynamically switches between these roles based on system demands, ensuring efficient data handling. This dual functionality allows the storage system to balance performance and endurance, addressing the trade-offs between fast writes and long-term reliability in flash memory. The apparatus may also include a controller to manage the SLC block's role transitions and data movement, ensuring seamless operation. This design is particularly useful in high-performance storage applications where both speed and durability are critical.
5. The apparatus of claim 3 , wherein, in response to the trigger event comprising the amount of data stored by the SLC block satisfying the threshold, the controller is configured to one of: perform an erase operation on the SLC block and write new program data to the SLC block; and perform an exchange operation to transfer valid program data stored in the SLC block to a different SLC block and write new program data to the SLC block.
This invention relates to data storage systems, specifically solid-state drives (SSDs) using single-level cell (SLC) blocks for high-speed data handling. The problem addressed is managing data storage and retrieval efficiency in SLC blocks, particularly when the stored data reaches a predefined threshold. The apparatus includes a controller and at least one SLC block. The controller monitors the amount of data stored in the SLC block and triggers an action when the stored data meets or exceeds a threshold. Upon triggering, the controller either performs an erase operation on the SLC block followed by writing new program data or executes an exchange operation. The exchange operation involves transferring valid program data from the SLC block to a different SLC block before writing new program data to the original SLC block. This ensures efficient data management, preventing performance degradation due to excessive data accumulation in the SLC block while maintaining data integrity. The invention optimizes storage operations by dynamically handling data based on storage thresholds, improving overall SSD performance and reliability.
6. The apparatus of claim 3 , wherein the failure comprises a program failure for a folding operation.
A system for detecting and handling failures in a folding operation within a computing environment. The folding operation involves processing data to transform it into a compact or reduced form, often used in machine learning, data compression, or signal processing. The system monitors the execution of the folding operation to identify failures, such as errors in computation, data corruption, or resource exhaustion. When a failure is detected, the system triggers a corrective action, such as retrying the operation, rolling back to a previous state, or alerting an operator. The system may also log failure details for analysis and improvement. The failure detection mechanism includes checks for invalid outputs, excessive processing time, or system resource limits. The corrective actions are tailored to the type of failure, ensuring system stability and data integrity. This approach enhances reliability in applications where folding operations are critical, such as in neural network training or data preprocessing pipelines.
7. The apparatus of claim 1 , wherein, during the open mode, the controller is configured to: receive program commands from a host computing device in communication with the controller; and accumulate, in a command queue, a plurality of program commands received from the host computing device.
This invention relates to a data storage apparatus with a controller that manages program commands in an open mode. The apparatus includes a non-volatile memory array and a controller that operates in at least an open mode and a closed mode. In the open mode, the controller receives program commands from a host computing device and accumulates them in a command queue. The controller processes these commands to write data to the non-volatile memory array. The apparatus may also include a volatile memory buffer for temporary data storage and a wear-leveling module to distribute write operations evenly across the memory array. The controller may further include a command parser to interpret received commands and a data encoder to prepare data for storage. The invention aims to improve efficiency and reliability in data storage operations by managing command accumulation and processing in a structured manner. The closed mode may involve finalizing pending operations or entering a low-power state. The apparatus is designed for use in solid-state storage systems, such as SSDs, where efficient command handling is critical for performance.
8. The apparatus of claim 7 , further comprising a set of memory latches for the memory device, wherein: the program commands include program data; and during the open mode, the controller is configured to, in response to the command queue accumulating at least a predetermined quantity of program commands, transmit the program data for the accumulated plurality of program commands to one or more memory latches of the set of memory latches.
A memory storage apparatus includes a controller and a memory device, where the controller manages data storage operations by executing program commands. The apparatus operates in an open mode, allowing continuous data transmission to the memory device without requiring a separate command for each data transfer. The controller accumulates program commands in a command queue and, when the queue reaches a predetermined quantity of commands, transmits the associated program data to memory latches in the memory device. These latches temporarily store the data before it is written to the memory. The apparatus optimizes data transfer efficiency by reducing the overhead of individual command transmissions, particularly in high-throughput storage environments. The memory latches act as an intermediate buffer, enabling faster data processing and minimizing latency during write operations. This design is particularly useful in systems requiring rapid and continuous data storage, such as solid-state drives or other high-performance memory systems. The controller dynamically adjusts data transmission based on the accumulated command queue, ensuring efficient use of memory resources while maintaining data integrity.
9. The apparatus of claim 8 , wherein, during the open mode, the controller is configured to accumulate the transferred program data in the one or more memory latches until a memory latch of the one or more memory latches is one of full and includes at least a latch threshold amount of program data.
This invention relates to a data transfer apparatus designed to optimize the handling of program data in a computing system. The apparatus includes a controller and one or more memory latches that facilitate the transfer of program data between components. The controller manages the transfer process, ensuring data is efficiently stored and processed. In an open mode, the controller accumulates transferred program data in the memory latches until a latch reaches a specific condition: either it is completely full or contains at least a predefined threshold amount of data. This approach prevents inefficient transfers by ensuring data is only processed in meaningful batches, reducing overhead and improving system performance. The apparatus may also include a data transfer interface that connects to a host system, allowing the controller to receive and distribute program data as needed. The memory latches serve as temporary storage buffers, holding data until it is ready for further processing or transfer. The controller monitors the latch status and triggers actions based on the fill level, ensuring optimal data handling. This design is particularly useful in systems where data transfer efficiency is critical, such as in high-performance computing or embedded systems.
10. The apparatus of claim 9 , wherein: the controller further comprises a flash translation layer (FTL) configured to track program data stored in the one or more memory latches; and during the open mode, the controller is configured to: write the program data to the memory device in response to the memory latch being the one of full and including greater than or equal to the latch threshold amount of program data, and update the FTL in response to writing the program data to the memory device.
This invention relates to a memory storage apparatus designed to improve data handling efficiency in non-volatile memory systems, particularly during open mode operations where data is temporarily stored in memory latches before being written to the main memory device. The apparatus includes a controller with a flash translation layer (FTL) that tracks program data stored in one or more memory latches. The FTL manages the mapping and organization of data within the memory system, ensuring efficient storage and retrieval. During open mode, the controller monitors the memory latches and writes program data to the memory device when a latch reaches a full state or contains an amount of data equal to or exceeding a predefined latch threshold. This write operation is followed by an update to the FTL to reflect the new data placement. The system optimizes data transfer by minimizing unnecessary writes and maintaining accurate data tracking, enhancing overall performance and reliability in memory operations. The apparatus is particularly useful in systems requiring efficient data management, such as solid-state drives (SSDs) and other flash-based storage solutions.
11. The apparatus of claim 8 , wherein the program data is continuously transmitted to the one or more memory latches.
A system for managing program data in a memory device includes a controller that continuously transmits program data to one or more memory latches. The memory latches temporarily store the data before it is written to a non-volatile memory array, such as NAND flash memory. The continuous transmission ensures that data is efficiently buffered and reduces latency in the write process. The controller may also include error correction mechanisms to verify data integrity during transmission. The system is designed to improve write performance and reliability in storage devices by minimizing delays between data reception and storage. The memory latches act as an intermediate buffer, allowing the controller to handle high-speed data streams while maintaining data accuracy. This approach is particularly useful in high-performance storage applications where low latency and high throughput are critical. The continuous transmission method ensures that data is consistently available for writing, reducing the risk of data loss or corruption during operation. The system may also include additional features such as dynamic latch allocation to optimize memory usage and adaptive error correction based on detected transmission errors.
12. The apparatus of claim 1 , wherein the controller is further configured to: set up a new data path between the controller and the memory device to reinitialize the open mode; and perform an additional plurality of program operations on the memory device in the reinitialized open mode using the new data path.
This invention relates to memory systems, specifically addressing the challenge of maintaining efficient data operations in non-volatile memory devices, such as flash memory, during extended use. The apparatus includes a controller and a memory device, where the controller manages data operations like programming and erasing. The invention focuses on reinitializing an "open mode" to optimize performance. Open mode refers to a state where a memory block remains partially programmed, allowing for subsequent data writes without full erasure. Over time, this mode may degrade, leading to inefficiencies. The controller detects such degradation and establishes a new data path to reinitialize the open mode, ensuring optimal performance. After reinitialization, the controller performs additional program operations in the refreshed open mode, maintaining high-speed data handling. This approach extends the lifespan of the memory device by reducing unnecessary erasures and write cycles, while improving reliability and speed. The solution is particularly useful in systems requiring frequent data updates, such as solid-state drives or embedded storage. By dynamically reinitializing the open mode, the apparatus ensures consistent performance without manual intervention.
13. A system comprising: a memory device, comprising: a memory array of memory elements; and a set of memory latches for the memory array; and a controller including a controller memory, the controller in communication with a host computing device and configured to: receive memory commands including program data from the host computing device; transmit the program data to one or more memory latches of the set of memory latches in a streaming write mode; and in response to detecting a program failure for a folding operation: exit the streaming write mode; and in response to exiting the streaming write mode, perform a garbage collection operation on the memory array.
The system relates to memory storage devices, specifically addressing the challenge of handling program failures during data writing operations in non-volatile memory systems. The system includes a memory device with a memory array of memory elements and a set of memory latches for storing data before it is written to the memory array. A controller, connected to a host computing device, manages memory operations. The controller receives memory commands and program data from the host, then streams the data to the memory latches in a streaming write mode, which allows for continuous data transfer without interruption. If a program failure occurs during a folding operation—a process where data is moved or consolidated within the memory—the controller exits the streaming write mode. Upon exiting, the controller performs a garbage collection operation on the memory array. Garbage collection involves reclaiming unused or invalid data blocks to maintain efficient storage utilization. This system ensures data integrity and system reliability by dynamically responding to program failures and optimizing memory management through automated garbage collection.
14. The system of claim 13 , wherein: the controller is further configured to: in response to exiting the streaming write mode, pause transmitting the program data to the one or more memory latches in the streaming write mode, and in response to completing the garbage collection operation: set up a data path between the controller and the set of memory latches, and resume transmitting the program data to the one or more memory latches in the streaming write mode.
This invention relates to a memory system with improved data handling during garbage collection operations. The system includes a controller and a set of memory latches used for streaming write operations, where data is continuously transmitted to the latches in a high-speed mode. The controller manages the data flow to optimize performance during background garbage collection, a process where invalid or obsolete data is consolidated to free up storage space. When garbage collection begins, the controller pauses the streaming write mode to prevent data corruption or conflicts. Once garbage collection is complete, the controller re-establishes the data path between itself and the memory latches, then resumes the streaming write mode, ensuring seamless data transmission without interruption. This approach maintains high write speeds while allowing background maintenance tasks to proceed efficiently. The system is particularly useful in high-performance storage devices where uninterrupted data flow is critical.
15. The system of claim 14 , wherein: the program data is continuously transmitted to the one or more memory latches; and in response to a memory latch in the one or more memory latches being one of full and including at least a predetermined latch amount of the program data, the controller is further configured to write the program data in the memory latch to the memory array.
This invention relates to a data storage system designed to improve the efficiency of writing program data to a memory array. The system addresses the challenge of managing data flow between a controller and memory latches, ensuring timely and efficient data transfer to the memory array. The system includes a controller, one or more memory latches, and a memory array. The controller receives program data and continuously transmits it to the memory latches. Each memory latch temporarily stores the program data until it reaches a full state or contains at least a predetermined amount of data. Once either condition is met, the controller writes the data from the latch to the memory array. This approach optimizes data handling by reducing unnecessary write operations and ensuring efficient use of memory resources. The system may also include additional features such as error detection and correction mechanisms to enhance data integrity during transmission and storage. The continuous transmission and conditional writing process ensures that data is processed in a streamlined manner, minimizing delays and improving overall system performance.
16. The system of claim 13 , wherein: the controller is configured to exit the streaming write mode in response to a counter being incremented to a predetermined value; and the counter is incremented in response to the controller transmitting the program data to the one or more memory latches of the set of memory latches.
This invention relates to a memory system with a controller that manages data streaming and write operations. The system addresses the challenge of efficiently handling data writes in memory devices, particularly in scenarios where continuous data streaming is required. The controller operates in a streaming write mode, where it transmits program data to a set of memory latches. To ensure controlled and orderly data processing, the controller increments a counter each time it sends data to the memory latches. Once the counter reaches a predetermined value, the controller exits the streaming write mode, preventing excessive or uncontrolled data writes. This mechanism helps maintain system stability and prevents memory overflow or corruption. The system may also include additional features, such as error detection and correction, to further enhance reliability. The invention is particularly useful in high-performance memory applications where data integrity and efficient write operations are critical.
17. An apparatus comprising: means for transmitting program data to one or more memory latches of a set of memory latches for a memory array in an open mode; means for exiting the open mode in response to detecting one or more trigger events; and means for performing a garbage collection operation on the memory array in response to exiting the open mode, wherein: the open mode is exited in response to a counter being incremented to a predetermined value, and the counter is incremented in response to each program operation of the plurality of program operations being performed.
This invention relates to memory management in non-volatile storage systems, specifically addressing the challenge of efficiently handling program operations and maintaining data integrity in memory arrays. The apparatus includes a mechanism for transmitting program data to one or more memory latches within a set of memory latches associated with a memory array while operating in an open mode. The open mode allows for continuous or batch program operations without immediate garbage collection, improving write performance. The system monitors program operations and increments a counter for each operation performed. When the counter reaches a predetermined threshold, a trigger event is detected, causing the apparatus to exit the open mode. Upon exiting, a garbage collection operation is automatically initiated to reclaim unused or invalid memory space, ensuring efficient memory utilization and preventing fragmentation. The garbage collection process may involve consolidating valid data, erasing obsolete blocks, and preparing the memory array for subsequent write operations. This approach balances performance and storage efficiency by deferring garbage collection until necessary, triggered by program operation frequency rather than fixed time intervals or external commands. The invention is particularly useful in flash memory systems where frequent writes can degrade performance if garbage collection is not managed intelligently.
18. The apparatus of claim 17 , further comprising means for detecting the one or more trigger events, wherein the one or more trigger events comprise one or more of: a single level cell (SLC) host write block being one of full and including at least a host write threshold amount of program data; an SLC fold destination block being one of full and including at least a fold destination threshold amount of program data; program data subject to the garbage collection operation being accumulated to at least a garbage collection threshold amount; and a program operation failure.
This invention relates to data storage systems, specifically managing data in single-level cell (SLC) memory blocks. The problem addressed is inefficient data handling in SLC memory, which can lead to performance degradation, increased wear, and operational failures. The apparatus includes a controller that performs garbage collection operations to reclaim storage space by relocating valid data from partially filled blocks to more efficiently utilized blocks. The invention further includes a mechanism to detect specific trigger events that initiate these garbage collection operations. These trigger events include an SLC host write block being full or containing at least a predefined host write threshold of program data, an SLC fold destination block being full or containing at least a fold destination threshold of program data, program data subject to garbage collection accumulating to at least a garbage collection threshold, or a program operation failure. By monitoring these conditions, the system ensures timely and efficient garbage collection, optimizing storage utilization and reducing wear on the memory cells. The apparatus dynamically adjusts operations based on these triggers to maintain performance and reliability in the storage system.
19. The apparatus of claim 17 , wherein the one or more trigger events comprises at least a predetermined quantity of program data writes being performed on the memory array, the apparatus further comprising: means for pausing transmission of the program data to the one or more memory latches in response to exiting the open mode; means for setting up a data path between the means for transmitting and the set of memory latches in response to completing the garbage collection operation; and means for resuming transmission of the program data to the one or more memory latches in response to setting up the data path.
This invention relates to memory systems, specifically managing data transmission during garbage collection operations in non-volatile memory arrays. The problem addressed is ensuring efficient data handling when performing garbage collection, which involves reclaiming storage space by consolidating valid data and discarding obsolete data. The invention provides an apparatus that includes a memory array and a controller configured to manage data transmission during garbage collection. The apparatus monitors trigger events, such as a predetermined number of program data writes to the memory array. When a trigger event occurs, the apparatus exits an open mode, pauses data transmission to memory latches, and initiates garbage collection. After completing garbage collection, the apparatus sets up a data path between the transmission means and the memory latches, then resumes data transmission. This ensures that data transmission is temporarily halted during garbage collection to prevent interference, improving the reliability and efficiency of the memory system. The apparatus may also include additional means for transmitting program data to the memory latches and for managing the data path setup. The invention optimizes memory operations by coordinating data transmission with garbage collection processes.
20. The apparatus of claim 17 , further comprising means for detecting a trigger event, wherein: the trigger event comprises one or more of: an amount of data stored by a single level cell block satisfying a threshold, an amount of data being accumulated for the garbage collection operation satisfying a threshold, and a failure of one or more program operations; and the failure comprises a program failure for a folding operation.
This invention relates to data storage systems, specifically managing data in single-level cell (SLC) blocks within a memory device. The problem addressed is inefficient garbage collection and program operation failures, which can degrade performance and reliability. The apparatus includes a mechanism to detect trigger events that initiate garbage collection or other corrective actions. These trigger events include when the amount of data stored in an SLC block reaches a predefined threshold, when the accumulated data for garbage collection meets a threshold, or when a program operation fails. The failure specifically includes a program failure during a folding operation, where data is moved or consolidated within the memory. The apparatus ensures timely and efficient data management by monitoring these conditions and responding accordingly, improving system reliability and performance. The solution helps prevent data loss and reduces unnecessary wear on the storage medium by proactively addressing storage thresholds and operation failures.
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April 28, 2020
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