Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A binary-to-gray conversion circuit, comprising: an input configured to receive a first binary signal; a register configured to store a second binary signal; a prediction circuit configured to receive the second binary signal and to provide a set of binary candidate values, wherein a respective Gray equivalent of each binary candidate value has a Hamming distance of one from a Gray equivalent of the second binary signal; an arbiter configured to select one of the binary candidate values as a function of the first binary signal and the second binary signal, wherein the selected binary candidate value is provided to the register; and an encoder block configured to receive the selected binary candidate value and output a Gray encoded equivalent of the selected binary candidate value.
This invention relates to digital logic circuits and specifically addresses the problem of efficiently converting binary signals to Gray code, particularly in scenarios where the input binary signal may be noisy or uncertain. The circuit includes an input for a first binary signal, which represents the potentially noisy or uncertain input. A register stores a second binary signal, which is a more stable or previously determined binary value. A prediction circuit takes the stored second binary signal and generates a set of candidate binary values. Each of these candidate values is designed such that its Gray code equivalent has a Hamming distance of only one from the Gray code equivalent of the stored second binary signal. An arbiter then selects one of these candidate binary values. This selection is based on both the first binary signal and the second binary signal, effectively using the first signal to refine or correct the second signal. The selected binary candidate value is then stored in the register, updating the stable binary value. Finally, an encoder block receives this selected binary candidate value and outputs its Gray encoded equivalent. This process allows for a robust conversion to Gray code, even with an imperfect initial binary input.
2. The circuit according to claim 1 , wherein the first binary signal, the second binary signal and the Gray encoded equivalent of the selected binary candidate value each have a given number k of bits, and the prediction circuit is configured to provide k binary candidate values.
A circuit is provided for processing binary signals in digital systems, addressing challenges in signal encoding and decoding, particularly in applications requiring efficient data representation and error resilience. The circuit includes a prediction circuit that generates multiple binary candidate values, each having a fixed bit length k. These candidate values are derived from a first binary signal and a second binary signal, both of which also have k bits. The prediction circuit is configured to produce k distinct binary candidate values, which are then compared to a Gray-encoded equivalent of a selected binary candidate value. Gray encoding is used to minimize bit errors during transmission or storage by ensuring that only one bit changes between consecutive values. The circuit leverages this property to improve reliability in digital communication or storage systems. The first and second binary signals may represent input data or intermediate values in a processing pipeline, while the Gray-encoded equivalent serves as a reference for validation or further processing. This approach enhances data integrity and reduces the likelihood of misinterpretation due to bit flips, making it suitable for high-reliability applications such as aerospace, automotive, or industrial control systems. The fixed bit length k ensures compatibility with standard digital interfaces and simplifies hardware implementation.
3. The circuit according to claim 2 , wherein the prediction circuit comprises k sub-circuits, each configured to provide at output an i-th binary candidate value, with i=1 . . . k.
A circuit is disclosed for generating binary candidate values in a prediction system. The circuit includes a prediction circuit that produces multiple binary outputs based on input data. The prediction circuit comprises k sub-circuits, each generating a distinct binary candidate value. These sub-circuits operate in parallel, with each sub-circuit producing an individual binary output, labeled as the i-th binary candidate value, where i ranges from 1 to k. The sub-circuits may be configured to evaluate different conditions or patterns in the input data to generate diverse candidate values, improving prediction accuracy. The circuit may be part of a larger system for data processing, machine learning, or decision-making, where multiple candidate predictions are evaluated to select an optimal outcome. The use of multiple sub-circuits allows for parallel processing, reducing latency and increasing throughput. The circuit may also include additional components, such as a selection circuit, to choose the most appropriate binary candidate value based on predefined criteria or further analysis. This design enhances flexibility and adaptability in prediction tasks by providing multiple potential outputs for evaluation.
4. The circuit according to claim 3 , wherein the prediction circuit comprises a first circuit configured to receive the second binary signal and to provide a first signal by computing the difference between (2 k −1) and the value of the second binary signal.
A digital circuit is provided for processing binary signals in a predictive coding system, addressing the need for efficient signal prediction to reduce computational complexity and power consumption. The circuit includes a prediction module that generates a predicted value based on a received binary input signal. The prediction module contains a subtraction circuit that computes the difference between a predefined constant (2^k - 1), where k is an integer, and the value of the input binary signal. This operation produces an intermediate signal used for further processing, such as error calculation or signal reconstruction. The circuit may also include additional components for signal conditioning, such as a second circuit that converts the intermediate signal into a format suitable for downstream operations. The system is designed to optimize predictive accuracy while minimizing hardware resources, making it suitable for applications in data compression, communication systems, and signal processing. The use of a fixed constant (2^k - 1) ensures deterministic behavior, simplifying implementation and verification. The overall design focuses on reducing latency and power consumption in digital signal prediction tasks.
5. The circuit according to claim 4 , wherein each the sub-circuit comprises: an input configured to receive the second binary signal; a second circuit configured to generate a second signal by selecting the (k−i) most significant bits of the second binary signal; a third circuit configured generate a third signal by selecting the i least significant bits of the first signal; and a fourth circuit configured to generate the respective binary candidate value by combining the second signal and the third signal.
This invention relates to digital signal processing circuits, specifically for generating binary candidate values from input signals. The problem addressed is efficiently extracting and combining specific bit segments from binary signals to produce intermediate values for further processing, such as in digital filtering or arithmetic operations. The circuit includes multiple sub-circuits, each receiving a second binary signal. Within each sub-circuit, an input receives the second binary signal. A second circuit extracts the (k−i) most significant bits (MSBs) from this signal, generating a second signal. A third circuit extracts the i least significant bits (LSBs) from a first binary signal, generating a third signal. A fourth circuit combines these two signals to produce a binary candidate value. The first binary signal is derived from a prior stage, where a first circuit generates it by selecting the (k−i) MSBs of an initial binary signal. This modular approach allows flexible bit manipulation for applications requiring partial bit extraction and recombination, such as in digital signal processing pipelines or arithmetic logic units. The design ensures precise bit selection and combination without full signal conversion, optimizing performance in high-speed digital systems.
6. The circuit according to claim 3 , wherein the prediction circuit comprises a first circuit configured to receive the second binary signal and to provide a first signal by inverting the bits of the second binary signal.
A digital circuit is provided for processing binary signals, particularly in applications requiring bit inversion. The circuit includes a prediction circuit that generates a predicted output based on an input binary signal. The prediction circuit contains a first sub-circuit designed to receive a second binary signal and produce a first output signal by inverting each bit of the second binary signal. This inversion operation is performed to transform the input signal into its logical complement, which may be useful in error correction, data encoding, or signal processing tasks. The circuit may also include additional components to further process the inverted signal or combine it with other signals for enhanced functionality. The overall system is optimized for efficient bit manipulation, ensuring accurate and reliable signal transformation in digital systems.
7. The circuit according to claim 6 , wherein each the sub-circuit comprises: an input configured to receive the second binary signal; a second circuit configured to generate a second signal by selecting the (k−i) most significant bits of the second binary signal; a third circuit configured generate a third signal by selecting the i least significant bits of the first signal; and a fourth circuit configured to generate the respective binary candidate value by combining the second signal and the third signal.
This invention relates to digital signal processing, specifically to a circuit for generating binary candidate values from input signals. The problem addressed is efficiently extracting and combining specific bit segments from binary signals to produce intermediate values for further processing, such as in digital filtering or signal reconstruction. The circuit includes multiple sub-circuits, each receiving a second binary signal and a first binary signal. Each sub-circuit processes these signals to generate a binary candidate value. The sub-circuit first selects the (k−i) most significant bits (MSBs) from the second binary signal, producing a second signal. Simultaneously, it selects the i least significant bits (LSBs) from the first binary signal, generating a third signal. These two signals are then combined to form the binary candidate value. This approach allows for flexible bit manipulation, enabling precise control over signal segmentation and recombination, which is useful in applications requiring bit-level precision, such as digital signal filtering or error correction. The circuit's modular design ensures scalability, allowing integration into larger systems where multiple sub-circuits operate in parallel. The selection and combination of specific bit segments enhance processing efficiency by reducing redundant computations and optimizing data flow. This method is particularly advantageous in high-speed digital systems where rapid and accurate bit manipulation is critical.
8. The circuit according to claim 1 , wherein the arbiter is associated with a preprocessing circuit configured to select the binary candidate values of the set of binary candidate values that are between the value of the second binary signal and the value of the first binary signal, the value of the second binary signal representing a lower limit and the value of the first binary signal representing an upper limit or target value.
This invention relates to digital circuits, specifically to an arbiter circuit with a preprocessing stage for selecting binary candidate values within a defined range. The problem addressed is efficiently narrowing down a set of binary candidate values to those that fall between a lower limit and an upper limit or target value, improving decision-making in digital systems. The circuit includes an arbiter that receives a set of binary candidate values and selects one based on predefined criteria. A preprocessing circuit is associated with the arbiter to filter the candidate values before arbitration. The preprocessing circuit compares each candidate value against a first binary signal (representing an upper limit or target) and a second binary signal (representing a lower limit). Only values between these two limits are passed to the arbiter for further processing. This reduces the number of candidates the arbiter must evaluate, improving efficiency and speed. The preprocessing circuit ensures that only relevant binary values are considered, which is particularly useful in applications requiring rapid decision-making, such as digital signal processing, data sorting, or control systems. By filtering candidates early, the overall system performance is enhanced. The invention may be applied in various digital logic designs where range-based selection of binary values is required.
9. The circuit according to claim 8 , wherein the preprocessing circuit comprises, for each binary candidate value, a respective out-of-range circuit, each configured to generate a respective mask signal indicating whether the respective binary candidate value is between the lower and the upper limit.
A digital circuit is provided for processing binary candidate values to determine whether they fall within predefined lower and upper limits. The circuit includes a preprocessing stage that evaluates each binary candidate value against these limits. For each candidate value, a dedicated out-of-range circuit generates a mask signal indicating whether the value is within the specified range. This mask signal can be used to filter or flag values that fall outside the acceptable bounds, ensuring only valid data is processed further. The preprocessing stage may also include additional circuits to normalize or adjust the candidate values before range checking. The overall system is designed to efficiently validate binary data in applications where strict range constraints are required, such as digital signal processing, data validation, or control systems. The out-of-range detection is performed in parallel for multiple candidate values, improving processing speed and reducing latency. The circuit may be implemented in hardware, such as an ASIC or FPGA, or as part of a larger integrated system. The range-checking mechanism ensures data integrity by rejecting or flagging values that do not meet specified criteria, enhancing reliability in critical applications.
10. The circuit according to claim 9 , wherein the arbiter is configured to disregard binary candidate values having a respective mask signal indicating that the respective binary candidate value is not between the lower and the upper limit.
A circuit for processing binary candidate values includes an arbiter that selects a final binary value from multiple candidate values based on predefined criteria. The circuit operates in a domain where multiple binary values are generated, and there is a need to select the most appropriate value while ensuring it falls within specified bounds. The circuit receives binary candidate values and corresponding mask signals, where each mask signal indicates whether the candidate value is within a defined range between a lower and upper limit. The arbiter evaluates these mask signals and disregards any candidate values that do not meet the range criteria, ensuring only valid values are considered. This filtering step prevents invalid or out-of-range values from being selected, improving the reliability of the final output. The circuit may also include a comparator to determine the final binary value based on additional criteria, such as the highest or lowest valid candidate value. The overall system ensures that the selected binary value is both optimal and within acceptable bounds, addressing challenges in systems where multiple candidate values are generated but only those within a specific range are valid.
11. The circuit according to claim 9 , wherein the arbiter is configured to disregard the binary candidate values having a distance from the second binary signal that is greater than a given maximum distance.
A circuit for processing binary signals includes an arbiter that evaluates candidate binary values to determine a final output. The circuit receives a first binary signal and generates a second binary signal based on the first signal. The arbiter compares the second binary signal to multiple binary candidate values, calculating a distance metric for each comparison. The arbiter selects the candidate value with the smallest distance to the second binary signal as the final output. To improve efficiency, the arbiter is configured to disregard any candidate values that exceed a predefined maximum distance threshold from the second binary signal. This filtering step reduces computational overhead by eliminating unlikely candidates early in the evaluation process. The circuit is particularly useful in applications requiring fast and accurate binary signal processing, such as digital communication systems, error correction, or signal reconstruction, where minimizing processing time and resource usage is critical. The maximum distance threshold ensures that only relevant candidates are considered, improving both speed and accuracy of the final output.
12. The circuit according to claim 1 , wherein the arbiter is configured to select the binary candidate value having the greatest value.
A circuit includes an arbiter that selects a binary candidate value from multiple candidate values. The arbiter is specifically configured to choose the binary candidate value with the greatest value among the available options. This selection process ensures that the highest-value binary candidate is prioritized in the circuit's operation. The circuit may be part of a larger system where multiple candidate values are generated, and the arbiter determines which one to use based on their relative magnitudes. The selection mechanism is designed to optimize performance by consistently choosing the highest-value option, which could be critical in applications requiring precise or efficient decision-making. The arbiter's function is to compare the candidate values and output the one with the greatest magnitude, ensuring the circuit operates with the most favorable input. This approach may be used in digital signal processing, data routing, or other systems where value-based selection is necessary. The circuit's design ensures reliability and accuracy in selecting the optimal binary candidate value.
13. The circuit according to claim 1 , wherein the arbiter is implemented with a combinational logic circuit.
A circuit for managing data transfer between multiple data sources and a shared resource includes an arbiter that resolves conflicts when multiple sources attempt simultaneous access. The arbiter is implemented using a combinational logic circuit, which processes input signals from the data sources without internal memory or feedback loops, ensuring fast and deterministic decision-making. The combinational logic evaluates priority rules or other criteria to grant access to one source while denying others, preventing data collisions. This approach eliminates the need for sequential logic, reducing latency and power consumption. The circuit may also include a multiplexer that routes data from the selected source to the shared resource, ensuring efficient and conflict-free operation. The combinational logic arbiter is particularly suited for high-speed applications where low-latency arbitration is critical, such as in network switches, memory controllers, or multi-core processors. By using combinational logic, the circuit achieves predictable performance and simplifies design verification.
14. A FIFO memory comprising: a memory area comprising a plurality of memory locations; a write interface configured to generate a binary write pointer indicating a memory location for writing data to the memory area; a read interface configured to generate a binary read pointer indicating a memory location for reading data from the memory area; a synchronization circuit configured to exchange the binary write pointer or the binary read pointer between the write interface and the read interface, wherein the synchronization circuit is configured to exchange Gray coded signals; and a binary-to-gray conversion circuit configured to receive the binary write pointer or the binary read pointer, wherein a Gray encoded equivalent of a binary candidate value determined by the Binary-to-Gray conversion circuit is provided to the synchronization circuit.
A FIFO (First-In-First-Out) memory system addresses synchronization challenges between write and read interfaces operating in different clock domains. The memory includes a memory area with multiple locations, a write interface generating a binary write pointer to indicate where data should be written, and a read interface generating a binary read pointer to indicate where data should be read. A synchronization circuit facilitates communication between the write and read interfaces by exchanging the binary write or read pointers. To prevent synchronization errors, the system uses Gray-coded signals, which minimize glitches during transitions. A binary-to-Gray conversion circuit converts the binary write or read pointer into its Gray-coded equivalent before transmission via the synchronization circuit. This ensures reliable pointer exchange between asynchronous clock domains, preventing metastability and data corruption. The system efficiently manages data flow in high-speed or multi-domain applications where clock synchronization is critical.
15. The FIFO memory according to claim 14 , wherein the binary-to-gray conversion circuit comprises: a register configured to store a second binary signal; a prediction circuit configured to receive the second binary signal and to provide a set of binary candidate values, wherein a respective Gray equivalent of each binary candidate value has a Hamming distance of one from a Gray equivalent of the second binary signal; an arbiter configured to select one of the binary candidate values as a function of a first binary signal and the second binary signal, wherein the first binary signal is the binary write pointer or the binary read pointer and wherein the selected binary candidate value is provided to the register; and an encoder block configured to receive the selected binary candidate value and output a Gray encoded equivalent of the selected binary candidate value.
A FIFO (First-In-First-Out) memory system includes a binary-to-Gray conversion circuit designed to reduce power consumption by minimizing bit transitions during pointer updates. The circuit converts binary pointer values into Gray code, where adjacent values differ by only one bit, reducing dynamic power in digital circuits. The conversion circuit includes a register storing a second binary signal, which represents a previous pointer value. A prediction circuit generates a set of binary candidate values, each having a Gray equivalent with a Hamming distance of one from the Gray equivalent of the second binary signal. An arbiter selects one of these candidate values based on a first binary signal (either the binary write or read pointer) and the second binary signal, ensuring the selected value transitions efficiently. The selected candidate value is stored in the register and encoded into its Gray equivalent by an encoder block, which outputs the final Gray-coded pointer. This design optimizes pointer updates by minimizing bit transitions, improving energy efficiency in FIFO memory operations.
16. A method of performing a Binary-to-Gray conversion, the method comprising: receiving a first binary signal representing a target value; storing a second binary signal in a register; determining a set of binary candidate values, wherein the Gray equivalent of each respective binary candidate value has a Hamming distance of one from the Gray equivalent of the second binary value; selecting one of the binary candidate values as a function of the first binary signal and the second binary signal, wherein the selected binary candidate value is provided at input to the register; and generating an encoded signal by determining the Gray encoded equivalent of the selected binary candidate value.
This invention relates to digital signal processing, specifically a method for converting binary signals to Gray code. Gray code is a non-weighted binary encoding where adjacent values differ by only one bit, reducing errors in noisy environments. The method addresses the challenge of efficiently converting arbitrary binary values to Gray code while minimizing hardware complexity and latency. The method receives a first binary signal representing a target value and stores a second binary signal in a register. It then determines a set of binary candidate values, where each candidate's Gray equivalent has a Hamming distance of one from the Gray equivalent of the second binary signal. This ensures smooth transitions between consecutive values. One candidate is selected based on the first and second binary signals, and the selected value is fed back into the register. Finally, the method generates an encoded signal by converting the selected binary candidate into its Gray code equivalent. This approach leverages the properties of Gray code to ensure minimal bit changes during conversion, which is useful in applications like analog-to-digital conversion, error correction, and digital communication systems. The method efficiently narrows down candidate values to those with adjacent Gray code representations, optimizing the conversion process.
17. The method according to claim 16 , wherein the first binary signal, the second binary signal and the Gray encoded equivalent of the selected binary candidate value each have a given number k of bits, and the set of binary candidate values has the k binary candidate values.
This invention relates to digital signal processing, specifically methods for encoding and decoding binary signals using Gray code techniques. The problem addressed is the need for efficient and error-resistant binary encoding, particularly in applications where minimizing bit transitions is critical, such as in communication systems or digital control circuits. The method involves selecting a binary candidate value from a predefined set of k binary candidate values, where each candidate value is represented by a first binary signal and a second binary signal. The first binary signal is derived from the selected binary candidate value, while the second binary signal is derived from a Gray-encoded equivalent of the selected binary candidate value. Gray encoding ensures that only one bit changes between consecutive values, reducing errors during transmission or storage. The method further includes generating a combined signal by combining the first binary signal and the second binary signal. This combined signal can be used for further processing, such as error detection or correction, or for transmission over a communication channel. The use of Gray encoding in conjunction with the original binary representation provides robustness against bit errors while maintaining the integrity of the encoded data. The invention is particularly useful in applications requiring high reliability, such as aerospace systems, industrial control systems, or high-speed data transmission, where minimizing bit errors and ensuring data integrity are critical.
18. The method according to claim 16 , wherein selecting one of the binary candidate values comprises selecting the binary candidate values of the set of binary candidate values that are between the value of the second binary signal and the value of the first binary signal, the value of the second binary signal representing a lower limit and the value of the first binary signal representing an upper limit or target value.
This invention relates to a method for selecting binary candidate values within a defined range in a digital signal processing system. The method addresses the challenge of efficiently narrowing down binary values for further processing or decision-making in applications where precise value selection is critical, such as analog-to-digital conversion, signal filtering, or digital control systems. The method involves comparing a set of binary candidate values against two reference binary signals: a first binary signal representing an upper limit or target value and a second binary signal representing a lower limit. The selection process filters the candidate values to retain only those that fall within the range defined by these two signals. This ensures that only relevant values are processed, improving efficiency and accuracy in subsequent operations. The method is particularly useful in systems where binary signals are used to represent thresholds or boundaries, such as in digital comparators, level detectors, or adaptive filtering algorithms. By dynamically adjusting the selection criteria based on the reference signals, the method provides flexibility in handling varying input conditions while maintaining precise control over the selected values. This approach reduces computational overhead and enhances system performance by eliminating irrelevant data early in the processing pipeline.
19. The method according to claim 18 , further comprising, for each binary candidate value generating a respective mask signal indicating whether the respective binary candidate value is between the lower and the upper limit.
This invention relates to a method for processing binary candidate values within a defined range. The method addresses the challenge of efficiently determining whether each binary candidate value falls within a specified lower and upper limit. The process involves generating a mask signal for each binary candidate value, where the mask signal indicates whether the value lies between the predefined limits. This allows for rapid filtering or validation of binary data against boundary conditions. The method is particularly useful in digital signal processing, data validation, or real-time systems where quick comparisons against thresholds are required. The mask signal can be used to selectively enable or disable further processing steps based on whether the binary candidate value is within the acceptable range. The technique ensures accurate and efficient range checking without requiring iterative comparisons, improving computational efficiency. The invention builds on a prior method that involves generating binary candidate values and may include additional steps such as adjusting the values or applying transformations before the range-checking step. The mask signal generation is performed for each candidate value independently, allowing parallel processing and further optimization in hardware or software implementations. This approach is beneficial in applications where real-time performance and low-latency decision-making are critical.
20. The method according to claim 19 , further comprising disregarding binary candidate values having a respective mask signal indicating that the respective binary candidate value is not between the lower and the upper limit.
A method for processing binary candidate values in a digital system involves filtering these values based on predefined limits. The method operates within a domain where binary data must be validated against specified thresholds to ensure accuracy or compliance with system constraints. The core process includes comparing each binary candidate value against a lower and an upper limit to determine if it falls within an acceptable range. A mask signal associated with each binary candidate value indicates whether the value is valid or invalid. The method further includes disregarding any binary candidate values that have a mask signal indicating they are outside the specified range. This ensures that only valid data is processed, improving system reliability and efficiency. The method may be applied in digital signal processing, data validation, or error correction systems where strict adherence to defined limits is critical. By filtering out invalid values early, the system avoids unnecessary computations and potential errors, enhancing overall performance. The technique is particularly useful in applications requiring high precision, such as financial transactions, medical diagnostics, or industrial control systems.
21. The method according to claim 19 , further comprising disregarding the binary candidate values having a distance from the second binary signal that is greater than a given maximum distance.
This invention relates to signal processing, specifically methods for evaluating binary candidate values in relation to a second binary signal. The problem addressed is the need to efficiently and accurately filter or disregard binary candidate values that are too dissimilar from a reference binary signal, improving the reliability of signal analysis or comparison processes. The method involves comparing binary candidate values to a second binary signal and calculating a distance metric between them. The distance metric quantifies how dissimilar the binary candidate values are from the second binary signal. The method then filters out or disregards any binary candidate values where this distance exceeds a predefined maximum threshold. This ensures that only sufficiently similar binary candidate values are retained for further processing, reducing noise and improving the accuracy of subsequent operations. The method may be applied in various signal processing applications, such as error correction, pattern recognition, or data validation, where distinguishing between valid and invalid binary signals is critical. By enforcing a maximum distance threshold, the method helps maintain the integrity of the processed data, ensuring that only relevant or sufficiently accurate binary candidate values are considered. This filtering step enhances computational efficiency and reliability in systems that rely on binary signal comparisons.
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April 28, 2020
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