Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A system comprising: one or more clients; and a memory subsystem having a first ratio of active memory channels to total memory channels; wherein the memory subsystem is configured to: reduce the first ratio to a second ratio of a first number to a second number; receive a memory request from a client of the one or more clients; responsive to determining that a first subset of physical address bits of the memory request have a value that is greater than or equal to the first number: calculate a third number based on a value corresponding to a second subset of physical address bits modulo the first number; select a memory channel, of a plurality of memory channels, using a concatenation of the third number and a third subset of physical address bits; and complete the memory request to the selected memory channel.
This invention relates to memory subsystem management in computing systems, specifically addressing the challenge of efficiently utilizing memory channels to improve performance and reduce power consumption. The system includes one or more clients and a memory subsystem with a configurable ratio of active to total memory channels. Initially, the memory subsystem operates with a first ratio of active channels, which can be dynamically reduced to a second ratio (e.g., 1:2, 1:4, etc.) to conserve power or optimize performance. When a memory request is received from a client, the system checks the physical address bits. If a first subset of these bits meets or exceeds the first number (e.g., half the total channels), the system calculates a third number by taking the modulo of a second subset of address bits with the first number. This third number is concatenated with a third subset of address bits to select a specific memory channel. The request is then routed to this channel for completion. This approach ensures efficient channel selection while maintaining data integrity, particularly useful in systems requiring dynamic memory channel management. The invention optimizes memory access by dynamically adjusting active channels and intelligently distributing requests across available channels.
2. The system as recited in claim 1 , wherein responsive to determining that the first subset of physical address bits of the memory request have a value that is greater than or equal to the first number, the control unit is further configured to: calculate a fourth number which is based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem; calculate a first subset of normalized address bits as being equal to the second subset of physical address bits with upper bits being replaced by the first subset of physical address bits; calculate a second subset of normalized address bits as being equal to a concatenation of a fourth subset of physical address bits and a fifth subset of physical address bits; and complete the memory request to a normalized address on the selected memory channel, wherein the normalized address comprises the first subset of normalized address bits and the second subset of normalized address bits.
This invention relates to memory address normalization in a memory subsystem, particularly for optimizing memory access in systems with multiple memory channels. The problem addressed is efficiently routing memory requests to the correct memory channel while ensuring address normalization to maintain data consistency and performance across different memory regions. The system includes a control unit that processes memory requests by analyzing physical address bits. When a first subset of these bits meets or exceeds a predefined threshold, the control unit performs several operations. First, it calculates a fourth number by shifting the first subset of physical address bits up by a fifth number, which is derived from the memory subsystem's address space size. Next, it generates a first subset of normalized address bits by replacing the upper bits of a second subset of physical address bits with the first subset. A second subset of normalized address bits is formed by concatenating a fourth and fifth subset of physical address bits. The memory request is then completed using a normalized address composed of these two subsets, directing the request to the appropriate memory channel. This approach ensures that memory addresses are properly normalized across different channels, improving access efficiency and reducing latency in systems with complex memory architectures. The method dynamically adjusts address routing based on address bit values, optimizing performance for varying memory configurations.
3. The system as recited in claim 2 , wherein the memory subsystem has a non-power of two number of active memory channels.
A system for managing memory access in a computing device addresses the challenge of optimizing memory bandwidth utilization and reducing latency in systems with non-uniform memory architectures. The system includes a memory controller configured to dynamically allocate and deactivate memory channels based on workload demands, improving efficiency and power consumption. A key feature is the ability to operate with a non-power of two number of active memory channels, allowing for flexible configuration to match specific system requirements. This includes scenarios where only a subset of available channels is active, such as when certain channels are deactivated due to power constraints or fault conditions. The memory controller monitors memory access patterns and adjusts channel activation accordingly, ensuring balanced load distribution and minimizing contention. The system also supports error handling by isolating faulty channels while maintaining operational integrity. This approach enhances performance in heterogeneous computing environments where memory access patterns vary dynamically, such as in data centers or high-performance computing applications. The solution provides a scalable and adaptive memory management framework, optimizing resource utilization without requiring hardware modifications.
4. The system as recited in claim 3 , wherein the first subset of physical address bits are adjacent to the third subset of physical address bits.
A system for memory address management in computing devices addresses the challenge of efficiently organizing and accessing memory addresses to improve performance and reduce latency. The system divides a physical address into multiple subsets of bits, where a first subset of physical address bits is adjacent to a third subset of physical address bits. This adjacency allows for optimized memory mapping and faster address decoding, particularly in systems with hierarchical memory structures or multi-level address translation mechanisms. The first subset of bits may correspond to a specific memory region or a portion of an address used for indexing, while the third subset may represent another segment of the address, such as a page offset or a cache line identifier. By ensuring these subsets are adjacent, the system simplifies address translation logic, reduces hardware complexity, and enhances memory access efficiency. The system may also include additional subsets of address bits, each serving distinct purposes like bank selection, row addressing, or column addressing in memory arrays. This structured approach to address bit allocation improves memory bandwidth utilization and minimizes access delays, making it particularly useful in high-performance computing, embedded systems, and memory-intensive applications. The system can be implemented in memory controllers, address decoders, or other memory management units to streamline address processing and optimize memory operations.
5. The system as recited in claim 4 , wherein the fourth subset of physical address bits are adjacent to the first subset of physical address bits.
A system for memory address management in computing devices addresses the challenge of efficiently organizing and accessing memory addresses to improve performance and reduce latency. The system divides a physical address into multiple subsets of bits, each serving a distinct purpose in memory addressing. A first subset of physical address bits is used to identify a specific memory bank within a memory module, while a second subset is used to select a row within the identified bank. A third subset is used to select a column within the identified row, and a fourth subset is used to select a specific memory cell within the identified column. The fourth subset of physical address bits is positioned adjacent to the first subset, ensuring efficient decoding and access to memory cells. This arrangement optimizes memory access by minimizing the time required to decode and locate the correct memory cell, thereby improving overall system performance. The system is particularly useful in high-performance computing environments where rapid memory access is critical.
6. The system as recited in claim 5 , wherein the third subset of physical address bits are adjacent to the fifth subset of physical address bits.
A system for memory addressing includes a memory controller that processes physical addresses divided into multiple subsets of bits. The system assigns a first subset of bits to a first memory region, a second subset to a second memory region, and a third subset to a third memory region. The third subset of bits is positioned adjacent to a fifth subset of bits, which is used for addressing within a specific memory region. The memory controller uses these subsets to map physical addresses to memory locations, ensuring efficient access and management of memory resources. The system may also include a memory module with multiple memory regions, where each region is addressed using the assigned subsets of bits. The adjacent positioning of the third and fifth subsets optimizes address decoding and reduces latency in memory access operations. The system is designed to improve memory addressing efficiency in computing devices, particularly in applications requiring high-speed data retrieval and storage.
7. The system as recited in claim 1 , wherein the one or more clients are graphics engines, and wherein the memory request is generated as part of an application for rendering pixels to be displayed on a display.
This invention relates to a system for managing memory requests in graphics processing, particularly for applications that render pixels for display. The system includes a memory controller that processes memory requests from one or more clients, such as graphics engines, to access memory resources. The memory controller prioritizes and schedules these requests to optimize memory access efficiency. The system also includes a memory interface that facilitates communication between the memory controller and the memory resources, ensuring timely data retrieval or storage. In this specific embodiment, the memory requests are generated by graphics engines as part of an application that renders pixels for display. The system ensures that the graphics engines receive the necessary data to render images efficiently, reducing latency and improving rendering performance. The memory controller may employ techniques such as request prioritization, bandwidth allocation, or caching to enhance memory access efficiency. The overall system aims to improve the performance of graphics rendering applications by optimizing memory access operations.
8. A method comprising: determining, by a control unit of a first device, a number of active memory channels out of a total number of physical memory channels in a memory subsystem; reducing a ratio of the number of active memory channels to the total number of physical memory channels down from a first number to a second number; responsive to determining that a first subset of physical address bits of a received memory request are greater than or equal to the first number: calculating a third number which is based on a value corresponding to a second subset of physical address bits modulo the first number; selecting a memory channel, of a plurality of memory channels, using a concatenation of the third number and a third subset of physical address bits; and completing the memory request to the selected memory channel.
This invention relates to memory channel management in computing systems, specifically addressing the challenge of efficiently distributing memory requests across available memory channels to optimize performance and power consumption. The method involves dynamically adjusting the number of active memory channels in a memory subsystem to balance workload distribution and resource utilization. A control unit in a first device determines the number of active memory channels out of the total physical channels available. The ratio of active to total channels is then reduced from an initial value to a lower value. When a memory request is received, the system checks if a first subset of the physical address bits is greater than or equal to the initial ratio value. If so, a third number is calculated based on the modulo operation of a second subset of address bits with the initial ratio value. This third number is concatenated with a third subset of address bits to select a specific memory channel for the request. The memory request is then completed on the selected channel. This approach ensures efficient memory access by dynamically adapting channel selection based on the current active channel configuration, improving system performance and energy efficiency.
9. The method as recited in claim 8 , wherein responsive to determining that the first subset of physical address bits of the memory request are greater than or equal to the first number, the method further comprising: calculating a fourth number which is based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem; calculating a first subset of normalized address bits as being equal to the second subset of physical address bits with upper bits being replaced by the first subset of physical address bits; calculating a second subset of normalized address bits as being equal to a concatenation of a fourth subset of physical address bits and a fifth subset of physical address bits; and completing the memory request to a normalized address on the selected memory channel, wherein the normalized address comprises the first subset of normalized address bits and the second subset of normalized address bits.
This invention relates to memory address normalization in a memory subsystem, particularly for optimizing memory access across multiple memory channels. The problem addressed is efficiently routing memory requests to the correct memory channel while ensuring address normalization to maintain data consistency and performance. The method involves processing a memory request by first determining whether a subset of physical address bits meets a threshold value. If the condition is satisfied, the method calculates a fourth number by shifting the first subset of physical address bits by a fifth number, which is derived from the memory subsystem's address space size. The method then constructs a first subset of normalized address bits by replacing the upper bits of a second subset of physical address bits with the first subset of physical address bits. A second subset of normalized address bits is formed by concatenating a fourth subset of physical address bits and a fifth subset of physical address bits. The memory request is then completed using a normalized address composed of these two subsets, directing the request to the appropriate memory channel. This approach ensures efficient address mapping and consistent memory access across the subsystem.
10. The method as recited in claim 9 , wherein the memory subsystem has a non-power of two number of active memory channels.
A method for managing memory channels in a computing system addresses the challenge of optimizing memory performance and efficiency, particularly in systems where the number of active memory channels is not a power of two. Traditional memory subsystems often rely on power-of-two channel configurations, which may not align with system requirements or hardware constraints. This method enables efficient memory access and data distribution across a non-power-of-two number of active memory channels, improving bandwidth utilization and reducing latency. The approach involves dynamically configuring memory access patterns to account for the irregular channel count, ensuring balanced workload distribution and minimizing bottlenecks. By adapting to non-standard channel configurations, the method enhances flexibility in system design while maintaining high performance. The technique may be applied in various computing environments, including servers, high-performance computing systems, and embedded devices, where memory subsystem optimization is critical. The method ensures compatibility with existing memory controllers and interfaces, allowing seamless integration into diverse hardware architectures. Overall, this solution provides a robust framework for leveraging non-power-of-two memory channel configurations without compromising system efficiency or performance.
11. The method as recited in claim 10 , wherein the first subset of physical address bits are adjacent to the third subset of physical address bits.
A method for managing memory addresses in a computing system involves partitioning a physical address into multiple subsets to optimize memory access and reduce latency. The physical address is divided into at least three subsets: a first subset, a second subset, and a third subset. The first subset and the third subset are adjacent to each other in the address space, while the second subset is separate. This partitioning allows for efficient addressing schemes, such as interleaving or banking, where adjacent address bits can be used to access different memory banks or modules in parallel, improving performance. The method may also include mapping these subsets to specific memory regions or using them to implement address translation mechanisms, such as page tables or caching strategies. By structuring the address bits in this way, the system can reduce contention, balance memory access loads, and enhance overall throughput. The technique is particularly useful in high-performance computing, embedded systems, and memory-intensive applications where efficient address management is critical.
12. The method as recited in claim 11 , wherein the fourth subset of physical address bits are adjacent to the first subset of physical address bits.
A method for managing memory addresses in a computing system involves partitioning physical address bits into multiple subsets to optimize memory access and reduce latency. The method addresses the challenge of efficiently mapping logical addresses to physical memory locations, particularly in systems with complex memory hierarchies or non-uniform access patterns. The physical address bits are divided into at least four subsets, each serving a distinct purpose in the addressing scheme. The first subset of physical address bits is used to identify a specific memory bank or module, while the second subset is used to select a row within that bank. The third subset targets a column within the selected row, and the fourth subset further refines the address to access a specific memory cell or cache line. The fourth subset of physical address bits is positioned adjacent to the first subset, ensuring contiguous bit ranges for efficient decoding and reducing the complexity of address translation logic. This arrangement improves memory access speed by minimizing the number of address translation steps and simplifying the hardware design. The method is particularly useful in high-performance computing environments where low-latency memory access is critical.
13. The method as recited in claim 12 , wherein the third subset of physical address bits are adjacent to the fifth subset of physical address bits.
A method for managing memory addresses in a computing system involves partitioning physical address bits into multiple subsets to optimize memory access and reduce latency. The method addresses the challenge of efficiently organizing memory addresses to improve performance in systems with complex memory hierarchies or non-uniform memory access (NUMA) architectures. The physical address bits are divided into at least five subsets, each serving a distinct purpose in addressing memory locations. The third subset of physical address bits is positioned adjacent to the fifth subset, ensuring contiguous bit allocation for specific memory management tasks. This adjacency may facilitate faster address decoding, improved cache coherence, or simplified address translation in systems where certain bit groups must be processed together. The method may also include additional steps such as mapping logical addresses to physical addresses, handling address conflicts, or optimizing address distribution across memory modules. By strategically partitioning and arranging address bits, the method aims to enhance memory access efficiency, reduce latency, and improve overall system performance in high-performance computing environments.
14. The method as recited in claim 8 , further comprising generating the memory request as part of an application for rendering pixels to be displayed on a display.
A method for processing memory requests in a computing system, particularly for applications involving pixel rendering on a display. The method addresses inefficiencies in memory access during graphics processing, where delays in memory requests can degrade performance. The system includes a memory controller that receives memory requests from a processing unit and determines whether to service them immediately or defer them based on priority and system conditions. If a request is deferred, it is stored in a buffer until conditions allow servicing. The method further involves generating memory requests as part of an application that renders pixels for display, ensuring timely access to memory resources for graphics rendering tasks. This approach optimizes memory bandwidth usage and reduces latency in graphics processing pipelines, improving overall system performance for display-related operations. The technique is applicable in systems where memory access contention is a bottleneck, such as in real-time rendering or high-resolution display applications.
15. An apparatus comprising: a control unit; and a memory subsystem comprising a plurality of memory channels; wherein the control unit is configured to: determine a number of active memory channels out of a total number of physical memory channels in the memory subsystem; reduce a ratio of the number of active memory channels to the total number of physical memory channels down from a first number to a second number; responsive to determining a first subset of physical address bits of a received memory request are greater than or equal to the first number: calculate a third number which is based on a second subset of physical address bits modulo the first number; select a memory channel, of the plurality of memory channels, using a concatenation of the third number and a third subset of physical address bits; and complete the memory request to the selected memory channel.
This invention relates to memory channel management in computing systems, specifically addressing power efficiency and performance optimization in memory subsystems with multiple channels. The problem solved is the inefficient use of memory channels, which can lead to excessive power consumption and suboptimal performance when all channels are active unnecessarily. The apparatus includes a control unit and a memory subsystem with multiple physical memory channels. The control unit dynamically adjusts the number of active memory channels by reducing the ratio of active channels to total physical channels from an initial value to a lower value. When processing a memory request, the control unit first checks if a subset of the request's physical address bits meets or exceeds the initial channel ratio. If so, it calculates a value based on another subset of address bits using a modulo operation with the initial ratio. This value is then concatenated with a third subset of address bits to select a specific memory channel for the request. The request is then completed on the selected channel. This approach enables selective activation of memory channels, reducing power consumption while maintaining performance by intelligently distributing memory requests across fewer active channels. The modulo-based selection ensures balanced usage of the active channels, preventing bottlenecks.
16. The apparatus as recited in claim 15 , wherein responsive to determining a first subset of physical address bits of the memory request are greater than or equal to the first number, the control unit is further configured to: calculate a fourth number which is based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem; calculate a first subset of normalized address bits as being equal to the second subset of physical address bits with upper bits being replaced by the first subset of physical address bits; calculate a second subset of normalized address bits as being equal to a concatenation of a fourth subset of physical address bits and a fifth subset of physical address bits; and complete the memory request to a normalized address on the selected memory channel, wherein the normalized address comprises the first subset of normalized address bits and the second subset of normalized address bits.
This invention relates to memory address normalization in a memory subsystem, particularly for optimizing memory access in systems with multiple memory channels. The problem addressed is efficiently routing memory requests to the correct memory channel while ensuring address normalization to maintain data consistency and performance. The apparatus includes a control unit that processes memory requests by analyzing physical address bits. When a first subset of these bits meets or exceeds a predefined threshold, the control unit performs several operations. First, it calculates a fourth number by shifting the first subset of physical address bits upward by a fifth number, which is derived from the memory subsystem's address space size. Next, it generates a first subset of normalized address bits by replacing the upper bits of a second subset of physical address bits with the first subset. A second subset of normalized address bits is formed by concatenating a fourth and fifth subset of physical address bits. The memory request is then completed using a normalized address composed of these two subsets, directing it to the appropriate memory channel. This method ensures that memory addresses are properly normalized across different channels, improving access efficiency and reducing latency in systems with distributed memory architectures. The approach is particularly useful in high-performance computing environments where memory bandwidth and consistency are critical.
17. The apparatus as recited in claim 16 , wherein the memory subsystem has a non-power of two number of active memory channels.
A memory subsystem is designed to improve performance and efficiency in computing systems by utilizing a non-power of two number of active memory channels. Traditional memory subsystems often rely on power-of-two configurations, such as 2, 4, 8, or 16 channels, which can lead to inefficiencies in data access patterns and resource utilization. The invention addresses this limitation by implementing a memory subsystem with a non-power of two number of active channels, such as 3, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, or 17 channels. This configuration allows for more flexible and optimized memory access, reducing bottlenecks and improving overall system performance. The memory subsystem may include multiple memory modules, each connected to one or more channels, and may be integrated into a computing device such as a server, workstation, or high-performance computing system. The non-power of two channel configuration enables better alignment with specific workload requirements, enhancing data throughput and reducing latency. This approach is particularly beneficial in applications where memory bandwidth and efficiency are critical, such as scientific computing, artificial intelligence, and large-scale data processing.
18. The apparatus as recited in claim 17 , wherein the first subset of physical address bits are adjacent to the third subset of physical address bits.
The invention relates to memory addressing systems, specifically addressing the challenge of efficiently managing physical memory addresses in computing systems. The apparatus includes a memory controller configured to receive a physical address and partition it into multiple subsets of bits. The first subset of physical address bits is used to select a memory bank, the second subset is used to select a row within the bank, and the third subset is used to select a column within the row. The apparatus further includes a memory module with multiple banks, each bank containing multiple rows and columns of memory cells. The memory controller maps the first subset of bits to a specific bank, the second subset to a specific row within that bank, and the third subset to a specific column within that row. The apparatus may also include a row buffer to temporarily store data from a selected row for faster access. The invention ensures efficient memory access by organizing physical addresses into distinct subsets for bank, row, and column selection, optimizing memory operations. The first subset of physical address bits is positioned adjacent to the third subset, allowing for streamlined address decoding and improved performance. This design reduces latency and enhances data retrieval efficiency in memory systems.
19. The apparatus as recited in claim 18 , wherein the fourth subset of physical address bits are adjacent to the first subset of physical address bits.
The invention relates to memory addressing systems, specifically addressing the challenge of efficiently managing and accessing memory in computing systems. The apparatus includes a memory controller configured to receive a physical address and distribute it into multiple subsets of address bits. The first subset of physical address bits is used to select a memory bank, while the second subset is used to select a row within the bank. The third subset is used to select a column within the row, and the fourth subset is used to select a specific memory cell within the column. The fourth subset of physical address bits is positioned adjacent to the first subset, optimizing the addressing scheme for faster access and reduced latency. This arrangement improves memory access efficiency by minimizing the time required to decode and route address signals, particularly in high-performance computing environments where rapid data retrieval is critical. The apparatus may also include additional logic to handle error correction or address remapping, ensuring reliable memory operations. The invention is particularly useful in systems requiring low-latency memory access, such as high-speed processors, graphics processing units, or specialized accelerators.
20. The apparatus as recited in claim 19 , wherein the third subset of physical address bits are adjacent to the fifth subset of physical address bits.
The invention relates to memory addressing systems, specifically addressing the challenge of efficiently managing and accessing memory in computing systems. The apparatus includes a memory controller configured to receive a physical address and partition it into multiple subsets of bits. These subsets are used to determine memory access parameters, such as row, column, and bank addresses, to optimize memory operations. The apparatus further includes a mapping module that translates these subsets into corresponding memory access commands. A key feature is the arrangement of the physical address bits, where a third subset of bits is positioned adjacent to a fifth subset of bits. This adjacency improves address decoding efficiency and reduces latency in memory access operations. The apparatus may also include error detection and correction mechanisms to ensure data integrity during memory operations. The system is designed to work with various memory types, including dynamic random-access memory (DRAM), and can be integrated into processors, memory modules, or other computing devices. The invention aims to enhance memory performance by optimizing address decoding and reducing access delays.
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May 5, 2020
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