Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for use by a data storage controller, comprising: assessing a fill status of a memory access queue associated with a memory device, the memory device including a memory die with cache memory and non-cache memory; determining whether to submit memory access operations to the memory die as cached operations or as non-cached operations based on the fill status of the memory access queue; and submitting the memory access operations to the memory die as cached operations or as non-cached operations based on the determination.
Data storage systems and memory management. This invention addresses the problem of optimizing memory access operations to a memory die that includes both cache memory and non-cache memory, aiming to improve performance and efficiency. A data storage controller assesses the current fill level of a queue used for managing memory access operations. Based on this assessment of the queue's fill status, the controller makes a decision. This decision dictates whether subsequent memory access operations directed to the memory die will be treated as cached operations or as non-cached operations. The controller then proceeds to submit these memory access operations to the memory die, adhering to the determined caching strategy (either cached or non-cached). This adaptive approach allows the controller to dynamically adjust its memory access behavior based on the real-time load on the memory access queue, potentially leading to reduced latency and improved throughput.
2. The method of claim 1 , wherein assessing the fill status of the memory access queue includes determining a number of entries in the memory access queue.
A system and method for managing memory access operations in a computing environment involves monitoring and optimizing the performance of memory access queues. The technology addresses inefficiencies in memory access operations, particularly in systems where memory access queues may become bottlenecks due to improper management of pending requests. The method includes assessing the fill status of a memory access queue to determine its current utilization, which involves counting the number of entries present in the queue. This assessment helps in dynamically adjusting memory access operations to prevent stalls or delays. The system may further include mechanisms to prioritize or reorder memory access requests based on the queue's fill status, ensuring efficient use of memory bandwidth and reducing latency. By monitoring the queue's occupancy, the system can proactively manage memory access operations, improving overall system performance and responsiveness. The method is particularly useful in high-performance computing environments where memory access efficiency is critical.
3. The method of claim 2 , wherein the memory access queue includes a read request queue, and wherein determining the number of entries in the memory access queue includes receiving a value indicative of the number of entries in the read request queue.
This invention relates to memory access management in computing systems, specifically addressing the challenge of efficiently tracking and prioritizing memory access requests to optimize performance. The method involves monitoring a memory access queue that includes a read request queue, where the number of entries in the queue is determined by receiving a value indicative of the number of entries in the read request queue. This allows the system to dynamically assess the load of pending read operations, enabling better scheduling and resource allocation. The method may also involve tracking other types of memory access requests, such as write requests, to provide a comprehensive view of memory access activity. By monitoring the read request queue specifically, the system can prioritize critical read operations, reduce latency, and improve overall system efficiency. The invention is particularly useful in high-performance computing environments where timely memory access is essential for maintaining throughput and responsiveness. The method ensures that memory access operations are managed in a way that minimizes bottlenecks and maximizes resource utilization.
4. The method of claim 1 , wherein, if the memory access operations are submitted to the memory die as cached operations, automatically resuming non-cached submissions if the memory access queue becomes empty.
A method for managing memory access operations in a memory system, particularly in systems with both cached and non-cached memory access modes. The invention addresses inefficiencies in memory access handling, where cached operations may lead to delays or resource contention, especially when the memory access queue becomes empty. The method dynamically adjusts the submission mode of memory access operations to optimize performance. When memory access operations are initially submitted as cached operations, the system monitors the memory access queue. If the queue becomes empty, the system automatically switches to submitting non-cached operations, ensuring continuous and efficient memory access without unnecessary delays. This adaptive approach improves system responsiveness and resource utilization by avoiding idle periods in the memory access pipeline. The method is particularly useful in high-performance computing environments where memory access patterns may vary, and maintaining optimal throughput is critical. By automatically resuming non-cached submissions when the queue is empty, the system ensures that memory access operations proceed without unnecessary interruptions, enhancing overall system efficiency.
5. The method of claim 1 , wherein the memory access queue is a single-stage queue; and wherein determining whether to submit the memory access operations to the memory die as cached operations or as non-cached operations includes comparing a number of entries in the single-stage queue to a single-stage queue threshold.
This invention relates to memory access optimization in computing systems, specifically addressing inefficiencies in handling memory operations between a host system and a memory die. The problem arises when memory access operations are processed through a multi-stage queue, leading to latency and reduced performance due to unnecessary buffering or delays in determining whether operations should be cached or executed directly. The solution involves a single-stage memory access queue that simplifies the decision-making process for memory operations. The system monitors the number of entries in this single-stage queue and compares it to a predefined threshold. If the queue count exceeds the threshold, memory access operations are submitted as non-cached operations to prioritize speed, while below the threshold, they are submitted as cached operations to optimize efficiency. This approach reduces latency by eliminating intermediate buffering stages and dynamically adjusts the caching strategy based on real-time queue occupancy, improving overall system performance. The invention is particularly useful in high-performance computing environments where minimizing memory access delays is critical.
6. The method of claim 5 , wherein submitting the memory access operations to the memory die comprises: submitting the memory access operations to the memory die as cached operations if the number of entries in the single-stage queue exceeds the single-stage queue threshold; and submitting the memory access operations to the memory die as non-cached operations if the number of entries in the single-stage queue does not exceed the single-stage queue threshold.
This invention relates to memory access management in computing systems, specifically optimizing memory operations in a memory subsystem with a single-stage queue. The problem addressed is inefficient memory access handling, particularly when dealing with varying workloads that can lead to bottlenecks or underutilization of memory resources. The method involves dynamically adjusting how memory access operations are submitted to a memory die based on the current load in a single-stage queue. The single-stage queue temporarily holds memory access operations before they are processed. A threshold is defined for the queue, representing a maximum number of entries. When the number of entries in the queue exceeds this threshold, indicating high demand, the operations are submitted to the memory die as cached operations. Cached operations leverage a cache to improve performance by reducing direct access to the slower memory die. Conversely, if the queue does not exceed the threshold, the operations are submitted as non-cached, bypassing the cache for direct memory access, which may be more efficient for certain workloads. This dynamic switching between cached and non-cached operations ensures optimal use of memory resources, balancing performance and efficiency based on real-time demand. The approach helps prevent bottlenecks during high-load periods while avoiding unnecessary cache usage when the system is underutilized.
7. The method of claim 1 , wherein the memory access queue is a two-stage queue that includes a first queue and a second queue, the second queue receiving entries only if the first queue is full; and wherein determining whether to submit the memory access operations to the memory die as cached operations or as non-cached operations includes comparing a number of entries in the second queue to a second queue threshold.
This invention relates to memory access management in computing systems, specifically addressing inefficiencies in handling memory access operations when a memory access queue becomes full. The problem arises when a memory controller must decide whether to submit operations as cached or non-cached, particularly under high load conditions where the queue may overflow. Traditional systems lack mechanisms to dynamically adjust memory access strategies based on queue congestion, leading to performance bottlenecks or unnecessary cache usage. The invention introduces a two-stage memory access queue system comprising a first queue and a second queue. The second queue only receives entries when the first queue is full, preventing data loss and ensuring all operations are processed. The system monitors the number of entries in the second queue and compares it to a predefined threshold. If the second queue exceeds this threshold, the memory controller submits subsequent memory access operations as non-cached, bypassing the cache to reduce latency and improve throughput. Conversely, if the second queue is below the threshold, operations are submitted as cached, leveraging cache for efficiency. This dynamic adjustment optimizes memory access performance by balancing cache usage and direct memory operations based on real-time queue congestion. The invention improves system efficiency by preventing queue overflow and dynamically adapting memory access strategies to current load conditions.
8. The method of claim 7 , wherein submitting the memory access operations to the memory die comprises: submitting the memory access operations as cached operations if the number of entries in the second queue exceeds the second queue threshold; and submitting the memory access operations as non-cached operations if the number of entries in the second queue does not exceed the second queue threshold.
This invention relates to memory access management in a memory system, specifically optimizing the handling of memory access operations based on queue occupancy. The problem addressed is inefficient memory access performance due to improper handling of cached and non-cached operations, leading to bottlenecks and reduced throughput. The system includes a memory controller that manages memory access operations for a memory die. A first queue stores memory access operations, and a second queue stores operations awaiting submission to the memory die. The memory controller monitors the number of entries in the second queue and compares it to a predefined second queue threshold. When the number of entries exceeds this threshold, the memory controller submits the operations as cached operations, leveraging the cache to improve efficiency. If the number of entries does not exceed the threshold, the operations are submitted as non-cached operations, bypassing the cache to reduce latency for lower queue loads. This dynamic switching between cached and non-cached modes optimizes memory access performance based on current system conditions. The threshold ensures that the cache is used effectively without overloading it, while non-cached operations are prioritized when the queue is lightly populated. This approach balances throughput and latency, improving overall memory system efficiency.
9. The method of claim 1 , wherein the data storage controller includes a die manager, and the die manager assesses the fill status of the memory access queue and determines whether to submit the memory access operations to the memory die as cached operations or as non-cached operations.
The invention relates to data storage systems, specifically improving memory access efficiency in solid-state storage devices. The problem addressed is optimizing memory access operations to balance performance and resource utilization in storage controllers. Traditional systems often struggle with inefficient handling of memory access queues, leading to bottlenecks or underutilized memory resources. The invention involves a data storage controller with a die manager that dynamically assesses the fill status of a memory access queue. Based on this assessment, the die manager determines whether to submit memory access operations to the memory die as cached or non-cached operations. Cached operations leverage temporary storage for faster access, while non-cached operations directly access the memory die, bypassing the cache. The die manager's decision optimizes performance by reducing latency when the queue is lightly loaded and conserving resources when the queue is heavily loaded. This adaptive approach ensures efficient use of memory resources and improves overall system responsiveness. The invention is particularly useful in high-performance storage systems where memory access patterns vary dynamically.
10. The method of claim 9 , wherein the memory device includes a plurality of memory dies with a separate memory access queue for each die, and wherein the die manager determines a number of entries in each separate memory access queue and separately determines, on a queue-by-queue basis, whether to submit memory access operations to a particular die as cached operations or as non-cached operations based on the number of entries in the memory access queue for the particular die.
A memory management system optimizes access operations in a multi-die memory device by dynamically adjusting caching behavior based on queue congestion. The system includes multiple memory dies, each with its own dedicated memory access queue. A die manager monitors the number of pending operations in each queue and independently decides, for each die, whether to process subsequent memory access requests as cached or non-cached operations. This decision is made on a per-queue basis, depending on the current queue length. By dynamically switching between cached and non-cached modes, the system improves memory efficiency and performance, particularly under varying workload conditions. The approach helps balance latency and throughput by avoiding excessive queue buildup while maintaining fast access for frequently used data when appropriate. This method is particularly useful in high-performance computing environments where memory access patterns can fluctuate significantly.
11. A data storage controller for use with a memory device, comprising: a queue assessment component configured to determine a fill level of a memory access queue associated with the memory device, the memory device including a memory die with cache memory and non-cache memory; a memory access determination component configured to determine whether to submit memory access operations to the memory die as cached operations or as non-cached operations based on the fill level of the memory access queue; and a memory access controller configured to submit the memory access operations to the memory die as cached operations or as non-cached operations based on the determination made by the memory access determination component.
A data storage controller manages memory access operations for a memory device containing a memory die with both cache and non-cache memory. The controller includes a queue assessment component that monitors the fill level of a memory access queue associated with the device. A memory access determination component evaluates this fill level to decide whether to route memory access operations through the cache or directly to the non-cache memory. The memory access controller then executes these operations accordingly, either utilizing the cache for faster access or bypassing it to reduce latency when the queue is heavily loaded. This dynamic routing optimizes performance by balancing the trade-offs between cache efficiency and queue congestion, particularly in systems where memory access patterns vary or where cache utilization may degrade performance under certain conditions. The controller ensures efficient memory access by adapting to real-time queue conditions, improving overall system responsiveness and throughput.
12. The data storage controller of claim 11 , wherein the queue assessment component and the memory access determination component are components of a die manager, the die manager configured to determine the fill level of the memory access queue and submit the memory access operations to the memory die as cached operations or as non-cached operations based on the fill level of the memory access queue.
This invention relates to a data storage controller with improved memory access management in solid-state storage systems. The problem addressed is inefficient memory access operations in storage devices, particularly when handling varying workloads and queue fill levels. The invention provides a die manager that dynamically adjusts memory access operations based on the fill level of a memory access queue. The die manager includes a queue assessment component to monitor the fill level of the memory access queue and a memory access determination component to decide whether to submit operations as cached or non-cached based on this fill level. When the queue is highly filled, operations may be submitted as non-cached to reduce latency, while lower fill levels may favor cached operations for better performance. This adaptive approach optimizes throughput and responsiveness by balancing between cached and non-cached operations according to real-time queue conditions. The die manager ensures efficient utilization of memory resources by dynamically adjusting access strategies without requiring external intervention. This solution is particularly useful in high-performance storage systems where workload patterns vary significantly.
13. The data storage controller of claim 12 , wherein the memory device includes a plurality of memory dies with a separate memory access queue for each die, and wherein the die manager is configured to determine a number of entries in each separate memory access queue and to separately determine, on a queue-by-queue basis, whether to submit memory access operations to a particular die as cached operations or as non-cached operations based on the number of entries in the memory access queue for the particular die.
A data storage controller manages memory access operations in a memory device containing multiple memory dies, each with its own dedicated memory access queue. The controller includes a die manager that monitors the number of entries in each queue and dynamically decides, for each die individually, whether to process memory access operations as cached or non-cached operations based on the queue length. This approach optimizes performance by adapting to the workload conditions of each die, reducing latency and improving efficiency. The controller ensures that memory access operations are distributed appropriately across the dies, preventing bottlenecks and enhancing overall system responsiveness. The die manager's decision-making process is independent for each die, allowing for fine-grained control over memory access strategies. This method improves resource utilization and minimizes delays in high-demand scenarios. The system is particularly useful in environments where memory access patterns vary significantly across different dies, ensuring balanced and efficient operation.
14. The data storage controller of claim 11 , wherein the queue assessment component includes a queue entry counter configured to count a number of entries in the memory access queue to assess the fill level; and wherein the memory access determination component includes a queue threshold comparator configured to determine whether to submit the memory access operations as cached operations or as non-cached operations by comparing the count to a queue threshold.
A data storage controller manages memory access operations by dynamically determining whether to process them as cached or non-cached operations based on the fill level of a memory access queue. The controller includes a queue assessment component that monitors the queue's fill level by counting the number of entries in the queue. A memory access determination component then compares this count to a predefined queue threshold to decide the processing mode. If the queue fill level exceeds the threshold, the controller may prioritize non-cached operations to prevent queue overflow or performance degradation. Conversely, if the fill level is below the threshold, cached operations may be preferred to optimize performance. This adaptive approach ensures efficient memory access management by balancing queue utilization and system performance. The system is particularly useful in high-performance storage environments where memory access patterns vary dynamically, requiring real-time adjustments to maintain optimal throughput and latency. The queue entry counter and queue threshold comparator work together to provide a scalable and responsive mechanism for handling memory access operations.
15. The data storage controller of claim 14 , wherein the memory access queue is configured as a single-stage queue.
A data storage controller manages data access operations between a host system and a storage device, ensuring efficient and reliable data transfer. A key challenge in such systems is optimizing memory access operations to minimize latency and maximize throughput, especially when handling multiple concurrent requests. Traditional multi-stage memory access queues can introduce complexity and overhead, leading to inefficiencies in processing. The invention addresses this by implementing a memory access queue as a single-stage queue within the data storage controller. This design simplifies the queue structure, reducing the number of stages required to process memory access requests. By eliminating intermediate stages, the system minimizes latency and improves overall performance. The single-stage queue directly manages memory access operations, ensuring faster response times and more efficient resource utilization. This approach is particularly beneficial in high-performance storage environments where low-latency access is critical. The simplified architecture also reduces hardware complexity, making the system more cost-effective and easier to maintain. The invention enhances data storage controller efficiency by streamlining memory access operations through a single-stage queue design.
16. The data storage controller of claim 14 , wherein the memory access queue is configured as a two-stage queue that includes a first queue and a second queue, the second queue configured to receive entries only if the first queue is full, and wherein the queue entry counter is configured to count the number of entries in the second stage of the two-stage queue.
This invention relates to data storage controllers and addresses the challenge of efficiently managing memory access requests to prevent data loss or performance degradation when the memory access queue becomes full. The system includes a data storage controller with a memory access queue structured as a two-stage queue comprising a first queue and a second queue. The second queue only receives entries when the first queue is full, ensuring that incoming requests are processed in an orderly manner without overwriting or dropping data. A queue entry counter is included to track the number of entries specifically in the second stage of the two-stage queue, allowing the controller to monitor and manage memory access requests more effectively. This design helps prevent queue overflow and ensures that all requests are processed, improving system reliability and performance. The counter provides real-time visibility into the queue's status, enabling dynamic adjustments to request handling. The invention is particularly useful in high-demand storage environments where efficient queue management is critical to maintaining data integrity and system responsiveness.
17. The data storage controller of claim 11 , wherein the memory access controller comprises a cached read submission controller and a non-cached read submission controller.
The invention relates to a data storage controller designed to improve memory access efficiency in computing systems. The controller addresses the problem of inefficient memory access operations, particularly in systems where different types of read requests (cached and non-cached) must be handled separately to optimize performance and resource utilization. The data storage controller includes a memory access controller that manages read operations from a memory device. This memory access controller is divided into two specialized components: a cached read submission controller and a non-cached read submission controller. The cached read submission controller processes read requests that can be served from a cache, reducing latency by avoiding direct memory access. The non-cached read submission controller handles read requests that require direct access to the memory device, ensuring that these operations are managed efficiently without unnecessary delays. By separating these functions, the controller ensures that cached and non-cached read operations are optimized independently, improving overall system performance. This design allows for better resource allocation and reduces contention between different types of memory access requests. The invention is particularly useful in high-performance computing environments where minimizing latency and maximizing throughput are critical.
18. The data storage controller of claim 17 , wherein the cached read submission controller is configured to submit memory access operations as cached operations while the fill level exceeds a threshold; and wherein the non-cached read submission controller is configured to submit the memory access operations as non-cached operations so long as the fill level does not exceed the threshold.
A data storage controller manages memory access operations by dynamically switching between cached and non-cached modes based on a buffer fill level. The controller includes a cached read submission controller and a non-cached read submission controller. The cached read submission controller submits memory access operations as cached operations when the buffer fill level exceeds a predefined threshold, leveraging cached data for faster access. Conversely, the non-cached read submission controller submits memory access operations as non-cached operations when the buffer fill level does not exceed the threshold, bypassing the cache to reduce latency or conserve resources. This adaptive approach optimizes performance by balancing the trade-offs between cached and non-cached access based on system conditions. The controller monitors the buffer fill level to determine the appropriate mode, ensuring efficient memory access while maintaining system responsiveness. This design is particularly useful in storage systems where varying workloads and buffer conditions require dynamic adjustments to access methods.
19. The data storage controller of claim 11 , wherein the memory die is a non-volatile memory (NVM) die.
A data storage controller is designed to manage data operations in a storage system, particularly focusing on improving efficiency and reliability. The controller interfaces with one or more memory dies, which are semiconductor chips that store data. In this configuration, the memory die is specifically a non-volatile memory (NVM) die, meaning it retains data even when power is removed. Non-volatile memory types include flash memory, such as NAND or NOR flash, as well as emerging technologies like phase-change memory (PCM) or resistive RAM (ReRAM). The controller includes circuitry to perform read, write, and erase operations on the NVM die, ensuring data integrity and optimizing performance. It may also include error correction mechanisms to handle data corruption and wear-leveling algorithms to extend the lifespan of the memory cells. The controller may further support features like bad block management, where defective memory regions are identified and avoided during data operations. By using an NVM die, the storage system achieves persistent data storage, making it suitable for applications requiring reliable long-term data retention, such as solid-state drives (SSDs), embedded storage, and enterprise storage systems. The controller's design ensures efficient data handling while maintaining the durability and reliability of the non-volatile memory.
20. A data storage device, comprising: a non-volatile memory (NVM) device having a die; and a die manager configured to determine a fill level of a memory access queue associated with the die, and submit memory access operations to the die as cached operations or as non-cached operations based on the fill level of the memory access queue.
A data storage device includes a non-volatile memory (NVM) device with at least one die and a die manager that optimizes memory access operations. The die manager monitors the fill level of a memory access queue associated with the die. When the queue is below a certain threshold, the die manager submits memory access operations as cached operations, allowing the NVM device to use internal caching mechanisms for faster access. When the queue reaches or exceeds the threshold, the die manager submits operations as non-cached, bypassing the cache to prevent queue congestion and ensure timely processing. This dynamic adjustment improves performance by balancing latency and throughput, particularly in high-load scenarios where excessive queuing can degrade efficiency. The system ensures that memory access operations are processed efficiently, reducing bottlenecks and maintaining responsiveness. The die manager may also prioritize certain operations or adjust thresholds based on workload characteristics to further optimize performance. This approach is particularly useful in solid-state drives (SSDs) and other NVM-based storage systems where efficient queue management is critical for maintaining high-speed data access.
21. The data storage device of claim 20 , wherein the NVM device includes a plurality of dies with a separate memory access queue for each of the plurality of dies, and wherein the die manager is configured to determine a fill level of each separate memory access queue and to separately determine, on a queue-by-queue basis, whether to submit memory access operations to a particular die as cached operations or as non-cached operations based on the fill level of the memory access queue for the particular die.
This invention relates to data storage devices, specifically non-volatile memory (NVM) devices with improved memory access management. The problem addressed is inefficient memory access handling in multi-die NVM devices, which can lead to performance bottlenecks and suboptimal resource utilization. The invention describes an NVM device comprising multiple dies, each with its own dedicated memory access queue. A die manager monitors the fill level of each queue and dynamically decides, on a per-queue basis, whether to submit memory access operations as cached or non-cached operations. This decision is based on the current fill level of the queue for a particular die. By adjusting the caching strategy per die, the system optimizes performance and resource usage, preventing queue overflows and reducing latency. The die manager's ability to independently assess each queue's status allows for fine-grained control over memory access operations. This approach ensures that high-priority operations are processed efficiently while maintaining system stability. The invention improves overall system performance by dynamically adapting to varying workload conditions across multiple dies.
22. The data storage device of claim 20 , wherein the NVM device is a NAND storage device.
The invention relates to data storage devices, specifically addressing the need for efficient and reliable data storage in non-volatile memory (NVM) systems. The device includes a controller and an NVM device, where the controller is configured to manage data operations such as reading, writing, and erasing data. The NVM device is a NAND storage device, which is a type of flash memory known for its high density, low power consumption, and cost-effectiveness. The controller interacts with the NAND storage device to perform these operations while ensuring data integrity and performance. The NAND storage device may include multiple memory cells arranged in a grid, where data is stored in pages and erased in blocks. The controller may implement error correction, wear leveling, and other techniques to optimize the NAND device's lifespan and reliability. The invention aims to improve data storage efficiency, durability, and performance in NVM systems by leveraging the characteristics of NAND flash memory.
23. An apparatus for use by a data storage controller, comprising: means for determining a number of entries in a memory access queue associated with a memory device, the memory device including a memory die with cache memory and non-cache memory; means for determining whether to submit memory access operations to the memory die as cached operations or as non-cached operations based on the number of entries in the memory access queue; and means for submitting the memory access operations to the memory die as cached operations or as non-cached operations based on the determination made by the means for determining.
The apparatus is designed for use by a data storage controller to optimize memory access operations in a memory device containing both cache and non-cache memory. The memory device includes at least one memory die with separate cache and non-cache memory regions. The apparatus monitors the number of entries in a memory access queue associated with the memory device. Based on the queue length, the apparatus decides whether to submit memory access operations as cached or non-cached operations. If the queue has a high number of entries, the apparatus may prioritize non-cached operations to reduce latency, while a lower queue length may favor cached operations for improved performance. The apparatus then submits the memory access operations to the memory die accordingly, dynamically adjusting the access method to balance performance and efficiency. This approach helps manage memory access bottlenecks and improves overall system responsiveness by intelligently routing operations based on current queue conditions. The solution addresses inefficiencies in memory access management, particularly in systems where memory operations must be dynamically optimized for varying workloads.
24. The apparatus of claim 23 , wherein the memory access queue is a single-stage queue; and wherein the means for determining whether to submit the memory access operations to the memory device as cached operations or as non-cached operations includes means for comparing a number of entries in the single-stage queue to a single-stage queue threshold.
This invention relates to memory access optimization in computing systems, specifically addressing inefficiencies in handling memory operations. The apparatus includes a memory access queue that processes memory access operations, such as read or write requests, for a memory device. The queue is a single-stage design, meaning it processes operations in a single step without multiple stages of buffering or prioritization. The apparatus determines whether to submit operations as cached (using a cache memory) or non-cached (directly accessing the main memory) by comparing the number of entries in the queue to a predefined threshold. If the queue exceeds the threshold, operations may be submitted differently to balance performance and resource usage. This approach helps manage memory access latency and bandwidth, particularly in systems where memory operations vary in frequency or priority. The single-stage queue simplifies the design while allowing dynamic adjustment based on workload conditions. The threshold comparison ensures that memory access strategies adapt to system demands, improving overall efficiency.
25. The apparatus of claim 24 , wherein the means for submitting the memory access operations to the memory die includes: means for submitting the memory access operations as cached operations if the number of entries in the single-stage queue exceeds the single-stage queue threshold; and means for submitting the memory access operations as non-cached operations if the number of entries in the single-stage queue does not exceed the single-stage queue threshold.
This invention relates to memory access management in electronic systems, specifically addressing inefficiencies in handling memory operations in systems with memory dies. The problem arises when memory access operations are processed through a single-stage queue, leading to bottlenecks and reduced performance due to the queue's limited capacity. The invention improves memory access efficiency by dynamically adjusting how operations are submitted to the memory die based on the queue's occupancy. The apparatus includes a single-stage queue for storing memory access operations and a mechanism to monitor the number of entries in the queue. When the number of entries exceeds a predefined threshold, the apparatus submits the operations as cached operations, leveraging a cache to reduce latency and improve throughput. Conversely, if the queue occupancy does not exceed the threshold, the operations are submitted as non-cached operations, bypassing the cache to minimize unnecessary overhead. This adaptive approach optimizes memory access performance by balancing between cached and non-cached submissions based on real-time queue conditions. The invention ensures efficient resource utilization and reduces latency in memory-intensive applications.
26. The apparatus of claim 23 , wherein the memory access queue is a two-stage queue that includes a first queue and a second queue, the second queue receiving entries only if the first queue is full; and wherein the means for determining whether to submit the memory access operations to the memory device as cached operations or as non-cached operations includes means for comparing a number of entries in the second queue to a second queue threshold.
This invention relates to memory access management in computing systems, specifically addressing the challenge of efficiently handling memory access operations to optimize performance and resource utilization. The apparatus includes a memory access queue structured as a two-stage queue comprising a first queue and a second queue. The second queue only receives entries when the first queue is full, preventing overflow and ensuring controlled processing. The apparatus further includes a mechanism to determine whether to submit memory access operations to the memory device as cached or non-cached operations. This determination is based on comparing the number of entries in the second queue to a predefined second queue threshold. If the second queue exceeds this threshold, the system may prioritize non-cached operations to avoid bottlenecks, while staying below the threshold may favor cached operations for faster access. This design improves memory access efficiency by dynamically adjusting operation types based on queue load, reducing latency and enhancing system performance. The invention is particularly useful in high-performance computing environments where memory access patterns vary dynamically.
27. The apparatus of claim 23 , wherein the memory die is a non-volatile memory (NVM).
A non-volatile memory (NVM) die is integrated into a semiconductor apparatus to enhance data retention and reliability. The apparatus includes a memory die, a controller, and an interface for communication between the memory die and an external host. The memory die stores data persistently without requiring continuous power, making it suitable for applications where data integrity must be maintained during power loss. The controller manages read, write, and erase operations, ensuring efficient data handling and wear leveling to prolong the memory die's lifespan. The interface facilitates high-speed data transfer between the memory die and the host system, supporting protocols such as PCIe or NVMe for low-latency access. The NVM die may include technologies like NAND flash, NOR flash, or emerging non-volatile memory types, providing scalable storage solutions for embedded systems, solid-state drives, and other data storage applications. The integration of NVM ensures that critical data remains intact even when power is disconnected, addressing the limitations of volatile memory in scenarios requiring long-term data retention. The apparatus may also include error correction mechanisms to mitigate data corruption, further enhancing reliability. This design is particularly useful in industrial, automotive, and consumer electronics where uninterrupted data availability is essential.
28. A method for use by a data storage controller, comprising: assessing a fill status of a memory access queue associated with a memory device; determining a memory access procedure for use in accessing the memory device based on the fill status of the memory access queue, including determining whether to submit memory access operations to the memory device as cached operations or as non-cached operations; and accessing the memory device based on the determined memory access procedure, wherein, if memory access operations are being submitted to the memory device as cached operations, automatically resuming non-cached submissions if the memory access queue becomes empty.
This invention relates to optimizing memory access operations in a data storage system. The problem addressed is inefficient memory access due to suboptimal handling of cached and non-cached operations, which can lead to performance bottlenecks. The solution involves dynamically adjusting memory access procedures based on the fill status of a memory access queue associated with a memory device. The method assesses the current fill status of the memory access queue to determine whether to submit memory access operations as cached or non-cached. Cached operations involve storing data in a cache before accessing the memory device, while non-cached operations directly access the memory device without caching. The decision is made based on the queue's fill status to balance performance and resource utilization. If the queue is full, the system may prioritize cached operations to reduce latency. If the queue becomes empty, the system automatically resumes non-cached submissions to avoid unnecessary caching overhead. This approach ensures efficient memory access by dynamically switching between cached and non-cached operations based on real-time queue conditions, improving overall system performance and resource management. The method is particularly useful in data storage controllers where memory access patterns vary, and optimal performance depends on adaptive access strategies.
29. A data storage controller for use with a memory device, comprising: a queue assessment component configured to determine a fill level of a memory access queue associated with the memory device; a memory access determination component configured to determine a memory access procedure for use in accessing the memory device based on the fill level of the memory access queue; and a memory access controller configured to control access to the memory device based on the determined memory access procedure, wherein the memory access controller comprises a cached read submission controller and a non-cached read submission controller.
This invention relates to data storage controllers designed to optimize memory access in computing systems. The problem addressed is inefficient memory access, which can lead to performance bottlenecks, particularly when handling varying workloads. The invention provides a data storage controller that dynamically adjusts memory access procedures based on the current fill level of a memory access queue associated with the memory device. The controller includes a queue assessment component that monitors the fill level of the memory access queue, which tracks pending memory access operations. A memory access determination component then evaluates this fill level to select an appropriate memory access procedure. The controller further includes a memory access controller that executes the chosen procedure, utilizing either a cached read submission controller or a non-cached read submission controller. The cached read submission controller prioritizes faster access to frequently used data, while the non-cached read submission controller ensures direct access to data not stored in cache, improving overall system efficiency. By dynamically switching between these modes based on queue fill levels, the invention optimizes memory access performance under different workload conditions.
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May 5, 2020
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