Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A display apparatus comprising: a display panel including a plurality of first gate lines; a first gate driver connected to first ends of the plurality of first gate lines; a second gate driver connected to second ends of the plurality of first gate lines; a feedback line connected adjacent to the first end of one of the plurality of first gate lines; and a gate delay sensing circuit connected to the feedback line, wherein the gate delay sensing circuit comprises: a time-to-digital converter which converts an activation time of a feedback gate signal into a digital activation value, wherein the feedback gate signal is retrieved from the feedback line when the first gate driver is enabled and the second gate driver is disabled or when the first gate driver is disabled and the second gate driver is enabled; and a digital comparator which generates a digital delay value based on the digital activation value, wherein the digital delay value indicates a resistive-capacitive delay of the one of the plurality of first gate lines connected to the feedback line.
This invention relates to display apparatuses, specifically addressing the challenge of measuring and compensating for resistive-capacitive (RC) delays in gate lines of display panels. In large-area displays, signal propagation delays along gate lines can degrade performance, causing timing mismatches and display artifacts. The apparatus includes a display panel with multiple gate lines, each driven by a first gate driver at one end and a second gate driver at the opposite end. A feedback line is positioned near one end of a selected gate line to monitor signal propagation. A gate delay sensing circuit, connected to the feedback line, measures the activation time of the feedback gate signal using a time-to-digital converter, converting it into a digital activation value. The circuit also includes a digital comparator that generates a digital delay value representing the RC delay of the monitored gate line. The system operates by enabling one gate driver while disabling the other, allowing the feedback signal to reflect the delay introduced by the gate line. This enables precise measurement of propagation delays, facilitating compensation techniques to improve display uniformity and performance. The invention enhances display quality by dynamically assessing and correcting timing discrepancies caused by RC delays in gate lines.
2. The display apparatus of claim 1 , wherein the time-to-digital converter converts a first activation time of a first feedback gate signal into a first digital activation value by oversampling the first feedback gate signal, wherein the first feedback gate signal is retrieved from the feedback line when the first gate driver is enabled and the second gate driver is disabled, and the time-to-digital converter converts a second activation time of a second feedback gate signal into a second digital activation value by oversampling the second feedback gate signal, wherein the second feedback gate signal is retrieved from the feedback line when the first gate driver is disabled and the second gate driver is enabled.
A display apparatus includes a time-to-digital converter (TDC) that measures activation times of gate signals in a display panel. The apparatus has multiple gate drivers, including at least a first and second gate driver, connected to a feedback line. The TDC converts the activation time of a first feedback gate signal into a first digital value by oversampling the signal when the first gate driver is active and the second gate driver is inactive. Similarly, the TDC converts the activation time of a second feedback gate signal into a second digital value by oversampling the signal when the second gate driver is active and the first gate driver is inactive. This allows precise timing measurements of gate signal activations, which can be used for calibration, synchronization, or fault detection in the display panel. The oversampling technique enhances accuracy by capturing multiple samples of the feedback signals to determine their activation times. The apparatus ensures reliable timing data for display operations by isolating the feedback signals from each gate driver during measurement.
3. The display apparatus of claim 2 , wherein the time-to-digital converter detects the first activation time and outputs a first bit periodically at a predetermined sampling cycle while a voltage level of the first feedback gate signal is higher than a reference voltage level, and the time-to-digital converter detects the second activation time and outputs the first bit periodically at the sampling cycle while a voltage level of the second feedback gate signal is higher than the reference voltage level.
A display apparatus includes a time-to-digital converter (TDC) that detects activation times of feedback gate signals and outputs a digital bit based on voltage comparisons. The TDC monitors a first feedback gate signal and periodically outputs a first bit at a fixed sampling rate when the signal's voltage exceeds a reference voltage. Similarly, the TDC detects a second feedback gate signal and outputs the first bit at the same sampling rate when its voltage exceeds the reference voltage. This mechanism enables precise timing measurements of signal activations, which can be used for display control or synchronization. The TDC's periodic output ensures consistent sampling, allowing the display apparatus to track signal transitions accurately. The reference voltage serves as a threshold to determine when the feedback signals are active, ensuring reliable detection. This approach improves signal processing efficiency in display systems by converting analog voltage levels into digital timing information, facilitating better synchronization and control of display operations. The TDC's operation is independent of the feedback signals' specific waveforms, focusing solely on voltage thresholds and timing. This method enhances the robustness of display timing circuits by standardizing signal detection and output.
4. The display apparatus of claim 2 , wherein the digital comparator compares the first digital activation value with the second digital activation value to generate the digital delay value.
A display apparatus includes a digital comparator that compares two digital activation values to generate a digital delay value. The first digital activation value corresponds to a first activation signal, and the second digital activation value corresponds to a second activation signal. The digital comparator evaluates these values to determine a delay between the signals, which is then used to adjust timing in the display system. This ensures synchronization between different components, such as light sources and scanning elements, to improve display performance. The apparatus may include a digital-to-analog converter to convert the digital delay value into an analog signal for further processing. The system may also incorporate a timing controller to manage signal timing and a light source driver to control light emission based on the adjusted timing. The digital comparator's function is to precisely measure and compensate for timing discrepancies, enhancing display accuracy and reducing artifacts. This technology is particularly useful in high-resolution or high-speed display systems where precise synchronization is critical.
5. The display apparatus of claim 4 , wherein each of the first digital activation value and the digital delay value is represented as a combination of first bits, the second digital activation value is represented as a combination of the first bits and second bits, and a number of the first bits included in the digital delay value is substantially equal to a difference between a number of the first bits included in the first digital activation value and a number of the first bits included in the second digital activation value.
This invention relates to display apparatuses, specifically those that use digital activation and delay values to control display elements. The problem addressed is the efficient representation and processing of these values to optimize display performance while minimizing computational overhead. The apparatus includes a display panel with multiple display elements, each controlled by a driver circuit. The driver circuit generates activation signals based on digital activation values and digital delay values. These values are used to precisely control the timing and intensity of the display elements, ensuring accurate image rendering. The digital activation and delay values are encoded using a combination of first and second bits. The first digital activation value and the digital delay value are each represented using only the first bits, while the second digital activation value uses both first and second bits. The number of first bits in the digital delay value is set to match the difference between the number of first bits in the first digital activation value and the number of first bits in the second digital activation value. This bit allocation ensures efficient data processing and reduces the computational complexity of the driver circuit. By structuring the bit representation in this way, the apparatus achieves precise control over display element activation while minimizing the hardware and processing requirements. This is particularly useful in high-resolution or high-refresh-rate displays where efficient data handling is critical. The invention improves display performance by optimizing the encoding and processing of activation and delay values, leading to more accurate and energy-efficient display operation.
6. The display apparatus of claim 2 , wherein the gate delay sensing circuit further includes: a memory which stores the first digital activation value and the second digital activation value.
A display apparatus includes a gate driver circuit with a gate delay sensing circuit that measures delays in gate signals. The gate delay sensing circuit generates a first digital activation value representing a delay in a first gate signal and a second digital activation value representing a delay in a second gate signal. These digital values are stored in a memory within the gate delay sensing circuit. The stored values can be used to compensate for variations in gate signal timing, ensuring accurate display operation. The apparatus may also include a timing controller that processes the digital activation values to adjust gate signal timing dynamically. This compensation helps maintain uniform display performance, particularly in large or high-resolution displays where signal delays can vary across different regions. The memory allows the apparatus to retain delay measurements for future reference, enabling continuous calibration and optimization of gate signal timing. The invention addresses the problem of signal delay inconsistencies in display panels, which can lead to visual artifacts or performance degradation. By storing and utilizing these delay measurements, the display apparatus can dynamically adjust to maintain consistent image quality.
7. The display apparatus of claim 1 , wherein the gate delay sensing circuit is located inside the first gate driver.
A display apparatus includes a gate driver circuit with a gate delay sensing circuit integrated within it. The apparatus is designed for use in display panels, particularly those requiring precise timing control for gate signals. The problem addressed is the need to accurately measure and compensate for signal delays within the gate driver, which can affect display performance. The gate delay sensing circuit monitors the timing of gate signals as they propagate through the driver, allowing for real-time adjustments to maintain synchronization. This integration reduces the need for external sensing components, simplifying the design and improving reliability. The apparatus may also include additional features such as a timing controller to process the sensed delay data and adjust the gate signals accordingly. The overall goal is to enhance display uniformity and image quality by minimizing timing errors in the gate driver circuit. The invention is particularly useful in high-resolution or high-refresh-rate displays where precise timing is critical.
8. The display apparatus of claim 1 , further comprising: a timing controller configured to compensate the resistive-capacitive delay based on the digital delay value.
A display apparatus includes a timing controller that compensates for resistive-capacitive (RC) delay in the display panel. The apparatus includes a display panel with a plurality of pixels, a data driver configured to supply data signals to the pixels, and a gate driver configured to supply scan signals to the pixels. The timing controller generates a digital delay value based on the RC delay characteristics of the display panel and adjusts the timing of the data and scan signals to compensate for the delay. This compensation ensures accurate synchronization between the data and scan signals, improving display performance. The timing controller may use pre-stored delay compensation values or dynamically calculate the delay based on operating conditions. The apparatus may also include a memory for storing the digital delay values and a compensation circuit to apply the delay compensation to the signals. This technology addresses the problem of signal distortion and timing mismatches in large-area or high-resolution displays, where RC delays can degrade image quality. By dynamically adjusting signal timing, the apparatus maintains consistent display performance across different operating conditions.
9. The display apparatus of claim 1 , wherein the one of the plurality of first gate lines connected to the feedback line is a dummy gate line.
A display apparatus includes a plurality of first gate lines and a feedback line connected to one of the first gate lines. The feedback line provides a feedback signal to a gate driver circuit, which controls the timing of signals applied to the first gate lines. The feedback signal is used to synchronize the gate driver circuit with the display panel's operation, ensuring proper timing for driving the display. In this configuration, the first gate line connected to the feedback line is a dummy gate line, meaning it does not actively drive pixels but is used solely for feedback purposes. This design allows the feedback signal to accurately reflect the timing of the display panel without interfering with the active gate lines that control pixel operation. The dummy gate line ensures that the feedback signal is stable and reliable, improving the overall synchronization of the display apparatus. This approach is particularly useful in high-resolution or high-refresh-rate displays where precise timing is critical. The feedback mechanism helps maintain consistent image quality by compensating for variations in signal propagation delays across the display panel.
10. The display apparatus of claim 1 , wherein the display panel further includes: a plurality of pixels connected to the plurality of first gate lines; and a plurality of data lines connected to the plurality of pixels.
A display apparatus includes a display panel with a plurality of first gate lines and a plurality of second gate lines. The first gate lines are connected to a first gate driver, and the second gate lines are connected to a second gate driver. The first and second gate drivers are configured to sequentially drive the first and second gate lines, respectively, to control the display panel. The display panel further includes a plurality of pixels connected to the first gate lines and a plurality of data lines connected to the pixels. The data lines provide data signals to the pixels, which are activated by the first gate lines to display an image. The apparatus may also include a timing controller that generates control signals for the first and second gate drivers to synchronize the driving of the gate lines. The display panel may be an organic light-emitting diode (OLED) panel or a liquid crystal display (LCD) panel, where the gate lines control the switching of transistors within the pixels to update the displayed image. The apparatus ensures efficient and synchronized driving of the display panel to achieve high-quality image output.
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May 12, 2020
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