Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An apparatus comprising: first and second power converter stages, each power converter stage comprising a primary side and a secondary side; the primary side of the first power converter stage further comprises a switching element T 1 A coupled to a voltage source and a switching element T 3 A coupled to the switching element T 1 A ; the primary side of the second power converter stage further comprises a switching element T 2 A coupled to the switching element T 3 A and a switching element T 4 A coupled to the switching element T 3 A and to the voltage source; and a control circuit configured to control an on/off time of the switching elements, the control circuit comprising: four gate driver controllers, each configured to control the on/off time of one of switching elements T 1 A , T 2 A , T 3 A , and T 4 A ; and a current sharing control section coupled to the gate driver controllers configured to: compare a current through each of multiple output inductors on the secondary sides of the first and second power converter stages to an average current through the multiple output inductors; and as a result of the current through one of the multiple output inductors being greater than the average current, decrease the on time of a corresponding switching element and, as a result of the current through the one of the multiple output inductors being less than the average current, increase the on time of the corresponding switching element.
This invention relates to power conversion systems and addresses the problem of uneven current distribution in multi-output power converters. The apparatus includes two power converter stages, each with a primary and secondary side. The primary side of the first stage has two switching elements, T1A connected to a voltage source, and T3A connected to T1A. The primary side of the second stage also has two switching elements, T2A connected to T3A, and T4A connected to T3A and the voltage source. A control circuit manages the switching elements. This circuit contains four gate driver controllers, each responsible for a specific switching element (T1A, T2A, T3A, T4A). Additionally, a current sharing control section is linked to these controllers. This section monitors the current in multiple output inductors on the secondary sides of both converter stages. It compares each inductor's current to the average current across all output inductors. If an inductor's current exceeds the average, the control circuit reduces the on-time of its corresponding switching element. Conversely, if an inductor's current is below the average, the control circuit increases the on-time of its corresponding switching element. This active adjustment ensures balanced current distribution among the outputs.
2. The apparatus of claim 1 wherein: the four gate driver controllers are further configured to control the on/off time of one of switching elements B 1 , B 2 , B 3 , and B 4 on the secondary sides of the first and second power converter stages, and each gate driver controller is configured to control the on/off time of switching elements T 1 A and B 1 , T 2 A and B 2 , T 3 A and B 3 , and T 4 A and B 4 , respectively, in a complementary manner; and the multiple output inductors comprise output inductors L 1 , L 2 , L 3 , and L 4 , and the current sharing control section is further configured to: as a result of the current through L 1 being greater than the average current, decrease the on time of T 1 A and, as a result of the current through L 1 being less than the average current, increase the on time of T 1 A ; as a result of the current through L 3 being greater than the average current, decrease the on time of T 3 A and, as a result of the current through L 3 being less than the average current, increase the on time of T 3 A ; as a result of the current through L 2 being greater than the average current, decrease the on time of T 2 A and, as a result of the current through L 2 being less than the average current, increase the on time of T 2 A ; and as a result of the current through L 4 being greater than the average current, decrease the on time of T 4 A and, as a result of the current through L 4 being less than the average current, increase the on time of T 4 A .
This invention relates to a power converter system with multiple output inductors and current sharing control for balanced power distribution. The system includes a power converter with primary and secondary stages, where the secondary stage contains switching elements B1, B2, B3, and B4. Four gate driver controllers regulate the on/off timing of these switching elements and their corresponding primary-side counterparts (T1A, T2A, T3A, T4A) in a complementary manner, ensuring synchronized operation. The system also features output inductors L1, L2, L3, and L4, each associated with a respective switching pair. A current sharing control section monitors the current through each inductor and adjusts the on-time of the primary-side switching elements (T1A, T2A, T3A, T4A) to maintain balanced current distribution. If an inductor's current exceeds the average, the control section reduces the on-time of its corresponding primary-side switch, and if the current falls below average, it increases the on-time. This dynamic adjustment ensures uniform power delivery across all output channels, improving efficiency and reliability in multi-output power converter applications.
3. The apparatus of claim 2 wherein the control circuit further comprises a voltage balance control section configured to: compare a sum of currents through L 1 and L 3 to a sum of currents through L 2 and L 4 ; as a result of the sum of currents through L 1 and L 3 being greater than the sum of currents through L 2 and L 4 , increase the on time of T 1 A and T 3 A and decrease the on time of T 2 A and T 4 A ; and as a result of the sum of currents through L 1 and L 3 being less than the sum of currents through L 2 and L 4 , decrease the on time of T 1 A and T 3 A and increase the on time of T 2 A and T 4 A .
This invention relates to power conversion systems, specifically a control circuit for balancing currents in a multi-phase power converter. The problem addressed is uneven current distribution among phases in a converter with multiple inductors, which can lead to inefficiency and overheating. The apparatus includes a control circuit with a voltage balance control section that actively monitors and adjusts current flow to maintain equilibrium. The control circuit compares the sum of currents through two inductors (L1 and L3) against the sum of currents through the other two inductors (L2 and L4). If the sum of currents through L1 and L3 exceeds that of L2 and L4, the control circuit increases the on time of switches T1A and T3A while decreasing the on time of switches T2A and T4A. Conversely, if the sum of currents through L1 and L3 is less than that of L2 and L4, the control circuit decreases the on time of T1A and T3A while increasing the on time of T2A and T4A. This dynamic adjustment ensures balanced current distribution across all phases, improving efficiency and reliability in the power converter.
4. The apparatus of claim 2 wherein: the primary side of the first power converter stage further comprises a capacitor C 1 coupled to switching element T 1 A , and a capacitor C 2 coupled to capacitor C 1 and to the switching element T 3 A ; the primary side of the second power converter stage further comprises a capacitor C 3 coupled to switching element T 2 A , and a capacitor C 4 coupled to capacitor C 3 and to the switching element T 4 A; the transformer of the first power converter stage is coupled to and between a node between the switching elements T 1 A and T 3 A and a node between the capacitors C 1 and C 2 ; and the transformer of the second power converter stage is coupled to and between a node between the switching elements T 2 A and T 4 A and a node between the capacitors C 3 and C 4 .
This invention relates to a multi-stage power converter system designed to improve efficiency and reliability in power conversion applications. The system addresses challenges in traditional power converters, such as voltage regulation, power factor correction, and harmonic distortion, by incorporating multiple converter stages with optimized switching and transformer coupling. The apparatus includes at least two power converter stages, each with a primary side and a secondary side. The primary side of the first converter stage features a capacitor (C1) connected to a switching element (T1A) and another capacitor (C2) coupled between C1 and a second switching element (T3A). Similarly, the primary side of the second converter stage includes a capacitor (C3) connected to a switching element (T2A) and a second capacitor (C4) coupled between C3 and another switching element (T4A). The transformers in each stage are connected between nodes formed by the switching elements and the capacitors, enabling efficient energy transfer and voltage regulation. This configuration allows for independent control of each converter stage, improving overall system performance and reducing losses. The design is particularly useful in applications requiring high efficiency, such as renewable energy systems, electric vehicle charging, and industrial power supplies.
5. The apparatus of claim 4 wherein the control circuit further comprises a voltage balance control section configured to: compare a voltage across capacitors C 3 and C 4 to an input voltage divided by 2; as a result of the voltage across capacitors C 3 and C 4 being less than the input voltage divided by 2, increase the on time of T 1 A and T 3 A and decrease the on time of T 2 A and T 4 A ; and as a result of the voltage across capacitors C 3 and C 4 being greater than the input voltage divided by 2, decrease the on time of T 1 A and T 3 A and increase the on time of T 2 A and T 4 A .
This invention relates to power conversion systems, specifically a control circuit for balancing voltages in a multi-phase converter. The problem addressed is maintaining balanced voltages across capacitors in a power converter to ensure efficient and stable operation. The apparatus includes a control circuit with a voltage balance control section that regulates the on-time of switching transistors (T1A, T3A, T2A, T4A) to maintain equal voltage distribution across capacitors C3 and C4. The control section compares the voltage across C3 and C4 to half of the input voltage. If the capacitor voltage is lower than half the input voltage, the on-time of T1A and T3A is increased while the on-time of T2A and T4A is decreased. Conversely, if the capacitor voltage is higher than half the input voltage, the on-time of T1A and T3A is decreased while the on-time of T2A and T4A is increased. This dynamic adjustment ensures that the voltages across C3 and C4 remain balanced, improving converter efficiency and reliability. The control circuit operates in conjunction with a multi-phase converter, where the switching transistors are part of a bridge configuration that manages power flow and voltage regulation. The invention is particularly useful in applications requiring precise voltage control in power conversion systems.
6. The apparatus of claim 2 wherein: the primary side of the first power converter stage further comprises a switching element T 3 B coupled to the switching element T 1 A , and a switching element T 1 B coupled to the switching element T 3 B and the switching element T 3 A; the primary side of the second power converter stage further comprises a switching element T 4 B coupled to the switching element T 2 A , and a switching element T 2 B coupled to the switching element T 4 B and the switching element T 4 A ; the transformer of the first power converter stage is coupled to and between a node between the switching elements T 1 A and T 3 A and a node between the switching elements T 1 B and T 3 B ; and the transformer of the second power converter stage is coupled to and between a node between the switching elements T 2 A and T 4 A and a node between the switching elements T 2 B and T 4 B ; wherein the gate driver controller that controls T 1 A also controls T 1 B , the gate driver controller that controls T 3 A also controls T 3 B , the gate driver controller that controls T 2 A also controls T 2 B , and the gate driver controller that controls T 4 A also controls T 4 B ; wherein each gate driver controller is configured to control the on/off time of the secondary side n-type MOSFETs in a complementary manner relative to the primary side n-type MOSFETs.
This invention relates to a multi-stage power converter apparatus designed to improve efficiency and control in power conversion systems. The apparatus includes at least two power converter stages, each with a primary side and a secondary side. Each primary side comprises multiple n-type MOSFET switching elements arranged in a specific configuration. The first power converter stage includes switching elements T1A, T3A, T3B, and T1B, where T3B is coupled to T1A, and T1B is coupled to T3B and T3A. Similarly, the second power converter stage includes switching elements T2A, T4A, T4B, and T2B, with T4B coupled to T2A and T2B coupled to T4B and T4A. Each stage also includes a transformer connected between specific nodes of the switching elements. The transformers in the first and second stages are coupled between the nodes formed by T1A-T3A and T1B-T3B, and T2A-T4A and T2B-T4B, respectively. The gate driver controllers manage the switching elements, with each controller for T1A also controlling T1B, and similarly for T3A-T3B, T2A-T2B, and T4A-T4B. The controllers ensure that the secondary side n-type MOSFETs operate in a complementary manner to the primary side MOSFETs, optimizing power conversion efficiency and control. This design enhances synchronization and reduces switching losses in multi-stage power conversion systems.
7. The apparatus of claim 6 wherein: the primary side of the first power converter stage further comprises a capacitor C 1 coupled to the switching elements T 1 A and T 3 A ; and the primary side of the second power converter stage further comprises a capacitor C 2 coupled to the switching elements T 2 A and T 4 A .
A power conversion apparatus includes multiple converter stages with improved switching element configurations. The apparatus addresses inefficiencies in traditional power converters, particularly in high-frequency applications where switching losses and electromagnetic interference (EMI) are significant challenges. The invention focuses on optimizing the primary side of each converter stage to enhance performance and reliability. The apparatus includes at least two power converter stages, each with a primary side containing switching elements and capacitors. In the first converter stage, a capacitor C1 is coupled to switching elements T1A and T3A, while in the second converter stage, a capacitor C2 is coupled to switching elements T2A and T4A. These capacitors help stabilize voltage levels and reduce switching transients, improving efficiency and reducing EMI. The switching elements in each stage are arranged to minimize conduction losses and ensure smooth power transfer. The configuration allows for independent control of each converter stage, enabling flexible power management and dynamic load balancing. The apparatus is particularly useful in applications requiring high efficiency, such as renewable energy systems, electric vehicle charging, and industrial power supplies. The use of dedicated capacitors for each switching pair ensures better voltage regulation and reduces stress on the switching elements, extending their lifespan.
8. The apparatus of claim 7 wherein the control circuit further comprises a voltage balance control section configured to: compare a voltage across capacitor C 2 to an input voltage divided by 2; as a result of the voltage across capacitor C 2 being less than the input voltage divided by 2, increase the on time of T 1 A/B and T 3 A/B and decrease the on time of T 2 A/B and T 4 A/B ; and as a result of the voltage across capacitor C 2 being greater than the input voltage divided by 2, decrease the on time of T 1 A/B and T 3 A/B and increase the on time of T 2 A/B and T 4 A/B .
This invention relates to a power conversion apparatus, specifically a voltage balancing control system for a multi-phase interleaved converter. The problem addressed is maintaining balanced voltages across capacitors in a power converter, particularly in applications where input voltage fluctuations or load variations could cause imbalance, leading to inefficiency or component stress. The apparatus includes a control circuit with a voltage balance control section that actively regulates the voltages across capacitors in a multi-phase converter. The control section compares the voltage across a capacitor (C2) to half of the input voltage. If the capacitor voltage is lower than half the input voltage, the control section increases the on-time of transistors T1A/B and T3A/B while decreasing the on-time of transistors T2A/B and T4A/B. Conversely, if the capacitor voltage is higher than half the input voltage, the control section decreases the on-time of T1A/B and T3A/B while increasing the on-time of T2A/B and T4A/B. This adjustment ensures that the capacitor voltage remains balanced relative to the input voltage, improving converter efficiency and reliability. The transistors (T1A/B, T2A/B, T3A/B, T4A/B) are part of a multi-phase interleaved converter topology, where interleaving helps reduce ripple and improve power delivery. The control circuit dynamically adjusts switching times to maintain optimal voltage distribution across the capacitors, preventing overvoltage or undervoltage conditions. This solution is particularly useful in high-power applications where voltage imbalance could degrade performance or damage components.
9. An apparatus comprising: first and second power converter stages, each power converter stage comprising a transformer that electromagnetically couples a primary side and a secondary side of the power converter stage; the primary side of the first power converter stage further comprises n-type metal oxide semiconductor field effect transistors (MOSFETs) T 1 A and T 3 A , a capacitor C 1 coupled to switching element T 1 A , and a capacitor C 2 coupled to capacitor C 1 and to the switching element T 3 A , wherein the transformer of the first power converter stage is coupled to and between a node between the n-type MOSFETs T 1 A and T 3 A and a node between the capacitors C 1 and C 2 ; the primary side of the second power converter stage further comprises n-type MOSFETs T 2 A and T 4 A , a capacitor C 3 coupled to switching element T 2 A , and a capacitor C 4 coupled to capacitor C 3 and to the switching element T 4 A , wherein the transformer of the second power converter stage is coupled to and between a node between the n-type MOSFETs T 2 A and T 4 A and a node between the capacitors C 3 and C 4 ; the secondary side of the first power converter stage further comprises output inductors L 1 and L 3 coupled to an output load and a first rectifier circuit comprising n-type MOSFETs B 1 and B 3 coupled to and between output inductors L 1 and L 3 , respectively, and ground; and the secondary side of the second power converter stage further comprises output inductors L 2 and L 4 coupled to the output load and a second rectifier circuit comprising n-type MOSFETs B 2 and B 4 coupled to and between the output inductors L 2 and L 4 , respectively, and ground.
This invention relates to a power converter apparatus designed to efficiently convert electrical power with high reliability and performance. The apparatus addresses challenges in power conversion, such as voltage regulation, efficiency, and compactness, by utilizing a multi-stage architecture with interleaved power converter stages. Each stage includes a transformer that electromagnetically couples a primary side and a secondary side, enabling galvanic isolation and efficient power transfer. The primary side of the first power converter stage includes two n-type MOSFETs (T1A and T3A), a capacitor (C1) coupled to T1A, and another capacitor (C2) connected to C1 and T3A. The transformer of this stage is connected between the node linking T1A and T3A and the node between C1 and C2. Similarly, the second power converter stage's primary side features two n-type MOSFETs (T2A and T4A), a capacitor (C3) coupled to T2A, and another capacitor (C4) connected to C3 and T4A. Its transformer is linked between the node joining T2A and T4A and the node between C3 and C4. On the secondary side, the first stage includes output inductors (L1 and L3) connected to an output load and a rectifier circuit with n-type MOSFETs (B1 and B3) coupled between L1 and L3, respectively, and ground. The second stage's secondary side mirrors this structure, with output inductors (L2 and L4) connected to the load and a rectifier circuit featuring n-type MOSFETs (B2 and B4) linked between L2 and L4, respectively, and ground. This configuration ensures balanced power distribution, reduced ripple, and improved efficiency in power conversion applications.
10. The apparatus of claim 9 further comprising a control circuit configured to control the on/off time of the n-type MOSFETs, the control circuit comprising: four gate driver controllers, each configured to control the on/off time of one of: n-type MOSFETs T 1 A and B 1 ; n-type MOSFETs T 3 A and B 3 ; n-type MOSFETs T 2 A and B 2 ; and n-type MOSFETs T 4 A and B 4 ; wherein each gate driver controller is configured to control the on/off time of its associated n-type MOSFETs in a complementary manner; and a current sharing control section coupled to the gate driver controllers configured to: compare a current through each output inductor to an average current through all output inductors; as a result of the current through L 1 being greater than the average current, decrease the on time of T 1 A and, as a result of the current through L 1 being less than the average current, increase the on time of T 1 A ; as a result of the current through L 3 being greater than the average current, decrease the on time of T 3 A and, as a result of the current through L 3 being less than the average current, increase the on time of T 3 A ; as a result of the current through L 2 being greater than the average current, decrease the on time of T 2 A and, as a result of the current through L 2 being less than the average current, increase the on time of T 2 A ; and as a result of the current through L 4 being greater than the average current, decrease the on time of T 4 A and, as a result of the current through L 4 being less than the average current, increase the on time of T 4 A .
This invention relates to power conversion systems, specifically a control circuit for managing current distribution in a multi-phase power converter. The problem addressed is uneven current sharing among parallel power stages, which can lead to inefficiency and overheating. The solution involves a control circuit that dynamically adjusts the on/off times of n-type MOSFETs in a complementary manner to balance currents across multiple output inductors. The control circuit includes four gate driver controllers, each responsible for a pair of n-type MOSFETs (T1A/B1, T3A/B3, T2A/B2, T4A/B4). Each controller operates its MOSFETs in a complementary fashion, ensuring one is on while the other is off. A current sharing control section monitors the current through each output inductor (L1, L2, L3, L4) and compares it to the average current across all inductors. If an inductor's current exceeds the average, the on time of its associated MOSFET (e.g., T1A for L1) is reduced. Conversely, if the current is below average, the on time is increased. This feedback mechanism ensures balanced current distribution, improving efficiency and reliability in multi-phase power converters.
11. The apparatus of claim 10 wherein the control circuit further comprises a voltage balance control section configured to: compare a sum of currents through L 1 and L 3 to a sum of currents through L 2 and L 4 ; as a result of the sum of currents through L 1 and L 3 being greater than the sum of currents through L 2 and L 4 , increase the on time of T 1 A and T 3 A and decrease the on time of T 2 A and T 4 A ; and as a result of the sum of currents through L 1 and L 3 being less than the sum of currents through L 2 and L 4 , decrease the on time of T 1 A and T 3 A and increase the on time of T 2 A and T 4 A .
This invention relates to power conversion systems, specifically a control circuit for balancing currents in a multi-phase power converter. The problem addressed is uneven current distribution among phases in a multi-phase converter, which can lead to inefficiency and component stress. The apparatus includes a control circuit with a voltage balance control section that actively monitors and adjusts current distribution across multiple phases. The control circuit compares the sum of currents flowing through two inductors (L1 and L3) with the sum of currents flowing through two other inductors (L2 and L4). If the sum of currents through L1 and L3 exceeds the sum through L2 and L4, the control circuit increases the on-time of switches T1A and T3A while decreasing the on-time of switches T2A and T4A. Conversely, if the sum through L1 and L3 is less than the sum through L2 and L4, the control circuit decreases the on-time of T1A and T3A while increasing the on-time of T2A and T4A. This dynamic adjustment ensures balanced current distribution, improving efficiency and reducing thermal stress in the converter. The system is particularly useful in high-power applications where precise current control is critical.
12. The apparatus of claim 10 wherein the control circuit further comprises a voltage balance control section configured to: compare a voltage across capacitors C 3 and C 4 to an input voltage divided by 2; as a result of the voltage across capacitors C 3 and C 4 being less than the input voltage divided by 2, increase the on time of T 1 A and T 3 A and decrease the on time of T 2 A and T 4 A ; and as a result of the voltage across capacitors C 3 and C 4 being greater than the input voltage divided by 2, decrease the on time of T 1 A and T 3 A and increase the on time of T 2 A and T 4 A .
This invention relates to power conversion circuits, specifically a control circuit for balancing voltages in a multi-capacitor system. The problem addressed is maintaining equal voltage distribution across capacitors in a power converter, particularly in applications where input voltage fluctuations or load variations could cause imbalance, leading to inefficiency or component stress. The apparatus includes a control circuit with a voltage balance control section that actively monitors and adjusts the voltage across two capacitors (C3 and C4) relative to half of the input voltage. If the combined voltage across C3 and C4 is below half the input voltage, the control circuit increases the on-time of transistors T1A and T3A while decreasing the on-time of transistors T2A and T4A. Conversely, if the voltage across C3 and C4 exceeds half the input voltage, the control circuit reduces the on-time of T1A and T3A and increases the on-time of T2A and T4A. This dynamic adjustment ensures that the voltage across the capacitors remains balanced, improving system stability and efficiency. The control circuit may be part of a larger power conversion system, such as a DC-DC converter or an inverter, where precise voltage regulation is critical. The invention focuses on maintaining balanced capacitor voltages to prevent overvoltage conditions and optimize power delivery.
13. An apparatus comprising: first and second power converter stages, each power converter stage comprising a transformer that electromagnetically couples a primary side and a secondary side of the power converter stage; the primary side of the first power converter stage further comprises n-type metal oxide semiconductor field effect transistors (MOSFETs) T 1 A , T 3 A , T 1 B , and T 3 B and capacitor C 1 , wherein C 1 , the combination of T 1 A and T 3 A , and the combination of T 1 B and T 3 B are arranged in parallel, and wherein the transformer of the first power converter stage is coupled to and between a node between the n-type MOSFETs T 1 A and T 3 A and a node between the n-type MOSFETs T 1 B and T 3 B ; the primary side of the second power converter stage further comprises n-type MOSFETs T 2 A , T 4 A , T 2 B , and T 4 B and capacitor C 2 , wherein C 2 , the combination of T 2 A and T 4 A , and the combination of T 2 B and T 4 B are arranged in parallel, and wherein the transformer of the second power converter stage is coupled to and between a node between the n-type MOSFETs T 2 A and T 4 A and a node between the n-type MOSFETs T 2 B and T 4 B ; the secondary side of the first power converter stage further comprises output inductors L 1 and L 3 coupled to an output load and a first rectifier circuit comprising n-type MOSFETs B 1 and B 3 coupled to and between output inductors L 1 and L 3 , respectively, and ground; and the secondary side of the second power converter stage further comprises output inductors L 2 and L 4 coupled to the output load and a second rectifier circuit comprising n-type MOSFETs B 2 and B 4 coupled to and between the output inductors L 2 and L 4 , respectively, and ground.
This invention relates to a power converter apparatus designed for efficient power conversion with reduced switching losses and improved performance. The apparatus includes two power converter stages, each featuring a transformer that isolates and couples a primary side to a secondary side. Each primary side contains a set of n-type MOSFETs and a capacitor arranged in parallel. Specifically, the first stage includes MOSFETs T1A, T3A, T1B, and T3B, along with capacitor C1, while the second stage includes MOSFETs T2A, T4A, T2B, and T4B, along with capacitor C2. The transformers in each stage are connected between the midpoints of the MOSFET pairs, enabling efficient power transfer. On the secondary side, each stage includes output inductors and a rectifier circuit composed of n-type MOSFETs. The first stage's secondary side has inductors L1 and L3 and MOSFETs B1 and B3, while the second stage's secondary side has inductors L2 and L4 and MOSFETs B2 and B4. The inductors are coupled to a shared output load, and the MOSFETs in the rectifier circuits are connected between the inductors and ground. This configuration allows for synchronized power conversion with minimized switching losses and enhanced efficiency, making it suitable for high-performance power supply applications.
14. The apparatus of claim 13 further comprising a control circuit configured to control the on/off time of the n-type MOSFETs, the control circuit comprising: four gate driver controllers, each configured to control the on/off time of one of: n-type MOSFETs T 1 A , T 1 B , and B 1 ; n-type MOSFETs T 3 A , T 3 B , and B 3 ; n-type MOSFETs T 2 A , T 2 B , and B 2 ; and n-type MOSFETs T 4 A , T 4 B , and B 4 ; wherein each gate driver controller is configured to control the on/off time of the secondary side n-type MOSFETs in a complementary manner relative to the primary side n-type MOSFETs; and a current sharing control section coupled to the gate driver controllers configured to: compare a current through each output inductor to an average current through all output inductors; as a result of the current through L 1 being greater than the average current, decrease the on time of T 1 A and T 1 B and, as a result of the current through L 1 being less than the average current, increase the on time of T 1 A and T 1 B ; as a result of the current through L 3 being greater than the average current, decrease the on time of T 3 A and T 3 B and, as a result of the current through L 3 being less than the average current, increase the on time of T 3 A and T 3 B ; as a result of the current through L 2 being greater than the average current, decrease the on time of T 2 A and T 2 B and, as a result of the current through L 2 being less than the average current, increase the on time of T 2 A and T 2 B ; and as a result of the current through L 4 being greater than the average current, decrease the on time of T 4 A and T 4 B and, as a result of the current through L 4 being less than the average current, increase the on time of T 4 A and T 4 B .
This invention relates to power conversion systems, specifically a control circuit for managing current distribution in a multi-phase power converter using n-type MOSFETs. The system addresses the problem of uneven current sharing among parallel power stages, which can lead to inefficiency and thermal imbalance. The apparatus includes a control circuit that regulates the on/off timing of multiple n-type MOSFETs arranged in primary and secondary side configurations. Each of the four gate driver controllers independently manages a set of MOSFETs, ensuring complementary switching between primary and secondary side devices. A current sharing control section monitors the current through each output inductor and compares it to the average current across all inductors. If a particular inductor's current exceeds the average, the on-time of its associated MOSFETs is reduced, while if it falls below the average, the on-time is increased. This dynamic adjustment ensures balanced current distribution, improving efficiency and reliability in multi-phase power converters. The system is particularly useful in high-power applications where precise current control is critical.
15. The apparatus of claim 14 wherein the control circuit further comprises a voltage balance control section configured to: compare a sum of currents through L 1 and L 3 to a sum of currents through L 2 and L 4 ; as a result of the sum of currents through L 1 and L 3 being greater than the sum of currents through L 2 and L 4 , increase the on time of T 1 A/B and T 3 A/B and decrease the on time of T 2 A/B and T 4 A/B ; and as a result of the sum of currents through L 1 and L 3 being less than the sum of currents through L 2 and L 4 , decrease the on time of T 1 A/B and T 3 A/B and increase the on time of T 2 A/B and T 4 A/B .
This invention relates to power conversion systems, specifically a control circuit for balancing currents in a multi-phase power converter. The problem addressed is uneven current distribution among phases in multi-phase converters, which can lead to inefficiency, overheating, or component stress. The invention provides a voltage balance control section within a control circuit that actively monitors and adjusts current distribution across multiple phases. The control circuit compares the sum of currents flowing through inductors L1 and L3 with the sum of currents flowing through inductors L2 and L4. If the sum of currents through L1 and L3 exceeds the sum through L2 and L4, the control circuit increases the on-time of switching devices T1A/B and T3A/B while decreasing the on-time of T2A/B and T4A/B. Conversely, if the sum of currents through L1 and L3 is less than the sum through L2 and L4, the control circuit decreases the on-time of T1A/B and T3A/B while increasing the on-time of T2A/B and T4A/B. This dynamic adjustment ensures balanced current distribution, improving efficiency and reliability in multi-phase power conversion systems. The switching devices (T1A/B, T2A/B, T3A/B, T4A/B) are likely part of a multi-phase inverter or converter topology, where precise current balancing is critical for optimal performance.
16. The apparatus of claim 14 wherein the control circuit further comprises a voltage balance control section configured to: compare a voltage across capacitor C 2 to an input voltage divided by 2; as a result of the voltage across capacitor C 2 being less than the input voltage divided by 2, increase the on time of T 1 A/B and T 3 A/B and decrease the on time of T 2 A/B and T 4 a/B ; and as a result of the voltage across capacitor C 2 being greater than the input voltage divided by 2, decrease the on time of T 1 A/B and T 3 A/B and increase the on time of T 2 A/B and T 4 A/B .
This invention relates to power conversion systems, specifically a control circuit for balancing voltages in a multi-phase converter. The problem addressed is maintaining balanced voltages across capacitors in a converter circuit, particularly when the input voltage is divided among multiple capacitors. The control circuit includes a voltage balance control section that monitors the voltage across a capacitor (C2) and compares it to half of the input voltage. If the voltage across C2 is lower than half the input voltage, the control circuit increases the on time of transistors T1A/B and T3A/B while decreasing the on time of transistors T2A/B and T4A/B. Conversely, if the voltage across C2 is higher than half the input voltage, the control circuit decreases the on time of T1A/B and T3A/B while increasing the on time of T2A/B and T4A/B. This adjustment ensures that the voltage across C2 remains balanced relative to the input voltage, improving efficiency and stability in the power conversion process. The transistors (T1A/B, T2A/B, T3A/B, T4A/B) are part of a switching network that regulates power flow in the converter, and their on-time adjustments are dynamically controlled to maintain voltage balance. The system is designed for use in power converters where precise voltage regulation is critical, such as in renewable energy systems or high-efficiency power supplies.
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May 12, 2020
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