Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A non-volatile memory, comprising: a plurality of storage elements; a plurality of access transistors, said access transistors being connected to one or more of said storage elements; a measurement unit, wherein said measurement unit is configured to measure a variation between electrical characteristics of said access transistors; a processing unit configured to use said variation between electric characteristics as a physical unclonable function.
This invention relates to non-volatile memory systems incorporating a physical unclonable function (PUF) for security. The problem addressed is the need for secure, unique identification in memory devices to prevent cloning or unauthorized access. The solution involves integrating a PUF directly into the memory architecture by leveraging inherent variations in access transistor electrical characteristics. The memory system includes multiple storage elements and access transistors connected to these elements. A measurement unit is configured to detect variations in electrical properties (e.g., threshold voltage, current) among the access transistors. These variations, which arise naturally during manufacturing due to process imperfections, serve as a unique fingerprint for the device. A processing unit utilizes these variations as a PUF, generating a cryptographic key or identifier that is inherently tied to the physical structure of the memory. By exploiting transistor-level inconsistencies, the system provides a tamper-resistant method for authentication or encryption without requiring additional dedicated PUF circuitry. This approach enhances security while maintaining compatibility with standard memory fabrication processes. The solution is particularly useful in applications where device uniqueness and resistance to cloning are critical, such as secure storage or hardware authentication.
2. The memory of claim 1 , wherein the measurement unit is configured to measure the variation between electrical characteristics by comparing currents through access transistors with the same gate voltage.
This invention relates to semiconductor memory devices, specifically addressing the challenge of accurately measuring variations in electrical characteristics within memory cells. The technology focuses on improving the reliability and performance of memory circuits by detecting and compensating for inconsistencies in transistor behavior. The system includes a memory array with multiple memory cells, each containing access transistors that control data access. A measurement unit is integrated to assess variations in electrical characteristics, such as threshold voltage or current drive, by comparing currents through access transistors under identical gate voltages. This comparison helps identify mismatches or deviations in transistor performance, which can degrade memory accuracy and efficiency. The measurement unit operates by applying a fixed gate voltage to the access transistors and measuring the resulting current flow. By analyzing the differences in current between transistors, the system can detect and quantify variations in electrical behavior. This data is then used to adjust memory operations, such as read or write processes, to compensate for the detected variations, ensuring consistent and reliable memory performance. The invention enhances memory reliability by providing a method to detect and mitigate transistor mismatches, which are common in advanced semiconductor processes due to manufacturing tolerances. This approach improves data integrity and extends the operational lifespan of memory devices.
3. The memory of claim 1 , wherein the measurement unit is configured to measure the variation between electrical characteristics by connecting gate voltages of the access transistors to drain voltages of the access transistors and forcing a predefined current through the access transistors.
This invention relates to semiconductor memory devices, specifically addressing the challenge of accurately measuring variations in electrical characteristics of access transistors in memory cells. The technology involves a memory system with a measurement unit designed to assess differences in electrical properties, such as threshold voltage or current drive capability, among access transistors. The measurement unit operates by connecting the gate voltages of the access transistors to their respective drain voltages while applying a predefined current through the transistors. This configuration allows for precise detection of variations in electrical behavior, which can arise from manufacturing inconsistencies or operational degradation. The system may include a memory array with multiple memory cells, each controlled by an access transistor, and a control circuit to manage the measurement process. The measurement unit's ability to force a specific current through the transistors while monitoring gate-to-drain voltage relationships enables detailed characterization of transistor performance. This approach helps identify and mitigate reliability issues in memory devices, ensuring consistent operation over time. The invention is particularly useful in advanced memory technologies where precise control of transistor behavior is critical for maintaining data integrity and system performance.
4. The memory of claim 1 , wherein the measurement unit is configured to measure the variation between electrical characteristics by comparing, between access transistors, voltages for conducting a predefined current.
This invention relates to semiconductor memory devices, specifically addressing the challenge of accurately measuring variations in electrical characteristics between access transistors in memory cells. The technology focuses on improving the reliability and performance of memory circuits by detecting and compensating for inconsistencies in transistor behavior. The system includes a memory array with multiple memory cells, each containing an access transistor and a storage element. A measurement unit is integrated to evaluate the electrical characteristics of these access transistors. The key innovation lies in the measurement unit's ability to compare the voltages required to conduct a predefined current across different access transistors. By analyzing these voltage variations, the system identifies discrepancies in transistor performance, which can arise from manufacturing imperfections or operational degradation. The measurement unit operates by applying a controlled current to the access transistors and measuring the corresponding voltage drop. The comparison of these voltage values between transistors reveals variations in their electrical properties, such as threshold voltage or on-resistance. This data can then be used to adjust read/write operations, ensuring consistent memory performance. The approach enhances memory reliability by detecting and mitigating transistor mismatches, which are critical for maintaining data integrity in high-density memory arrays. The solution is particularly valuable in advanced semiconductor technologies where process variations are more pronounced.
5. The memory of claim 1 , wherein the electric characteristics are the threshold voltages of the access transistors.
This invention relates to memory systems, specifically addressing the challenge of accurately measuring and utilizing electrical characteristics of access transistors in memory cells to improve performance and reliability. The system includes a memory array with multiple memory cells, each containing an access transistor and a storage element. The access transistors control data access to the storage elements, and their electrical characteristics, particularly threshold voltages, are critical for reliable operation. The system further includes a measurement circuit designed to measure these threshold voltages during operation, ensuring that the transistors function within specified parameters. By monitoring and adjusting the threshold voltages, the system can detect and mitigate issues such as leakage current, voltage drift, or degradation over time. This proactive approach enhances memory stability, reduces errors, and extends the lifespan of the memory device. The measurement circuit may be integrated into the memory controller or as a separate module, allowing for real-time or periodic assessments. The invention is particularly useful in high-density memory applications where precise control of transistor behavior is essential for maintaining data integrity and performance.
6. The memory of claim 1 , wherein the measurement unit is configured to measure a variation between electrical characteristics of a subset of said access transistors.
This invention relates to semiconductor memory devices, specifically addressing the challenge of detecting and mitigating variations in electrical characteristics among access transistors in memory arrays. The technology focuses on improving reliability and performance by monitoring and compensating for inconsistencies in transistor behavior, which can degrade memory functionality over time or due to manufacturing imperfections. The system includes a memory array with multiple access transistors that control data access to memory cells. A measurement unit is integrated to measure variations in electrical characteristics, such as threshold voltage or current drive, among a subset of these transistors. This subset may be selected based on proximity, function, or other criteria to identify localized or systematic deviations. The measured data is used to adjust operating parameters, such as bias voltages or timing, to compensate for detected variations and maintain consistent memory performance. The measurement unit may employ techniques like voltage sensing, current sensing, or parametric testing to quantify differences in transistor behavior. The system can operate dynamically during memory operations or periodically during calibration phases. By detecting and correcting variations early, the invention prevents data errors and extends the lifespan of the memory device. This approach is particularly valuable in high-density memory designs where transistor variability is more pronounced.
7. The memory of claim 6 , wherein said subset is defined in read-only memory, ROM, code.
A system and method for managing memory access in a computing device involves a memory controller that selectively grants or denies access to memory regions based on predefined access rules. The memory is divided into multiple regions, each associated with a set of access permissions. The memory controller includes a permission checker that evaluates access requests against these rules to determine whether to allow or block the request. The system also includes a memory access monitor that tracks access attempts and logs violations for security auditing. The memory regions can be dynamically reconfigured to adjust access permissions in response to changing security requirements. The system is particularly useful in embedded systems or secure environments where strict control over memory access is required to prevent unauthorized data access or tampering. The invention ensures that only authorized processes or users can access specific memory regions, enhancing system security and integrity. The subset of memory regions with restricted access is defined in read-only memory (ROM) code, ensuring that these access rules cannot be altered during runtime, providing an additional layer of security against unauthorized modifications. This approach prevents tampering with critical memory access controls, maintaining the integrity of the system's security policies.
8. The memory of claim 1 , wherein the access transistors are N-type metal-oxide-semiconductor, NMOS, transistors.
This invention relates to semiconductor memory devices, specifically non-volatile memory cells with improved performance and reliability. The problem addressed is the need for efficient, high-density memory cells that maintain data integrity over time while minimizing power consumption and fabrication complexity. The invention describes a memory cell structure where access transistors are N-type metal-oxide-semiconductor (NMOS) transistors, which are integrated into a memory array to control data read and write operations. NMOS transistors are used due to their higher electron mobility compared to P-type transistors, enabling faster switching speeds and lower power consumption. The memory cell includes a storage element, such as a floating gate or charge-trapping layer, that retains data even when power is removed. The NMOS access transistors selectively connect the storage element to bit lines and word lines, allowing controlled access to stored data. This configuration enhances read/write efficiency, reduces leakage current, and improves overall memory reliability. The use of NMOS transistors also simplifies manufacturing processes by leveraging existing CMOS fabrication techniques. The invention is particularly useful in applications requiring high-speed, low-power non-volatile memory, such as embedded systems, solid-state drives, and portable electronics.
9. The memory of claim 1 , wherein the processing unit is further configured to apply redundancy to the measured variation between electrical characteristics.
This invention relates to a system for analyzing and processing electrical characteristics of a semiconductor device to improve reliability and performance. The system measures variations in electrical characteristics, such as voltage, current, or resistance, across different regions of the semiconductor device. These variations can arise from manufacturing inconsistencies, environmental factors, or operational wear. The system includes a processing unit that analyzes these variations to detect anomalies, predict failures, or optimize device performance. To enhance accuracy and robustness, the processing unit applies redundancy to the measured variations. Redundancy involves using multiple measurements, statistical techniques, or error-correction methods to mitigate noise, outliers, or measurement errors. This ensures that the analysis remains reliable even in the presence of fluctuations or disturbances. The system may also include a memory unit to store measurement data, historical trends, or calibration parameters. By applying redundancy, the system improves the reliability of the electrical characteristic analysis, enabling better decision-making for maintenance, calibration, or performance tuning of semiconductor devices. The invention is particularly useful in applications where precise and consistent electrical measurements are critical, such as in integrated circuits, sensors, or power management systems.
10. The memory of claim 9 , wherein applying said redundancy comprises applying an error correction scheme to the measured variation between electrical characteristics.
This invention relates to memory systems that address variations in electrical characteristics, such as resistance or voltage, which can degrade performance or reliability. The problem solved is ensuring data integrity and operational stability in memory devices where such variations occur due to manufacturing imperfections, environmental factors, or wear over time. The invention involves a memory system that measures variations in electrical characteristics of memory cells or components. To compensate for these variations, the system applies a redundancy scheme, specifically an error correction scheme, to the measured variations. This error correction scheme detects and corrects errors caused by the variations, ensuring accurate data storage and retrieval. The redundancy may be applied at different stages, such as during read, write, or refresh operations, to maintain reliability. The error correction scheme may include techniques like error-correcting codes (ECC), parity checks, or other redundancy-based methods. By applying redundancy to the measured variations, the system mitigates the impact of electrical characteristic fluctuations, improving memory reliability and longevity. This approach is particularly useful in non-volatile memory technologies like flash, resistive RAM (ReRAM), or phase-change memory (PCM), where such variations are common. The invention enhances data integrity without requiring significant hardware modifications, making it adaptable to existing memory architectures.
11. The memory of claim 1 , wherein the processing unit is further configured to generate an encryption key based on the physical unclonable function.
A system and method for secure key generation using physical unclonable functions (PUFs) addresses the challenge of generating unique, tamper-resistant cryptographic keys for devices. PUFs leverage inherent manufacturing variations in integrated circuits to produce unpredictable, device-specific outputs that are difficult to replicate. The system includes a processing unit and a memory storing instructions that, when executed, cause the processing unit to generate an encryption key based on the PUF. The PUF provides a unique, hardware-based source of entropy, ensuring that each key is distinct and resistant to cloning or reverse engineering. The processing unit may also perform additional operations, such as storing the generated key in a secure memory location or using it to encrypt or decrypt data. This approach enhances security by eliminating the need for pre-stored keys, reducing vulnerabilities associated with key storage and distribution. The system is particularly useful in applications requiring high security, such as IoT devices, secure authentication, and hardware-based encryption.
12. The memory of claim 1 , wherein each access transistor is connected in series with one or more of said storage elements.
A system for memory storage includes a plurality of storage elements and access transistors, where each access transistor is connected in series with one or more storage elements. The storage elements are configured to store data, and the access transistors control access to the storage elements during read and write operations. The series connection between the access transistors and storage elements allows for efficient data storage and retrieval while minimizing power consumption and improving reliability. This configuration enables high-density memory storage by reducing the number of transistors required per storage element, thereby increasing storage capacity within a given area. The system may be implemented in various memory technologies, including flash memory, DRAM, or other non-volatile memory types, to enhance performance and scalability. The series connection also helps mitigate interference between adjacent storage elements, improving data integrity and reducing errors during read and write operations. The overall design optimizes memory efficiency, making it suitable for high-performance computing, embedded systems, and portable electronic devices.
13. The memory of claim 1 , being a flash memory.
14. A security device comprising the memory of claim 1 .
A security device includes a memory configured to store a plurality of data blocks, where each data block is associated with a unique identifier and a version number. The memory is further configured to store a plurality of access control rules, each rule specifying a set of permissions for accessing a data block based on the unique identifier and version number. The security device also includes a processor configured to receive an access request for a data block, determine the unique identifier and version number of the requested data block, and evaluate the access control rules to determine whether the request complies with the specified permissions. If the request is compliant, the processor grants access to the data block; otherwise, it denies access. The device may also include a communication interface for transmitting and receiving data blocks and access requests, and a user interface for displaying access status and configuration options. The security device ensures secure data access by enforcing version-specific permissions, preventing unauthorized modifications, and maintaining an audit trail of access attempts. This system is particularly useful in environments where data integrity and controlled access are critical, such as financial systems, healthcare records, or enterprise databases.
15. A method of manufacturing a non-volatile memory, comprising: providing the non-volatile memory with a plurality of storage elements; providing the non-volatile memory with a plurality of access transistors, said access transistors being connected to one or more of said storage elements; providing the non-volatile memory with a measurement unit, wherein said measurement unit is configured to measure a variation between electrical characteristics of said access transistors; providing the non-volatile memory with a processing unit, wherein the processing unit is configured to use said variation between electrical characteristics as a physical unclonable function.
This describes a method for manufacturing a non-volatile memory designed with a unique hardware security feature. The process involves constructing the memory with multiple storage elements and access transistors, where each access transistor is connected to one or more storage elements. Crucially, a measurement unit is integrated, configured to detect and quantify natural, subtle variations in the electrical characteristics of these access transistors. Subsequently, a processing unit is provided, configured to use these measured electrical variations as a Physical Unclonable Function (PUF). This enables each manufactured memory to derive a unique, device-specific "fingerprint" from its intrinsic component differences.
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May 19, 2020
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