Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A memory system comprising: a memory device having a plurality of memory regions; and a memory controller configured to generate a read command for a first memory region corresponding to one of the plurality of memory regions when a number of write commands successively generated for the first memory region reaches a reference value, wherein the memory controller includes: a command processing circuit configured to process a command outputted from a host and configured to generate the read command for the first memory region regardless of the host in response to a read command generation control signal; and a write counting circuit configured to output the read command generation control signal to the command processing circuit when the number of the write commands successively generated for the first memory region reaches the reference value.
This invention relates to a memory system designed to improve data integrity and performance by automatically triggering read operations after a certain number of write operations to a specific memory region. The system addresses the problem of data corruption or reliability issues that can arise from repeated write operations to the same memory region without periodic verification. The memory system includes a memory device with multiple memory regions and a memory controller that monitors write operations to these regions. When the number of successive write commands directed to a particular memory region reaches a predefined reference value, the memory controller generates a read command for that region, regardless of any input from the host system. This ensures that the data integrity of the memory region is periodically checked, even if the host does not explicitly request a read operation. The memory controller consists of a command processing circuit that handles commands from the host and generates read commands based on an internal control signal, and a write counting circuit that tracks the number of write operations to each memory region. When the write count for a region reaches the reference value, the write counting circuit sends a control signal to the command processing circuit, triggering the automatic read command. This proactive approach helps maintain data reliability and prevents potential errors caused by excessive write operations.
2. The memory system of claim 1 , wherein the memory device includes a phase change memory (PCM) device.
A memory system is designed to improve data storage efficiency and reliability by incorporating a phase change memory (PCM) device. PCM technology leverages the reversible phase transition between amorphous and crystalline states of a chalcogenide material to store data, offering high density, low power consumption, and non-volatility. The system addresses challenges in traditional memory technologies, such as limited endurance, high power usage, and slow write speeds, by utilizing PCM's unique properties. The PCM device within the memory system enables fast read and write operations while maintaining data integrity over extended use. Additionally, the system may include error correction mechanisms to further enhance reliability, ensuring accurate data retrieval even under varying environmental conditions. The integration of PCM technology allows the memory system to support high-performance computing applications, including data centers, embedded systems, and portable electronics, where energy efficiency and storage density are critical. By combining PCM with other memory components, the system achieves a balanced trade-off between speed, endurance, and power consumption, making it suitable for a wide range of applications.
3. The memory system of claim 1 , wherein the plurality of memory regions include a plurality of memory blocks.
The invention relates to a memory system designed to improve data storage efficiency and reliability. The system addresses the challenge of managing memory resources in a way that optimizes performance while minimizing wear and data loss. The memory system includes multiple memory regions, each containing a plurality of memory blocks. These memory blocks are organized to facilitate efficient data storage and retrieval, ensuring that data is distributed across the system in a manner that balances wear levels and reduces the risk of data loss. The system may also include mechanisms for tracking the usage and health of these memory blocks, allowing for proactive management of storage resources. By dividing memory into distinct blocks within regions, the system can dynamically allocate and reallocate storage space based on usage patterns, improving overall system longevity and reliability. The memory blocks may further support error correction and redundancy features to enhance data integrity. This structured approach to memory organization helps mitigate issues such as uneven wear, data fragmentation, and performance degradation, making the system suitable for applications requiring high durability and consistent performance.
4. The memory system of claim 1 , wherein the plurality of memory regions include a plurality of pages.
The invention relates to a memory system designed to improve data management and access efficiency. The system addresses the challenge of efficiently organizing and retrieving data in memory storage devices, particularly in scenarios where data is stored in discrete regions. The memory system includes multiple memory regions, each containing a plurality of pages. These pages are structured to facilitate organized data storage and retrieval, allowing for better performance and resource utilization. The system may also include mechanisms for managing these pages, such as tracking their usage, allocating new pages, or reclaiming unused pages. By dividing memory into regions and further subdividing them into pages, the system enables more granular control over data storage, reducing fragmentation and improving access times. The invention may be applicable in various storage technologies, including solid-state drives, flash memory, and other non-volatile memory systems. The structured organization of memory regions and pages enhances data integrity, reliability, and overall system efficiency.
5. The memory system of claim 1 , wherein the command processing circuit includes a read command generator that receives the read command generation control signal and an address of the first memory region from the write counting circuit to generate the read command for the first memory region.
The invention relates to a memory system designed to improve data management by dynamically adjusting read operations based on write activity. The system includes a memory controller with a command processing circuit that monitors write operations to specific memory regions. A write counting circuit tracks the frequency of writes to these regions and generates a control signal when a predefined threshold is reached. This signal triggers a read command generator within the command processing circuit to issue a read command for the affected memory region. The read command generator uses the address of the region, provided by the write counting circuit, to target the read operation precisely. This mechanism ensures that frequently written regions are periodically read, which can help maintain data integrity, detect errors, or optimize performance. The system is particularly useful in applications where write-heavy regions may require periodic verification or where read operations need to be synchronized with write activity to prevent data corruption. The invention enhances memory reliability and efficiency by automating the generation of read commands based on real-time write monitoring.
6. The memory system of claim 1 , wherein the command processing circuit transmits both of the command and an address of the first memory region to the write counting circuit and the memory device when the command is generated by the host.
A memory system includes a command processing circuit that manages data storage operations. The system addresses the challenge of efficiently tracking write operations to specific memory regions to prevent excessive wear and ensure data integrity. The command processing circuit generates commands for writing data to a memory device, such as a flash memory, and distributes these commands to both the memory device and a write counting circuit. When a host system issues a write command targeting a first memory region, the command processing circuit transmits both the command and the address of that region to both the write counting circuit and the memory device. The write counting circuit monitors the number of write operations performed on the first memory region, allowing the system to implement wear-leveling techniques or other management strategies. The memory device executes the write operation as directed. This dual transmission ensures that the write counting circuit remains synchronized with the memory device, enabling accurate tracking of write operations and improving the system's reliability and longevity. The system may also include additional circuits for error correction, data encryption, or other memory management functions.
7. The memory system of claim 1 , wherein the write counting circuit includes: a write counting value storage circuit configured to store a counted value of the write commands successively generated for each of the memory regions and configured to change and store a current write counting value for the first memory region into an updated write counting value when the write command for the first memory region is transmitted from the command processing circuit to the write counting value storage circuit; a write counter configured to count the current write counting value outputted from the write counting value storage circuit to generate and output the updated write counting value to the write counting value storage circuit; and a write counting value checker configured to compare the updated write counting value with the reference value and configured to output the read command generation control signal for the first memory region to the command processing circuit when the updated write counting value is equal to the reference value.
This invention relates to a memory system with a write counting circuit that tracks write operations to memory regions and triggers read operations based on a reference value. The system includes a write counting value storage circuit that stores a count of write commands for each memory region. When a write command is issued for a first memory region, the current write count for that region is updated and stored. A write counter increments this count to generate an updated value, which is then compared to a predefined reference value by a write counting value checker. If the updated count matches the reference value, the checker outputs a signal to a command processing circuit, instructing it to generate a read command for the first memory region. This mechanism ensures that read operations are performed at specific intervals, which can be useful for wear leveling, data validation, or other memory management tasks. The system dynamically adjusts write counts and triggers actions based on usage patterns, improving memory reliability and performance. The write counting circuit operates independently for each memory region, allowing fine-grained control over read operations.
8. The memory system of claim 7 , wherein the write counting circuit further includes a write counting value reset circuit that outputs a reset signal for the first memory region when the read command for the first memory region is transmitted from the command processing circuit to the write counting value reset circuit; and wherein the write counting value storage circuit is configured to reset a write counting value for the first memory region when the reset signal is transmitted from the write counting value reset circuit to the write counting value storage circuit.
A memory system includes a write counting circuit that tracks write operations to memory regions. The system monitors write counts to determine when data in a memory region may need to be refreshed or relocated due to wear. The write counting circuit includes a write counting value storage circuit that maintains a count of write operations for each memory region. When a read command is issued for a specific memory region, a write counting value reset circuit generates a reset signal for that region. The reset signal causes the write counting value storage circuit to reset the write count for the memory region, effectively clearing the accumulated write operations. This reset mechanism ensures that the write count accurately reflects only recent write activity, preventing excessive wear-leveling operations or unnecessary data refreshes based on outdated write counts. The system improves memory reliability by dynamically adjusting write tracking based on read operations, reducing unnecessary wear-leveling overhead while maintaining accurate wear monitoring.
9. The memory system of claim 1 , wherein the memory controller further includes an error correction code (ECC) circuit that detects and corrects erroneous data during a read operation of the memory device.
The invention relates to a memory system with enhanced error detection and correction capabilities. The system includes a memory controller that manages data storage and retrieval operations for a memory device, such as a flash memory or other non-volatile storage. A key challenge in memory systems is ensuring data integrity, particularly as storage densities increase and error rates rise. The memory controller includes an error correction code (ECC) circuit designed to identify and fix errors in data during read operations. The ECC circuit applies error detection algorithms to locate corrupted data and correction algorithms to restore the original information. This ensures reliable data retrieval even when errors occur due to wear, manufacturing defects, or environmental factors. The memory controller may also include additional features, such as wear-leveling mechanisms to distribute write operations evenly across the memory device, reducing the likelihood of localized errors. The ECC circuit operates transparently during read operations, automatically verifying and correcting data before it is returned to the requesting system. This improves system reliability and extends the lifespan of the memory device by mitigating the impact of errors. The invention is particularly useful in high-density storage applications where error rates are higher and data integrity is critical.
10. The memory system of claim 9 , wherein the ECC circuit includes: an ECC encoder configured to generate codeword-type write data including original write data and parity data during a write operation of the memory device; and an ECC decoder configured to detect and correct codeword-type read data outputted from the memory device during the read operation.
The invention relates to a memory system with an error correction code (ECC) circuit designed to enhance data integrity in memory devices. The system addresses the problem of data corruption during read and write operations, which can occur due to noise, wear, or other disturbances in memory storage. The ECC circuit includes an encoder and a decoder to mitigate these issues. The encoder generates codeword-type write data by appending parity data to original write data during a write operation, ensuring that the stored data is protected. The decoder then processes codeword-type read data outputted from the memory device during a read operation, detecting and correcting errors to restore the original data accurately. This dual-function ECC circuit improves reliability by actively correcting errors introduced during storage and retrieval, making it particularly useful in high-reliability memory applications such as solid-state drives, embedded systems, and other storage solutions where data integrity is critical. The system ensures that data remains accurate over time, even in the presence of environmental or operational disturbances.
11. A memory system comprising: a memory device having a plurality of memory regions; and a memory controller configured to generate a read command for data stored in a first memory region corresponding to one of the plurality of memory regions whenever a write command for the first memory region is generated from a point of time that a number of the write command repeatedly generated for the first memory region is equal to or greater than a reference value, wherein the memory controller includes: a command processing circuit configured to process a command outputted from a host and configured to generate the read command for the first memory region regardless of the host in response to a read command generation control signal; and a write counting circuit configured to output the read command generation control signal to the command processing circuit whenever the write command for the first memory region is generated when the number of the write command repeatedly generated for the first memory region is equal to or greater than the reference value.
The invention relates to a memory system designed to mitigate data retention issues in non-volatile memory devices, particularly in regions frequently subjected to write operations. The system includes a memory device with multiple memory regions and a memory controller that monitors write operations to these regions. When the number of write commands directed to a specific memory region reaches or exceeds a predefined threshold, the memory controller automatically generates a read command for that region, regardless of any host request. This proactive read operation helps verify data integrity and refreshes the memory cells, counteracting wear and retention degradation caused by repeated writes. The memory controller comprises a command processing circuit that executes commands from a host and generates the read command in response to an internal control signal, and a write counting circuit that tracks write operations to each memory region. When the write count for a region meets or exceeds the threshold, the write counting circuit triggers the read command generation control signal, ensuring periodic data validation and refresh without host intervention. This approach extends the lifespan of frequently written memory regions by proactively addressing potential data corruption risks.
12. The memory system of claim 11 , wherein the memory device includes a phase change memory (PCM) device.
A memory system is designed to improve data storage efficiency and reliability in computing systems. The system addresses challenges related to power consumption, data retention, and performance in traditional memory technologies. The memory system includes a memory device that utilizes phase change memory (PCM) technology. PCM devices store data by altering the physical state of a chalcogenide material between amorphous and crystalline phases, which correspond to different electrical resistances. This allows for non-volatile storage with fast read/write speeds and high density. The system may also incorporate additional memory devices, such as dynamic random-access memory (DRAM) or static random-access memory (SRAM), to optimize performance for different types of data access patterns. The integration of PCM with other memory types enables a hybrid storage solution that balances speed, endurance, and energy efficiency. The system may further include a controller to manage data operations, ensuring efficient use of the memory resources and maintaining data integrity. This approach enhances overall system performance while reducing power consumption and improving reliability.
13. The memory system of claim 11 , wherein the plurality of memory regions include a plurality of memory blocks.
A memory system is designed to manage data storage and retrieval in a non-volatile memory device, such as a flash memory or solid-state drive (SSD). The system addresses challenges related to wear leveling, data integrity, and efficient memory utilization by organizing data into distinct memory regions. Each memory region is further divided into multiple memory blocks, which are the smallest individually erasable units within the memory device. This hierarchical structure allows the system to distribute write and erase operations evenly across the memory blocks, extending the lifespan of the memory device. The system also includes mechanisms to track the usage and health of each memory block, enabling dynamic adjustments to optimize performance and reliability. By segmenting the memory into blocks, the system can efficiently handle data operations, reduce fragmentation, and maintain consistent performance over time. The memory blocks may be organized in a way that supports different types of data storage, such as user data, metadata, or system information, ensuring efficient access and management. This approach helps mitigate issues like write amplification and uneven wear, which are common in non-volatile memory systems. The system may also include error correction and redundancy features to enhance data durability. Overall, the memory system provides a robust framework for managing memory resources in non-volatile storage devices, improving longevity and reliability.
14. The memory system of claim 11 , wherein the plurality of memory regions include a plurality of pages.
A memory system is designed to manage data storage and retrieval in a non-volatile memory device, such as a flash memory. The system addresses challenges related to efficient data organization, wear leveling, and performance optimization in memory operations. The memory system includes a controller that dynamically allocates and manages multiple memory regions, each containing a plurality of pages. These pages are logical units of storage that can be individually read, programmed, or erased. The controller ensures that data is distributed across the memory regions to balance wear and improve endurance. The system may also include error correction mechanisms to detect and correct data errors, enhancing reliability. The memory regions and pages are structured to support efficient addressing and access, allowing the controller to optimize read and write operations. The system may further include mechanisms for garbage collection, where invalid or obsolete data is identified and removed to free up space for new data. The overall design aims to improve the lifespan, performance, and reliability of the memory device by intelligently managing the storage space and data distribution.
15. The memory system of claim 11 , wherein the command processing circuit includes a read command generator that receives the read command generation control signal and an address of the first memory region from the write counting circuit to generate the read command for the first memory region.
The invention relates to a memory system designed to manage data storage and retrieval efficiently, particularly in scenarios where write operations are frequent and may lead to data corruption or loss. The system includes a write counting circuit that monitors write operations to a first memory region and generates a read command generation control signal when a predetermined number of write operations is detected. This signal triggers a command processing circuit to initiate a read operation of the first memory region, ensuring data integrity by verifying or recovering data after repeated writes. The command processing circuit includes a read command generator that receives the control signal and the address of the first memory region from the write counting circuit to produce a read command specifically targeting that region. This mechanism helps prevent data corruption by periodically checking or refreshing data in heavily written memory areas, improving reliability in systems where frequent writes are common, such as in logging or temporary storage applications. The system may also include additional circuits for error detection, correction, or data migration to further enhance data integrity.
16. The memory system of claim 11 , wherein the command processing circuit transmits both of the command and an address of the first memory region to the write counting circuit and the memory device when the command is generated by the host.
A memory system includes a command processing circuit that manages data storage operations in a memory device. The system addresses inefficiencies in tracking write operations to memory regions, which can lead to premature wear or data loss. The command processing circuit generates commands for writing data to a first memory region and transmits both the command and the address of the first memory region to a write counting circuit and the memory device. The write counting circuit monitors write operations to track usage and wear of memory regions, ensuring balanced wear leveling and preventing data loss. The memory device executes the write command to store data in the specified memory region. This approach improves reliability by maintaining accurate write counts and ensuring commands are properly routed to both the memory device and the write counting circuit. The system may also include additional circuits for error correction, data encryption, or other memory management functions to enhance performance and durability. The invention optimizes memory usage by dynamically adjusting write operations based on wear leveling data, extending the lifespan of the memory device.
17. The memory system of claim 11 , wherein the write counting circuit includes: a write counting value storage circuit configured to store a counted value of the write commands generated for each of the memory regions and configured to change and store a current write counting value for the first memory region into an updated write counting value when the write command for the first memory region is transmitted from the command processing circuit to the write counting value storage circuit; a write counter configured to count the current write counting value outputted from the write counting value storage circuit to generate and output the updated write counting value to the write counting value storage circuit; and a write counting value checker configured to compare the updated write counting value with the reference value and configured to output the read command generation control signal for the first memory region to the command processing circuit when the updated write counting value is equal to or greater than the reference value.
This invention relates to a memory system with a write counting circuit that monitors write operations to memory regions and triggers read operations based on write frequency. The system addresses the problem of wear leveling and data integrity in non-volatile memory by tracking write counts for each memory region and initiating read operations when a predefined threshold is reached. The write counting circuit includes a storage circuit that maintains a write count for each memory region, updating the count when a write command is issued. A write counter increments the current count and outputs an updated value to the storage circuit. A checker compares the updated count against a reference value and generates a control signal to trigger a read command when the count meets or exceeds the threshold. This ensures that frequently written regions are periodically read to maintain data accuracy and extend memory lifespan. The system dynamically adjusts read operations based on write activity, improving efficiency and reliability in memory management.
18. The memory system of claim 11 , wherein the memory controller further includes an error correction code (ECC) circuit that detects and corrects erroneous data during a read operation of the memory device.
The invention relates to memory systems, specifically addressing the need for reliable data storage and retrieval in memory devices. The system includes a memory controller that manages data operations between a host device and a memory device, such as a flash memory. A key feature is the memory controller's ability to perform wear leveling, which distributes write and erase operations evenly across memory blocks to extend the lifespan of the memory device. The controller also handles garbage collection, reclaiming invalid data blocks to maintain storage efficiency. Additionally, the memory controller includes an error correction code (ECC) circuit that detects and corrects erroneous data during read operations, ensuring data integrity. The ECC circuit identifies errors in the retrieved data and applies correction algorithms to restore the original information, mitigating the impact of data corruption. This combination of wear leveling, garbage collection, and ECC functionality enhances the reliability, longevity, and performance of the memory system. The invention is particularly useful in storage applications where data durability and error resilience are critical.
19. The memory system of claim 18 , wherein the ECC circuit includes: an ECC encoder configured to generate codeword-type write data including original write data and parity data during a write operation of the memory device; and an ECC decoder configured to detect and correct codeword-type read data outputted from the memory device during the read operation.
This invention relates to memory systems with error correction capabilities, specifically addressing data integrity issues in memory devices. The system includes a memory device and an error correction code (ECC) circuit designed to enhance reliability by detecting and correcting errors in stored data. The ECC circuit comprises an ECC encoder and an ECC decoder. During a write operation, the ECC encoder generates codeword-type write data by appending parity data to the original write data, ensuring that errors can be detected and corrected later. During a read operation, the ECC decoder processes codeword-type read data outputted from the memory device, identifying and correcting any errors present. This dual-function ECC circuit improves data accuracy and system reliability by actively managing errors during both write and read operations. The system is particularly useful in applications where data integrity is critical, such as in storage devices, embedded systems, and high-reliability computing environments. The invention focuses on integrating efficient error correction mechanisms directly into the memory system to mitigate data corruption risks.
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May 26, 2020
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