Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A computer processor comprising: a memory unit configured to store key values to be sequentially sorted; a processor cache configured to obtain tree data from the memory unit indicating the key values; a hardware merge sort accelerator in signal communication with the memory unit and the processor cache, the merge sort accelerator configured to: generate a master tournament tree based on the key values; perform a tournament sort that determines a first winning key value based on the master tournament tree; and speculate a second winning key value based on the master tournament tree, wherein the speculated second winning key value is a next sequential winning key value of the tournament sort, wherein a first portion of tournament results is stored in the processor cache while a second portion of the tournament results is excluded from the processor cache.
This invention relates to a computer processor with a specialized hardware merge sort accelerator designed to improve sorting efficiency. The processor includes a memory unit storing key values to be sorted sequentially, a processor cache for retrieving tree data representing these key values, and a hardware merge sort accelerator connected to both. The accelerator generates a master tournament tree from the key values and performs a tournament sort to determine the first winning key value. It also speculates the next sequential winning key value based on the same tournament tree, allowing for faster sorting by predicting subsequent results. The processor cache stores a portion of the tournament results while excluding another portion, optimizing cache usage and reducing latency. This approach enhances sorting performance by leveraging hardware acceleration and speculative execution, minimizing the need for repeated memory access and improving overall processing speed. The system is particularly useful in applications requiring high-speed data sorting, such as database management and real-time data processing.
2. The computer processor of claim 1 , wherein each key value represents a numeral including a plurality of digits, and wherein the merge sort accelerator performs the tournament sort by performing a first tournament to determine a first digit of an overall winning key value and using the master tournament tree to speculate a first digit of the next sequential winning key value in parallel with determining the first digit of the overall winning key value.
This invention relates to a computer processor with a merge sort accelerator that optimizes the sorting of key values representing multi-digit numerals. The problem addressed is the inefficiency in traditional merge sort algorithms when processing large datasets with multi-digit numerical keys, particularly in determining the next winning key value in a tournament sort. The merge sort accelerator includes a master tournament tree that enables parallel processing of key comparisons. The system performs a first tournament to determine the first digit of the overall winning key value while simultaneously speculating the first digit of the next sequential winning key value using the master tournament tree. This parallel processing reduces latency by predicting the next winning key value before the current one is fully resolved. The accelerator also includes a plurality of tournament trees, each configured to compare key values and propagate results through the master tournament tree to determine the winning key value. The system further includes a digit comparator that compares digits of key values at each level of the tournament trees, ensuring accurate sorting of multi-digit numerals. The accelerator dynamically adjusts the tournament trees based on the number of key values being sorted, optimizing performance for varying dataset sizes. This approach enhances sorting efficiency by leveraging parallel digit comparisons and speculative execution.
3. The computer processor of claim 2 , wherein the merge sort accelerator determines the first portion of the tournament results based on a winning digit of a particular match between a first digit of a first key value and a first digit of a second key value different from the first key value.
This invention relates to a computer processor with a merge sort accelerator that optimizes sorting operations by leveraging tournament-based comparisons of digit values. The problem addressed is the computational inefficiency of traditional merge sort algorithms, particularly in handling large datasets where repeated comparisons of key values consume significant processing resources. The merge sort accelerator includes a tournament circuit that compares digit values from multiple key values in parallel, reducing the number of sequential comparisons needed. Specifically, the accelerator determines a portion of the tournament results by identifying a winning digit from a match between the first digit of a first key value and the first digit of a second key value. This winning digit is used to guide subsequent sorting decisions, improving efficiency by minimizing redundant comparisons. The accelerator further includes a digit selection circuit that selects digits from key values for comparison, ensuring that only relevant digits are processed. A tournament circuit performs parallel comparisons of these digits, generating results that indicate which key values have higher or lower digit values. These results are then used to determine the relative ordering of the key values, accelerating the merge sort process. The invention also includes a control circuit that manages the flow of data and operations within the accelerator, ensuring that comparisons are performed in the correct sequence and that results are properly utilized. This control circuit coordinates the digit selection, comparison, and result processing stages to optimize performance. By integrating these components, the merge sort accelerator significantly reduces the time and computational overhead associate
4. The computer processor of claim 3 , wherein the merge sort accelerator determines the winning digit as a lowest value among a comparison between digits of the first and second key values of a given match.
The invention relates to a hardware-accelerated merge sort system designed to improve the efficiency of sorting operations in computing systems. The system addresses the computational overhead and latency associated with traditional software-based merge sort algorithms, particularly in high-performance applications requiring rapid data processing. The merge sort accelerator is a specialized hardware component integrated into a computer processor to expedite the comparison and merging of key values during the merge sort process. It operates by comparing pairs of key values from two input streams and determining the smaller value, which is then selected as the "winning digit." This hardware-accelerated comparison reduces the time required for sorting operations by offloading the task from the general-purpose CPU. The accelerator includes a comparator circuit that evaluates the digits of the first and second key values in a given match. The winning digit is identified as the lowest value among the compared digits, ensuring correct ordering. This digit selection process is repeated iteratively to merge the sorted key values efficiently. The system may also include additional components, such as a digit selector and a merge controller, to manage the flow of data and coordinate the sorting operations. By integrating this hardware accelerator into the processor, the invention enhances sorting performance, particularly in applications involving large datasets or real-time processing requirements. The accelerator minimizes software overhead and leverages parallel processing capabilities to achieve faster sorting times compared to traditional software implementations.
5. The computer processor of claim 4 , wherein the merge sort accelerator determines the overall winning key value of the first tournament by selecting a key value from the tournament results and performing a plurality of passes through the master tournament tree using the selected key value.
This invention relates to a merge sort accelerator for optimizing key value selection in a tournament-based sorting process. The problem addressed is the computational inefficiency in determining the overall winning key value from multiple tournament results in a merge sort operation. Traditional methods require multiple comparisons and passes through the data, leading to increased processing time and resource usage. The merge sort accelerator includes a tournament tree structure that processes multiple key values in parallel. The accelerator determines the overall winning key value by selecting a key value from the tournament results and performing multiple passes through a master tournament tree using the selected key value. The master tournament tree is a hierarchical structure that compares key values in stages, progressively narrowing down the candidates to identify the highest or lowest key value. The accelerator uses the selected key value to traverse the master tournament tree, comparing it against stored key values at each level to determine the final winning key value. This approach reduces the number of comparisons and passes required, improving the efficiency of the merge sort operation. The invention also includes a method for updating the master tournament tree with new key values, ensuring the tree remains current for subsequent sorting operations. The accelerator dynamically adjusts the tree structure based on the incoming key values, maintaining optimal performance. This solution is particularly useful in high-performance computing environments where fast and efficient sorting of large datasets is critical.
6. The computer processor of claim 5 , wherein the processor cache is located separately and externally from the merge sort accelerator, and wherein the overall winning key value and the speculated second winning key value are stored in parallel from the merge sort accelerator to the memory unit.
This invention relates to a computer processor system designed to optimize merge sort operations by using a dedicated processor cache and a merge sort accelerator. The system addresses inefficiencies in traditional merge sort implementations, particularly in handling key comparisons and data movement between memory and processing units. The merge sort accelerator performs parallel processing of key values to determine the overall winning key value and a speculated second winning key value. These values are then stored in parallel from the merge sort accelerator to a memory unit, reducing latency and improving throughput. The processor cache is located separately and externally from the merge sort accelerator, allowing for independent operation and efficient data access. This separation ensures that the cache can handle other processing tasks while the merge sort accelerator focuses on sorting operations. The system enhances performance by minimizing data transfer bottlenecks and leveraging parallel processing to accelerate sorting tasks. The invention is particularly useful in high-performance computing environments where efficient data sorting is critical.
7. The computer processor of claim 6 , wherein the overall winning key value and the speculated second winning key value are automatically stored sequentially with respect to one another.
This invention relates to a computer processor system for managing and storing key values in a secure and efficient manner. The system addresses the challenge of accurately tracking and storing multiple winning key values, particularly in scenarios where a primary winning key value and a secondary speculated winning key value need to be recorded in a specific sequence. The processor includes a mechanism to automatically store these key values sequentially, ensuring that the overall winning key value and the speculated second winning key value are recorded in a predefined order. This sequential storage helps maintain data integrity and consistency, especially in applications where the order of key values is critical, such as in financial transactions, cryptographic operations, or competitive gaming systems. The system may also include additional features to validate and verify the key values before storage, ensuring that only valid and authorized key values are recorded. The invention improves upon existing systems by automating the storage process, reducing the risk of errors, and enhancing the reliability of key value management.
8. A computer-implemented method of sorting a plurality of data values stored in a hardware computer processor, the method comprising: storing, in a memory unit of the computer processor, key values to be sequentially sorted with respect to one another; obtaining, via a processor cache, tree data from the memory unit indicating the key values; generating, via a hardware merge sort accelerator, a master tournament tree based on the key values; and generating, via the merge sort accelerator, a master tournament tree based on the key values; and performing, via the merge sort accelerator, a tournament sort that determines a first winning key value based on the master tournament tree and speculates a second winning key value based on the master tournament tree, wherein the speculated second winning key value is a next sequential winning key value of the tournament sort; and storing a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.
This invention relates to a hardware-accelerated sorting method for efficiently organizing data values in a computer processor. The method addresses the computational overhead and latency associated with traditional software-based sorting algorithms by leveraging specialized hardware components to enhance performance. The system stores key values in a memory unit of the processor, which are then retrieved via a processor cache. A hardware merge sort accelerator generates a master tournament tree based on these key values. The accelerator performs a tournament sort, determining a first winning key value and speculating a second winning key value as the next sequential result. This speculative approach allows for faster processing by predicting subsequent outcomes. The method stores a portion of the tournament results in the processor cache while excluding another portion, optimizing memory usage and reducing access latency. The hardware-accelerated approach minimizes software intervention, improving sorting efficiency and throughput for large datasets. The invention is particularly useful in high-performance computing environments where rapid data organization is critical.
9. The method of claim 8 , further comprising: representing each key value as a numeral that includes a plurality of digits, wherein performing the tournament sort further comprises: executing a first tournament to determine a first digit of an overall winning key value; and using the master tournament tree to speculate a first digit of the next sequential winning key value in parallel with determining the first digit of the overall winning key value.
This invention relates to optimizing key value sorting in database systems, particularly for improving the efficiency of tournament sorting algorithms. The problem addressed is the computational overhead in determining the next winning key value during sorting operations, which can slow down query processing in large-scale databases. The method involves representing each key value as a multi-digit numeral. During the tournament sort, a first tournament is executed to determine the first digit of the overall winning key value. Simultaneously, a master tournament tree is used to speculate the first digit of the next sequential winning key value. This parallel processing reduces latency by predicting the next result while the current result is being finalized, improving throughput in sorting operations. The master tournament tree is a hierarchical structure that tracks partial results from multiple sub-tournaments, allowing early speculation of subsequent digits. By leveraging this structure, the system can precompute potential outcomes, minimizing delays when transitioning between key values. This approach is particularly useful in high-performance database environments where sorting speed directly impacts query response times. The technique ensures efficient digit-by-digit comparison while maintaining accuracy in the sorting process.
10. The method of claim 9 , wherein the first portion of the tournament results is based on a winning digit of a particular match between a first digit of a first key value and a first digit of a second key value different from the first key value.
A method for generating tournament results in cryptographic operations, particularly for key comparison or selection processes, involves determining outcomes based on digit-wise comparisons between two distinct key values. The method focuses on evaluating a specific match between the first digits of the first and second key values to derive a winning digit, which contributes to the first portion of the tournament results. This approach is useful in scenarios requiring efficient key comparison, such as in cryptographic protocols or secure multi-party computations, where partial results from digit-level comparisons are aggregated to produce final outcomes. The method ensures that the comparison process is deterministic and based on predefined rules, allowing for secure and verifiable results. The technique may be applied in systems where key values are compared in a tournament-style structure, with intermediate results derived from individual digit matches. The method enhances security and efficiency by leveraging digit-level comparisons to reduce computational overhead while maintaining accuracy in key evaluation.
11. The method of claim 10 , wherein determining the winning digit is based on a lowest value among a comparison between digits of the first and second key values of a given match.
This invention relates to a method for determining a winning digit in a cryptographic or data processing system where two key values are compared. The problem addressed is efficiently identifying a specific digit from two key values when a match occurs between them. The method involves comparing corresponding digits of the first and second key values during a match event. The winning digit is selected based on the lowest value among the compared digits of the first and second key values. This ensures a deterministic and consistent selection process when multiple digits are involved. The method may be part of a larger cryptographic or data validation process where key comparison is critical, such as in authentication, encryption, or secure communication protocols. The approach optimizes performance by minimizing computational overhead while ensuring accuracy in digit selection. The technique is particularly useful in systems requiring fast and reliable key validation, such as blockchain, digital signatures, or secure transaction processing. The method ensures that the winning digit is consistently chosen based on predefined criteria, enhancing security and reliability in key-based operations.
12. The method of claim 11 , further comprising determining the overall winning key value of the first tournament by selecting a key value from the tournament results and performing a plurality of passes through the master tournament tree using the selected key value.
This invention relates to a method for optimizing key value selection in a tournament-based sorting or searching algorithm. The problem addressed is improving the efficiency of determining the optimal key value in a master tournament tree, which is a hierarchical structure used to compare and select key values in multiple passes. The method involves conducting a tournament to generate tournament results, then refining the selection by performing multiple passes through the master tournament tree using a selected key value from the tournament results. This iterative process ensures that the most optimal key value is identified, enhancing the performance of sorting or searching operations. The technique is particularly useful in systems where rapid and accurate key value determination is critical, such as in database indexing, real-time data processing, or competitive sorting algorithms. By leveraging the master tournament tree and iterative passes, the method reduces computational overhead while improving the accuracy of key value selection. The approach can be applied in various computational environments where hierarchical comparisons are used to manage and process large datasets efficiently.
13. The method of claim 12 , wherein determining the overall winning key value of the first tournament includes selecting a key value from the tournament results and performing a plurality of passes through the master tournament tree using the selected key value.
This invention relates to a method for determining an overall winning key value in a tournament-based selection process, particularly in systems requiring efficient and accurate key value selection from a large dataset. The problem addressed is the computational inefficiency and potential inaccuracy in traditional tournament selection methods, which may struggle with scalability and optimal key value determination. The method involves a multi-pass approach to refine the selection of a key value from tournament results. Initially, a tournament tree structure is used to compare and rank key values through multiple rounds of competition. After generating tournament results, a key value is selected from these results. The selected key value is then used to perform multiple passes through a master tournament tree. Each pass refines the selection process, ensuring that the final winning key value is both accurate and computationally efficient. This iterative refinement helps avoid suboptimal selections that might occur in a single-pass approach. The method is particularly useful in applications requiring robust and efficient key value selection, such as data processing, optimization algorithms, or machine learning systems where tournament-based selection is employed. By leveraging multiple passes through the master tournament tree, the method improves the reliability and performance of the selection process.
14. The method of claim 13 , further comprising: storing the overall winning key value and the speculated second winning key value in parallel from the merge sort accelerator to the memory unit; and updating the memory unit in response to the storing such that the overall winning key value and the speculated second winning key value are automatically stored sequentially with respect to one another.
In the field of data processing, particularly in systems requiring efficient sorting and key value management, a challenge exists in optimizing the storage and retrieval of sorted key values, especially when dealing with high-speed merge operations. Traditional methods often suffer from inefficiencies in handling multiple winning key values during merge sort operations, leading to delays and increased computational overhead. This invention addresses this problem by providing a method for storing and updating key values in a memory unit during a merge sort operation. The method involves using a merge sort accelerator to process key values and identify an overall winning key value and a speculated second winning key value. These values are then stored in parallel from the merge sort accelerator to the memory unit. The memory unit is updated in response to this storage operation, ensuring that the overall winning key value and the speculated second winning key value are automatically stored sequentially with respect to one another. This sequential storage enhances data integrity and reduces the need for additional processing steps, improving overall system performance. The method ensures that the key values are correctly ordered and readily accessible, which is particularly useful in applications requiring real-time data processing and sorting.
15. A computer program product to control an electronic computer processor to sort data, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by the electronic computer processor to perform operations comprising: storing, in a memory unit of the computer processor, key values to be sequentially sorted with respect to one another; obtaining, via a processor cache, tree data from the memory unit indicating the key values; generating, via a hardware merge sort accelerator, a master tournament tree based on the key values; generating, via the merge sort accelerator, a master tournament tree based on the key values; and performing, via the merge sort accelerator, a tournament sort that determines a first winning key value based on the master tournament tree and speculates a second winning key value based on the master tournament tree, wherein the speculated second winning key value is a next sequential winning key value of the tournament sort, wherein performing the tournament sort comprises: performing a first tournament to determine a first digit of an overall winning key value; performing a second tournament to determine a second digit of the overall winning key value; determining a first portion of tournament results based on a winning digit of a particular match between a first key value and a second key value different from the first key value; and storing the overall winning key value and the speculated second winning key value in parallel from the merge sort accelerator to the memory unit, wherein the winning digit is determined according to a comparison between a first digit of the first key value and a first digit of the second key value.
This invention relates to a hardware-accelerated sorting system for efficiently sorting key values in a computer processor. The problem addressed is the computational overhead and latency associated with traditional software-based sorting algorithms, particularly for large datasets. The solution involves a specialized hardware merge sort accelerator that leverages a tournament sort mechanism to improve sorting performance. The system stores key values in a memory unit and retrieves them via a processor cache. A hardware merge sort accelerator generates a master tournament tree from these key values. The tournament sort process involves multiple stages, including determining winning key values by comparing digits of the key values in parallel. The system performs a first tournament to determine a digit of the overall winning key value and a second tournament to determine another digit. The winning digit is based on a comparison between corresponding digits of two key values. The system also speculates the next sequential winning key value to enhance efficiency. The winning key value and the speculated next key value are stored in parallel back to the memory unit, reducing latency and improving throughput. This approach minimizes the number of memory accesses and leverages hardware parallelism to accelerate the sorting process.
16. The computer program product of claim 15 , the program instructions further executable by the electronic computer processor to perform operations comprising: representing each key value as a numeral that includes a plurality of digits, wherein performing the tournament sort further comprises: executing a first tournament to determine a first digit of an overall winning key value; and using the master tournament tree to speculate a first digit of the next sequential winning key value in parallel with determining the first digit of the overall winning key value.
This invention relates to optimizing key value sorting in computer systems, particularly for improving the efficiency of tournament sorting algorithms. The problem addressed is the computational overhead in determining the next winning key value during sorting operations, which can slow down data processing in large-scale systems. The invention involves a method for sorting key values by representing each key as a numeral composed of multiple digits. A tournament sorting process is used, where a first tournament is executed to determine the first digit of the overall winning key value. Simultaneously, a master tournament tree is utilized to speculate the first digit of the next sequential winning key value in parallel with determining the current winning key value. This parallel processing reduces latency by predicting the next result while the current one is being finalized, improving sorting performance. The master tournament tree is a hierarchical structure that enables efficient speculation of subsequent key values by leveraging the outcomes of prior tournaments. By predicting the next winning key value in advance, the system minimizes delays associated with sequential processing, enhancing throughput in data-intensive applications. This approach is particularly useful in high-performance computing environments where rapid sorting of large datasets is required.
17. The computer program product of claim 16 , the program instructions further executable by the electronic computer processor to perform operations comprising: updating the memory unit in response to the storing such that the overall winning key value and the speculated second winning key value are automatically stored sequentially with respect to one another.
This invention relates to a computer program product for managing key values in a memory unit, particularly in systems where multiple winning key values need to be tracked and stored efficiently. The problem addressed is the need to automatically and sequentially store key values, such as winning outcomes in a gaming or lottery system, to ensure accurate record-keeping and retrieval. The system includes an electronic computer processor and a memory unit that stores key values, including an overall winning key value and a speculated second winning key value. The program instructions are executable to update the memory unit in response to storing these values, ensuring they are stored sequentially with respect to one another. This sequential storage helps maintain the integrity and order of key values, preventing data corruption or misalignment. The invention may also involve generating a random number, comparing it to a threshold, and determining the overall winning key value based on this comparison. The speculated second winning key value may be derived from a secondary comparison or calculation. The sequential storage mechanism ensures that these values are recorded in a predictable and retrievable manner, which is critical for applications requiring audit trails or historical data analysis. The system may also include additional features, such as generating a random number, comparing it to a threshold, and determining the overall winning key value based on this comparison. The speculated second winning key value may be derived from a secondary comparison or calculation. The sequential storage mechanism ensures that these values are recorded in a predictable and retrievable manner, which is critical for applications requiring audit trails or historical data analysis.
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June 23, 2020
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