Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A system, comprising: a memory circuit including a plurality of banks; a sparse array circuit, including a plurality of entries, wherein a given entry of the plurality of entries corresponds to an address location in the memory circuit, in which a sparse data pattern is stored, wherein the sparse array circuit is configured to: receive first information indicative of a request to perform a read operation, wherein the first information includes a first address; compare the first address to at least one entry of the plurality of entries; and in response to a determination that the first address matches a particular entry of the plurality of entries, generate first and second control signals, wherein the memory circuit is further configured to disable the read operation based upon the first control signal; and a data control circuit configured to transmit the sparse data pattern on a bus coupled to the memory circuit based on the second control signal.
This invention relates to memory systems with sparse data handling capabilities. The problem addressed is the inefficiency in conventional memory systems when accessing sparse data patterns, where most data values are zero or irrelevant, leading to unnecessary read operations and bandwidth waste. The system includes a memory circuit with multiple banks and a sparse array circuit containing entries that correspond to address locations in the memory where sparse data patterns are stored. When a read request is received with a target address, the sparse array circuit compares the address against its entries. If a match is found, the system generates two control signals. The first signal disables the read operation to the memory circuit, preventing unnecessary access. The second signal triggers a data control circuit to transmit the pre-stored sparse data pattern directly onto the bus connected to the memory, bypassing the memory access entirely. This approach reduces power consumption and improves efficiency by avoiding redundant memory reads for known sparse data locations. The system is particularly useful in applications like machine learning, where sparse data is common, to optimize memory bandwidth and energy usage.
2. The system of claim 1 , wherein the sparse array circuit is further configured to: receive second information indicative of a request to perform a write operation, wherein the second information includes a second address and write data; compare the write data to the sparse data pattern; in response to a determination that the write data matches the sparse data pattern: generate a third control signal; and store at least part of the second address in another entry of the plurality of entries; and wherein the memory circuit is further configured to disable the write operation based upon the third control signal.
The system relates to memory management in computing systems, specifically addressing inefficiencies in handling write operations for data that matches a predefined sparse data pattern. The problem being solved is the unnecessary consumption of memory resources and bandwidth when writing data that is already in a sparse state, such as all zeros or another predictable pattern. This is particularly relevant in systems where memory optimization is critical, such as in embedded systems or high-performance computing environments. The system includes a sparse array circuit and a memory circuit. The sparse array circuit is configured to receive a request to perform a write operation, which includes an address and the data to be written. The circuit compares the write data to a predefined sparse data pattern. If the write data matches the pattern, the circuit generates a control signal and stores part of the address in an entry within the circuit. The memory circuit then disables the write operation based on this control signal, preventing the data from being written to memory. This avoids unnecessary write operations, conserving memory bandwidth and power. The sparse array circuit maintains a list of addresses where sparse data has been written, allowing the system to efficiently track and manage sparse data patterns without redundant writes. This mechanism improves overall system performance by reducing memory traffic and energy consumption.
3. The system of claim 2 , wherein to store at least the part of the second address in the another entry of the plurality of entries, the sparse array circuit is further configured to map the second address to a particular region of the memory circuit, and store third information indicative of a mapping the particular region in the another entry.
A system for managing memory addresses in a computing environment involves a sparse array circuit that efficiently maps and stores address information. The system addresses the challenge of handling large address spaces with limited memory resources by using a sparse array structure to store only relevant address mappings, reducing storage overhead. The sparse array circuit maps a second address to a specific region of a memory circuit and stores metadata (third information) in an entry of the sparse array, where the metadata indicates the mapping of that region. This allows the system to quickly access and manage address translations without storing full address mappings for every possible address. The sparse array circuit is configured to handle multiple entries, each storing partial address information and associated metadata, enabling efficient address resolution in systems with sparse or irregular address mappings. The system improves memory efficiency and performance by dynamically mapping addresses to memory regions and storing only necessary mapping information.
4. The system of claim 2 , wherein the sparse array circuit is further configured to: check the write data for possible modification using at least one of a plurality of algorithms; in response to a determination that the write data can be modified, modify the write data using a particular algorithm of the plurality of algorithms to generate modified data; and store third information indicative of the particular algorithm in the another entry; and wherein the memory circuit is further configured to store the modified data.
This invention relates to a data storage system that processes and modifies write data before storage to optimize memory usage. The system addresses the problem of inefficient storage in memory arrays, particularly when handling sparse data or data that can be compressed or encoded. The system includes a sparse array circuit and a memory circuit. The sparse array circuit checks incoming write data for potential modifications using one or more algorithms, such as compression, encoding, or other data transformation techniques. If the data can be modified, the circuit applies a specific algorithm to generate modified data, which is then stored in the memory circuit. The system also stores metadata indicating which algorithm was used for the modification, allowing the original data to be reconstructed later. This approach reduces storage requirements by transforming data into a more compact or efficient form before storage, while ensuring the original data can be accurately retrieved. The system is particularly useful in applications where memory space is limited or where data redundancy needs to be minimized.
5. The system of claim 2 , wherein the write data includes a plurality of data bits, and wherein the sparse array circuit is further configured to: check the plurality of data bits for at least one sequence of repeated data bits; in response to a determination that the plurality of data bits includes a particular sequence of repeated data bits, compress the write data to generate compressed data; and store third information indicative of the particular sequence of repeated data bits in the another entry; and wherein the memory circuit is further configured to store the compressed data.
The invention relates to a data storage system that improves efficiency by compressing write data containing repeated bit sequences. The system includes a memory circuit and a sparse array circuit. The sparse array circuit processes write data, which consists of multiple data bits, to identify sequences of repeated bits. When such a sequence is detected, the system compresses the write data and stores the compressed version in the memory circuit. Additionally, the sparse array circuit stores metadata in another entry, indicating the specific repeated bit sequence used for compression. This approach reduces storage requirements by leveraging redundancy in the data, particularly when the same bit pattern repeats multiple times. The system is designed to handle write operations more efficiently by dynamically compressing data before storage, which is beneficial for applications requiring high-speed data processing and storage optimization. The sparse array circuit's ability to detect and compress repeated bit sequences ensures that storage space is used more effectively, while the metadata stored in another entry allows for accurate reconstruction of the original data when needed. This method is particularly useful in systems where data compression is critical for performance and storage efficiency.
6. The system of claim 1 , further comprising a data capture circuit coupled to the memory circuit, wherein the data capture circuit includes a power gate circuit and a flip-flop circuit, wherein the power gate circuit is configured to selectively couple a power supply node of the flip-flop circuit to a power supply signal using the first control signal.
The system relates to integrated circuit design, specifically addressing power management in digital circuits to reduce energy consumption. The problem being solved is the need for efficient power gating in flip-flop circuits to minimize static power dissipation while maintaining data integrity during power transitions. The system includes a memory circuit and a data capture circuit coupled to the memory circuit. The data capture circuit comprises a power gate circuit and a flip-flop circuit. The power gate circuit is configured to selectively couple the power supply node of the flip-flop circuit to a power supply signal using a first control signal. This allows the flip-flop circuit to be powered on or off dynamically, reducing static power consumption when the circuit is idle. The flip-flop circuit stores and captures data, while the power gate circuit controls the power supply to the flip-flop based on operational requirements, ensuring efficient power management without data loss during transitions. The system optimizes energy efficiency in digital circuits by selectively enabling or disabling power to the flip-flop circuit as needed.
7. A method, comprising: receiving, by a memory, information indicative of a request to perform a read operation, wherein the information includes an address; comparing the address to at least one entry of a plurality of entries included in a sparse array circuit, wherein a given entry of the plurality of entries corresponds to an address location in the memory, in which a sparse data pattern is stored; and in response to determining that the address matches a particular entry of the plurality of entries: disabling the read operation; and transmitting, by a data control circuit, the sparse data pattern on a bus coupled to the memory.
This invention relates to memory systems and addresses the problem of efficiently handling read operations for memory locations storing sparse data patterns, which are data patterns with a high proportion of zeros or repeated values. Traditional read operations for such patterns can be inefficient, consuming unnecessary bandwidth and processing resources. The invention provides a method to optimize these operations by leveraging a sparse array circuit that tracks memory addresses where sparse data patterns are stored. When a read request is received, the address is compared against entries in the sparse array circuit. If a match is found, the read operation is disabled, and the pre-stored sparse data pattern is transmitted directly over the bus, bypassing the memory access. This reduces latency and conserves power by avoiding unnecessary memory reads. The sparse array circuit acts as a lookup table, allowing quick identification of sparse data locations. The data control circuit manages the transmission of the pre-stored pattern, ensuring efficient data retrieval. This approach is particularly useful in systems where sparse data patterns are frequently accessed, such as in certain computational or storage applications.
8. The method of claim 7 , further comprising, in response to determining the address fails to match any entries of the plurality of entries: performing a power up operation on the memory; and performing the read operation.
A method for memory access optimization involves improving the efficiency of read operations in a memory system. The problem addressed is the delay and resource consumption associated with repeated read attempts when an address does not initially match any entries in a lookup table or cache. The method includes a pre-read check to determine if the target address exists in a stored list of entries. If the address is found, the read operation proceeds directly. If the address is not found, the method triggers a power-up operation on the memory module before retrying the read operation. This ensures that the memory is in an optimal state for data retrieval, reducing the likelihood of failed reads and improving overall system performance. The power-up operation may involve initializing or refreshing the memory to ensure data integrity and accessibility. This approach minimizes unnecessary read attempts and conserves power by avoiding redundant operations when the memory is already active. The method is particularly useful in systems where memory access speed and efficiency are critical, such as in embedded systems, high-performance computing, or real-time applications.
9. The method of claim 7 , further comprising: receiving, by the memory, second information indicative of a request to perform a write operation, wherein the information includes storage data and a second address; comparing the storage data to the sparse data pattern; and in response to determining the storage data matches the sparse data pattern: disabling the write operation; and updating another entry of the plurality of entries using the second address.
This invention relates to memory systems, specifically optimizing write operations in storage devices by detecting and handling sparse data patterns. The problem addressed is inefficient storage and unnecessary write operations when data contains repetitive or predictable patterns, such as zeros or other sparse values, which waste storage space and processing resources. The method involves a memory system that stores a sparse data pattern, which represents a predefined sequence of values (e.g., all zeros). When a write operation is requested, the system receives storage data and an address. The storage data is compared to the sparse data pattern. If the storage data matches the pattern, the write operation is disabled to avoid storing redundant data. Instead, the system updates an entry in a lookup table or metadata structure using the address, indicating that the storage location contains the sparse pattern. This reduces storage overhead and improves efficiency by avoiding unnecessary writes. The system may also include a mechanism to track addresses where sparse data is stored, allowing the memory to quickly identify and manage these locations. This approach is particularly useful in systems where large datasets contain significant amounts of sparse or repetitive data, such as in databases, file systems, or caching mechanisms. By dynamically detecting and handling sparse patterns, the method enhances storage efficiency and performance.
10. The method of claim 9 , further comprising, in response to determining the storage data fails to match the sparse data pattern: performing a power up operation on the memory; writing the storage data to the memory using the address; and in response to completing writing the storage data to the memory, performing a power down operation on the memory.
This invention relates to memory management in computing systems, specifically addressing the challenge of efficiently handling storage data that does not conform to expected sparse data patterns. In systems where memory is powered down to conserve energy, data must be written to memory when it deviates from a predefined sparse pattern. The method involves monitoring storage data to determine if it matches a sparse data pattern. If the data does not match, the system performs a power-up operation on the memory, writes the storage data to the memory at a specified address, and then performs a power-down operation once the write operation is complete. This ensures that non-sparse data is properly stored while minimizing unnecessary power consumption. The method is particularly useful in low-power or energy-efficient computing environments where memory access must be optimized to balance performance and power usage. The approach helps maintain data integrity while reducing the frequency of power cycles, thereby extending the lifespan of memory components and improving overall system efficiency.
11. The method of claim 9 , wherein updating the another entry of the plurality of entries includes mapping the second address to a particular collection region of one or more collection regions included in the memory.
This invention relates to memory management systems, specifically addressing the challenge of efficiently organizing and accessing data in memory to improve performance and reduce fragmentation. The method involves managing memory by updating entries in a data structure that tracks memory allocations. When a new memory allocation request is received, the system determines a second address for the allocation and updates an entry in the data structure to reflect this allocation. The updated entry is then mapped to a specific collection region within the memory. Collection regions are designated areas of memory used to group related allocations, improving memory locality and reducing fragmentation. The method ensures that memory allocations are efficiently tracked and organized, enhancing system performance by optimizing memory access patterns and minimizing wasted space. This approach is particularly useful in systems where memory management overhead must be minimized, such as in real-time or embedded systems. The invention provides a structured way to manage memory by dynamically associating allocations with collection regions, allowing for better memory utilization and faster access times.
12. The method of claim 9 , further comprising: checking the storage data for one or more sequences of repeated bits, a given sequence of the one or more sequences of repeated bits includes a plurality of bits of a same logic value; in response to detecting at least one sequence of repeated bits: compressing the storage data to generate compressed data; storing the compressed data in a particular region of a plurality of regions included in the memory; and updating status associated with the compressed data.
This invention relates to data compression in memory systems, specifically for optimizing storage efficiency by detecting and compressing sequences of repeated bits in stored data. The method involves analyzing storage data to identify sequences where multiple consecutive bits share the same logic value (e.g., all 0s or all 1s). Upon detecting such sequences, the data is compressed to reduce storage footprint. The compressed data is then stored in a designated region of memory, and metadata or status information associated with the compressed data is updated to reflect the compression. This approach improves storage utilization by reducing redundancy, particularly in scenarios where data contains long sequences of identical bits, such as in certain types of encoded or structured data. The method may be applied to various memory types, including but not limited to flash memory, DRAM, or other non-volatile storage media. The compression process may involve encoding the repeated bits in a compact form, such as using run-length encoding or similar techniques, while the status update ensures that the system can accurately track and retrieve the compressed data when needed. This technique is particularly useful in systems where storage space is limited or where power efficiency is critical, as compressed data requires less energy to store and retrieve.
13. The method of claim 7 , further comprising: decoding a portion of the address to generated a partially-decoded address; in response to determining that the partially-decoded address corresponds to a particular region of a plurality of regions included in the memory: disabling further decoding of the address; and transmitting, by the data control circuit, the sparse data pattern on the bus coupled to the memory.
This invention relates to memory access optimization in computing systems, specifically addressing inefficiencies in address decoding for memory regions storing sparse data patterns. The problem occurs when memory controllers must fully decode addresses for regions containing repetitive or predictable data, wasting processing cycles and bandwidth. The solution involves a method to optimize address decoding by partially decoding an address to identify if it corresponds to a predefined memory region storing sparse data. If the partially-decoded address matches a region, further decoding is skipped, and the sparse data pattern is directly transmitted to the memory bus. This reduces unnecessary decoding steps, improving system performance and efficiency. The method is implemented within a data control circuit that manages memory access operations. The invention also includes determining the sparse data pattern based on predefined criteria, such as repetitive values or predictable sequences, and storing this pattern in a lookup table or similar structure for quick retrieval. The approach is particularly useful in systems where certain memory regions frequently store predictable data, such as zero-filled blocks or repeated values, allowing faster access and reduced power consumption.
14. A non-transitory computer-readable storage medium having design information stored thereon, wherein the design information specifies a design of at least a portion of a hardware integrated circuit in a format recognized by a semiconductor fabrication system that is configured to use the design information to produce the hardware integrated circuit according to the design information, wherein the design information specifies that the hardware integrated circuit comprises: a memory circuit including a plurality of banks; a sparse array circuit, including a plurality of entries, wherein a given entry of the plurality of entries corresponds to an address location in the memory circuit, in which a sparse data pattern is stored, wherein the sparse array circuit is configured to: receive first information indicative of a request to perform a read operation, wherein the first information includes a first address; compare the first address to at least one entry of the plurality of entries; and in response to a determination that the first address matches a particular entry of the plurality of entries, generate first and second control signals; and wherein the memory circuit is further configured to disable the read operation based upon the first control signal; and a data control circuit configured to transmit the sparse data pattern on a bus coupled to the memory circuit based on the second control signal.
This invention relates to hardware integrated circuits designed to efficiently handle sparse data patterns in memory systems. The problem addressed is the inefficiency of conventional memory access operations when dealing with sparse data, where most data values are zero or irrelevant, leading to unnecessary read operations and bandwidth waste. The integrated circuit includes a memory circuit with multiple banks, a sparse array circuit, and a data control circuit. The sparse array circuit contains entries that correspond to specific address locations in the memory circuit where sparse data patterns are stored. When a read request is received with a target address, the sparse array circuit compares this address against its entries. If a match is found, the circuit generates two control signals. The first control signal disables the read operation to the memory circuit, preventing unnecessary access. The second control signal triggers the data control circuit to transmit the pre-stored sparse data pattern directly onto the bus connected to the memory circuit, bypassing the memory access entirely. This approach reduces power consumption and improves performance by avoiding redundant memory operations for sparse data. The design information for this circuit is stored in a format compatible with semiconductor fabrication systems, enabling direct production of the hardware.
15. The non-transitory computer-readable storage medium of claim 14 , wherein the sparse array circuit is further configured to: receive second information indicative of a request to perform a write operation, wherein the second information includes a second address and write data; compare the write data to the sparse data pattern; in response to a determination that the write data matches the sparse data pattern: generate a second control signal to halt the write operation; and store at least part of the second address in another entry of the plurality of entries.
This invention relates to memory systems, specifically optimizing write operations in sparse data storage. The problem addressed is inefficient storage and unnecessary write operations when data matches a predefined sparse pattern, such as zero-filled or repeated values. The solution involves a sparse array circuit that detects such patterns and avoids redundant writes, improving storage efficiency and performance. The system includes a memory controller and a sparse array circuit. The circuit stores a sparse data pattern, such as a sequence of zeros or a repeating value, and compares incoming write data against this pattern. If the write data matches the pattern, the circuit halts the write operation and records the address where the write would have occurred. This prevents unnecessary writes, reducing wear on storage media and conserving energy. The circuit maintains a list of addresses where sparse data is stored, allowing efficient retrieval without full writes. The invention also handles dynamic updates. When a new write request is received, the system checks if the data matches the sparse pattern. If it does, the write is skipped, and the address is logged. If not, the data is written normally. This adaptive approach ensures that only meaningful data consumes storage resources, optimizing both capacity and performance in systems handling large datasets with repetitive or zero-filled content.
16. The non-transitory computer-readable storage medium of claim 15 , wherein to store at least the part of the second address in the another entry of the plurality of entries, the sparse array circuit is further configured to: map the second address to a particular region of the memory circuit; and store third information indicative of a mapping the particular region in the another entry.
This invention relates to memory management in computer systems, specifically addressing the challenge of efficiently storing and retrieving address mappings in sparse memory arrays. The system includes a sparse array circuit configured to manage memory access by storing address mappings in a plurality of entries. When storing at least part of a second address in another entry of the plurality of entries, the circuit maps the second address to a particular region of the memory circuit and stores third information indicative of this mapping in the entry. This allows for efficient address translation and memory access in systems where memory is not densely populated or where address mappings are sparse. The circuit may also handle address collisions by remapping conflicting addresses to different regions, ensuring reliable memory operations. The system optimizes memory usage and access speed by dynamically adjusting address mappings based on memory availability and access patterns. This approach is particularly useful in large-scale memory systems, virtual memory environments, or distributed storage systems where efficient address management is critical. The invention improves upon traditional memory management techniques by reducing overhead and enhancing performance in sparse memory configurations.
17. The non-transitory computer-readable storage medium of claim 15 , wherein the sparse array circuit is further configured to: check the write data for possible modification using at least one of a plurality of algorithms; in response to a determination that the write data can be modified, modify the write data using a particular algorithm of the plurality of algorithms to generate modified data; and store third information indicative of the particular algorithm in the another entry.
This invention relates to data storage systems, specifically methods for efficiently handling write operations in sparse arrays. The problem addressed is the need to optimize storage space and processing efficiency when writing data to a sparse array, where many entries may be empty or contain redundant information. The system includes a sparse array circuit that processes write data before storage. The circuit checks the write data for potential modifications using multiple algorithms, such as compression, encryption, or deduplication. If the data can be modified, the circuit applies a selected algorithm to generate modified data, which is then stored in the array. The system also stores metadata indicating which algorithm was used, allowing for accurate reconstruction of the original data during retrieval. The sparse array circuit dynamically selects the most efficient algorithm for each write operation, reducing storage requirements and improving performance. This approach ensures that data is stored in the most compact or secure form possible while maintaining the ability to revert to the original data when needed. The metadata stored with each entry ensures that the correct algorithm is applied during read operations, preserving data integrity. This method is particularly useful in systems where storage space is limited or where data security is a priority.
18. The non-transitory computer-readable storage medium of claim 15 , wherein the write data includes a plurality of data bits, and wherein the sparse array circuit is further configured to: check the plurality of data bits for at least one sequence of repeated data bits; in response to a determination that the plurality of data bits includes a particular sequence of repeated data bits, compress the write data to generate compressed data; and store third information indicative of the particular sequence of repeated data bits in the another entry.
This invention relates to data storage systems, specifically optimizing storage efficiency by compressing repeated data sequences. The problem addressed is the inefficient use of storage space when storing repetitive data patterns, which can lead to wasted capacity and reduced performance. The system includes a sparse array circuit that processes write data before storage. The write data consists of multiple data bits, and the circuit checks for sequences of repeated bits. If such a sequence is detected, the data is compressed to generate compressed data. The system then stores metadata indicating the detected repeated sequence in a separate entry. This metadata allows the system to reconstruct the original data when needed, while reducing the storage footprint of repetitive patterns. The sparse array circuit is part of a larger storage system that uses a sparse array structure to manage data storage. This structure includes multiple entries, each storing different types of information, such as data, metadata, or pointers. The compression process is applied dynamically during write operations, ensuring that repetitive data is stored in a more compact form without requiring manual intervention. By compressing repeated data sequences and storing metadata about these sequences, the system improves storage efficiency, reduces the amount of physical storage required, and enhances overall system performance. This approach is particularly useful in environments where repetitive data patterns are common, such as in databases, log files, or backup systems.
19. The non-transitory computer-readable storage medium of claim 14 , wherein the hardware integrated circuit further comprises a data capture circuit coupled to the memory circuit, wherein the data capture circuit includes a power gate circuit and a flip-flop circuit, wherein the power gate circuit is configured to selectively couple a power supply node of the flip-flop circuit to a power supply signal using the first control signal.
This invention relates to integrated circuit design, specifically addressing power management in hardware circuits to reduce energy consumption. The technology focuses on a non-transitory computer-readable storage medium containing instructions for implementing a hardware integrated circuit with enhanced power control features. The circuit includes a memory circuit and a data capture circuit connected to it. The data capture circuit comprises a power gate circuit and a flip-flop circuit. The power gate circuit is designed to selectively connect or disconnect the flip-flop circuit's power supply node from the power supply signal based on a first control signal. This selective coupling allows the flip-flop circuit to be powered on or off dynamically, reducing unnecessary power consumption when the circuit is idle. The flip-flop circuit stores data, and the power gate circuit ensures efficient power management by controlling the supply voltage to the flip-flop based on operational needs. This design helps minimize energy waste in integrated circuits, particularly in applications requiring low-power operation, such as mobile devices or embedded systems. The invention improves upon existing power management techniques by integrating a dedicated power gate circuit within the data capture circuit, enabling finer control over power distribution to individual components.
20. The non-transitory computer-readable storage medium of claim 14 , wherein the hardware integrated circuit further comprises a data capture circuit coupled to the memory circuit, wherein the data capture circuit includes a flip-flop circuit and a clock gating circuit configured to selectively couple a local clock signal coupled to the flip-flop circuit to a clock signal using the first control signal.
The invention relates to integrated circuit design, specifically addressing challenges in data capture and clock management within hardware circuits. The technology focuses on improving data capture efficiency and reducing power consumption in digital circuits by selectively controlling clock signals. A hardware integrated circuit includes a memory circuit and a data capture circuit. The data capture circuit comprises a flip-flop circuit and a clock gating circuit. The clock gating circuit is configured to selectively couple a local clock signal to the flip-flop circuit based on a first control signal. This selective coupling allows the flip-flop circuit to capture data only when necessary, reducing unnecessary clock toggling and conserving power. The flip-flop circuit stores data from the memory circuit, while the clock gating circuit dynamically manages the clock signal to optimize performance and energy efficiency. This approach is particularly useful in high-performance computing and low-power applications where precise control over clock signals is critical for maintaining system efficiency. The invention enhances data capture reliability and minimizes power dissipation by ensuring that the clock signal is only active when data needs to be captured, thereby improving overall circuit efficiency.
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June 23, 2020
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