Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A clock generation system having a time and frequency division activation mechanism comprising: a clock source processing circuit configured to generate a primary clock signal; and a plurality of clock-branching circuits that perform a clock-branching generation procedure respectively in an order each comprising: a frequency division unit, during the clock-branching generation procedure, configured to receive the primary clock signal to divide a frequency of the primary clock signal according to a divisor number and output a branch clock signal; and a processing unit configured to control the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over the time period from an initial divisor number larger than one to a final divisor number after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.
A clock generation system is designed to control the activation of clock signals in a time and frequency division manner. The system includes a clock source processing circuit that generates a primary clock signal. Multiple clock-branching circuits are connected to this primary signal, each performing a clock-branching generation procedure. Each clock-branching circuit contains a frequency division unit that receives the primary clock signal and divides its frequency according to a specified divisor number, producing a branch clock signal. A processing unit within each circuit controls the frequency division unit to initially suppress the output of the branch clock signal. Once the clock-branching generation procedure begins, the processing unit gradually decreases the divisor number from an initial value (greater than one) to a final value over a defined time period. This adjustment causes the branch clock signal's frequency to increase from an initial frequency to a final frequency, completing the procedure. The system ensures controlled activation of clock signals with adjustable frequency division, allowing precise timing and synchronization in electronic circuits.
2. The clock generation system of claim 1 , wherein each of the clock-branching circuits corresponds to a circuit block such that the frequency division unit outputs the branch clock signal to the circuit block.
A clock generation system is designed to distribute clock signals efficiently in integrated circuits, addressing the challenge of power consumption and synchronization in complex digital systems. The system includes multiple clock-branching circuits, each assigned to a specific circuit block within the integrated circuit. Each clock-branching circuit receives a branch clock signal from a frequency division unit, which adjusts the clock frequency to meet the requirements of the corresponding circuit block. This ensures that each block operates at an optimal frequency, reducing unnecessary power consumption and improving overall system efficiency. The frequency division unit dynamically controls the clock signals, allowing for flexible and adaptive clock distribution across different circuit blocks. This approach minimizes power dissipation by avoiding overclocking or underclocking of individual blocks, while maintaining precise synchronization across the entire system. The system is particularly useful in applications requiring low-power operation and high-performance computing, such as mobile devices, embedded systems, and high-speed processors. By tailoring clock frequencies to specific circuit blocks, the system enhances energy efficiency without compromising performance.
3. The clock generation system of claim 1 , wherein after generating the primary clock signal, the clock source processing circuit transmits an initializing signal to trigger a first one of the clock-branching circuits to perform the clock-branching generation procedure, each of the clock-branching circuits generates a triggering signal after the respective clock-branching generation procedure is finished to trigger the next one of the clock-branching circuits to perform the clock-branching generation procedure and the last one of the clock-branching circuits generates the triggering signal to the clock source processing circuit after the clock-branching generation procedure is finished.
This invention relates to a clock generation system designed to improve synchronization and efficiency in digital circuits. The system addresses the challenge of distributing clock signals across multiple branches while minimizing skew and ensuring precise timing. The system includes a clock source processing circuit that generates a primary clock signal. After generating this primary signal, the clock source processing circuit sends an initializing signal to trigger the first of several clock-branching circuits. Each clock-branching circuit performs a clock-branching generation procedure, which involves dividing or modifying the primary clock signal to produce a derived clock signal for a specific branch. Once a clock-branching circuit completes its procedure, it generates a triggering signal to activate the next clock-branching circuit in sequence. This cascading process continues until the last clock-branching circuit finishes its procedure and sends a final triggering signal back to the clock source processing circuit. This sequential activation ensures that each branch receives its clock signal in a controlled and synchronized manner, reducing timing errors and improving overall system performance. The system is particularly useful in high-speed digital circuits where precise timing is critical.
4. The clock generation system of claim 1 , wherein the clock source processing circuit controls the clock-branching circuits to stop outputting the branch clock signal in the order according to a frequency-adjusting command and the clock source processing circuit further stops to output the primary clock signal such that the clock source processing circuit restarts to generate the primary clock signal.
A clock generation system is designed to manage and distribute clock signals in electronic circuits, particularly in systems requiring precise timing control. The system addresses the challenge of dynamically adjusting clock frequencies while minimizing disruptions to dependent circuits. The system includes a clock source processing circuit that generates a primary clock signal and multiple clock-branching circuits that distribute branch clock signals derived from the primary clock signal. To adjust the frequency of the primary clock signal, the clock source processing circuit issues a frequency-adjusting command. In response, the clock-branching circuits sequentially stop outputting their respective branch clock signals in a controlled order, ensuring that dependent circuits are not abruptly affected. After all branch clock signals are halted, the clock source processing circuit stops outputting the primary clock signal entirely. The system then restarts the generation of the primary clock signal at the new desired frequency, allowing the clock-branching circuits to resume outputting their branch clock signals. This method ensures smooth frequency adjustments without causing timing errors in the system. The system is particularly useful in applications where precise timing synchronization is critical, such as in digital signal processing, communication systems, and microprocessors.
5. The clock generation system of claim 1 , wherein the clock source processing circuit comprises: a phase-locked loop circuit configured to generate a clock signal; and a clock signal output circuit configured to perform a primary clock signal generation procedure and comprises: a clock signal output frequency division unit, during the primary clock signal generation procedure, configured to receive the clock signal to divide a frequency of the clock signal according to an output divisor number and output the primary clock signal; and a clock signal output processing unit configured to control the clock signal output frequency division unit to not output the primary clock signal before the primary clock signal generation procedure and to decrease the output divisor number gradually over the time period from an initial output divisor number larger than one to a final output divisor number after the primary clock signal generation procedure begins such that a primary frequency of the primary clock signal generated by the clock signal output frequency division unit increases from an initial output frequency to a final output frequency to finish the primary clock signal generation procedure.
This invention relates to a clock generation system designed to control the frequency of a clock signal during startup. The system addresses the problem of abrupt frequency changes in clock signals, which can cause instability in electronic circuits. The clock generation system includes a phase-locked loop (PLL) circuit that generates a base clock signal. A clock signal output circuit processes this signal to produce a primary clock signal with controlled frequency transitions. The clock signal output circuit includes a frequency division unit that divides the base clock signal according to a configurable divisor. Before the primary clock signal generation procedure begins, the frequency division unit is disabled, preventing any output. Once the procedure starts, the divisor is gradually decreased over time, beginning from an initial value greater than one and reducing to a final value. This gradual reduction increases the primary clock signal's frequency from an initial low value to a final higher value, ensuring a smooth transition. The controlled ramp-up of the clock frequency prevents sudden changes that could disrupt circuit operations. This approach is particularly useful in systems requiring stable clock signal initialization, such as digital processors or communication devices.
6. The clock generation system of claim 1 , wherein the clock-branching circuits are connected in the form of a daisy chain.
A clock generation system includes multiple clock-branching circuits arranged in a daisy chain configuration to distribute clock signals efficiently. The system generates a primary clock signal and uses the daisy chain to propagate this signal through interconnected branching circuits, ensuring synchronized distribution to multiple components. Each branching circuit receives an input clock signal, divides or multiplies the frequency as needed, and outputs one or more derived clock signals to downstream circuits. The daisy chain structure minimizes signal skew by reducing the number of parallel connections and simplifies routing in integrated circuits. This design is particularly useful in high-speed digital systems where precise timing and low latency are critical, such as microprocessors, FPGAs, and communication devices. The daisy chain arrangement also enhances scalability, allowing additional branching circuits to be added without significant redesign. The system may include phase-locked loops (PLLs) or delay-locked loops (DLLs) to stabilize the clock signals and compensate for variations in propagation delay. By chaining the circuits, the system ensures consistent clock distribution while maintaining low power consumption and reducing electromagnetic interference.
7. A clock generation method having a time and frequency division activation mechanism comprising: generating a primary clock signal by a clock source processing circuit; controlling a frequency division unit comprised in each of a plurality of clock-branching circuits to not output a branch clock signal before a clock-branching generation procedure by a processing unit comprised in each of the clock-branching circuits; and performing the clock-branching generation procedure respectively in an order by the clock-branching circuits, wherein the clock-branching generation procedure comprises: receiving the primary clock signal to divide a frequency of the primary clock signal according to a divisor number and output a branch clock signal by the frequency division unit; and decreasing the divisor number gradually over the time period from an initial divisor number larger than one to a final divisor number such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure by the processing unit.
This invention relates to clock signal generation systems, specifically addressing the challenge of efficiently activating multiple clock branches with controlled frequency transitions. The method involves a primary clock source generating a base clock signal, which is then distributed to multiple clock-branching circuits. Each branching circuit includes a frequency division unit and a processing unit. Initially, the frequency division units are disabled, preventing any branch clock signals from being output. The processing units then sequentially activate the frequency division units in a time and frequency division activation mechanism. During activation, each frequency division unit receives the primary clock signal and divides its frequency according to a dynamically adjusted divisor number. The divisor number starts at an initial value greater than one and gradually decreases over time, causing the output branch clock frequency to increase from an initial frequency to a final frequency. This controlled ramp-up ensures smooth and synchronized activation of all clock branches, preventing abrupt frequency changes that could disrupt system operations. The method is particularly useful in systems requiring precise timing control across multiple clock domains.
8. The clock generation method of claim 7 , further comprising: outputting the branch clock signal to a circuit block that one of the clock-branching circuits corresponds by the frequency division unit.
A clock generation method addresses the need for efficient clock signal distribution in integrated circuits, particularly in systems requiring multiple clock domains with different frequencies. The method involves generating a master clock signal and distributing it to multiple clock-branching circuits, each configured to produce a branch clock signal with a specific frequency. These branch clock signals are then routed to corresponding circuit blocks within the system. The method further includes a frequency division unit that ensures the branch clock signals are output to the appropriate circuit blocks, allowing precise control over clock distribution. This approach optimizes power efficiency and performance by dynamically adjusting clock frequencies based on operational requirements, reducing unnecessary power consumption in inactive or low-activity circuit blocks. The method is particularly useful in complex systems such as microprocessors, digital signal processors, and other integrated circuits where multiple clock domains must be managed efficiently. By integrating frequency division and selective clock distribution, the method enhances overall system performance while minimizing energy waste.
9. The clock generation method of claim 7 , further comprising: transmitting an initializing signal to trigger a first one of the clock-branching circuits to perform the clock-branching generation procedure by the clock source processing circuit after the primary clock signal is generated; generating a triggering signal by each of the clock-branching circuits after the respective clock-branching generation procedure is finished to trigger the next one of the clock-branching circuits to perform the clock-branching generation procedure; and generating the triggering signal to the clock source processing circuit by the last one of the clock-branching circuits after the clock-branching generation procedure is finished.
This invention relates to clock generation systems, specifically methods for managing clock-branching circuits in a hierarchical clock distribution network. The problem addressed is the need for efficient and synchronized activation of multiple clock-branching circuits to generate secondary clock signals from a primary clock source. The system includes a clock source processing circuit that generates a primary clock signal and multiple clock-branching circuits connected in sequence. Each clock-branching circuit performs a clock-branching generation procedure to produce a secondary clock signal. The method involves transmitting an initializing signal to the first clock-branching circuit to begin its procedure after the primary clock signal is generated. Once a clock-branching circuit completes its procedure, it generates a triggering signal to activate the next clock-branching circuit in the sequence. After the last clock-branching circuit finishes its procedure, it sends a triggering signal back to the clock source processing circuit, completing the cascaded activation process. This ensures synchronized and sequential activation of all clock-branching circuits, improving clock signal distribution efficiency in integrated circuits or other systems requiring precise timing control.
10. The clock generation method of claim 7 , further comprising: controlling the clock-branching circuits to stop outputting the branch clock signal in the order according to a frequency-adjusting command by the clock source processing circuit and further stopping to output the primary clock signal by the clock source processing circuit such that the clock source processing circuit restarts to generate the primary clock signal.
This invention relates to clock generation systems, specifically methods for dynamically adjusting clock frequencies in digital circuits. The problem addressed is the need for efficient and flexible clock frequency control in systems where multiple clock branches are used, ensuring stable operation while minimizing power consumption and maintaining synchronization. The method involves a clock source processing circuit that generates a primary clock signal, which is then distributed to multiple clock-branching circuits. Each branching circuit outputs a branch clock signal derived from the primary clock signal. To adjust the clock frequency, the clock source processing circuit issues a frequency-adjusting command. In response, the clock-branching circuits stop outputting their branch clock signals in a controlled order, ensuring no abrupt disruptions. After all branch clock signals are halted, the clock source processing circuit stops the primary clock signal entirely. The system then restarts the primary clock signal generation, allowing the branching circuits to resume operation with the new frequency settings. This approach ensures smooth frequency transitions, reduces power consumption during idle states, and maintains system stability. The method is particularly useful in applications requiring dynamic clock scaling, such as power management in processors or communication systems.
11. The clock generation method of claim 7 , wherein the clock source processing circuit comprises: generating a clock signal by a phase-locked loop circuit comprised in the clock source processing circuit; controlling a clock signal output frequency division unit comprised in a clock signal output circuit of the clock source processing circuit to not output the primary clock signal before the primary clock signal generation procedure by a clock signal output processing unit comprised in the clock signal output circuit; and performing the primary clock signal generation procedure by the clock signal output circuit, wherein the primary clock signal generation procedure comprises: receiving the clock signal to divide a frequency of the clock signal according to an output divisor number and output the primary clock signal by the clock signal output frequency division unit; and decreasing the output divisor number gradually over the time period from an initial output divisor number larger than one to a final output divisor number after the primary clock signal generation procedure begins by the clock signal output processing unit such that a primary frequency of the primary clock signal generated by the clock signal output frequency division unit increases from an initial output frequency to a final output frequency to finish the primary clock signal generation procedure.
This invention relates to clock signal generation, specifically a method for controlling the output of a primary clock signal in a phase-locked loop (PLL) system. The problem addressed is the need to gradually increase the frequency of a primary clock signal from an initial low frequency to a final operating frequency, ensuring stable and controlled signal generation. The method involves a clock source processing circuit that includes a PLL circuit to generate a base clock signal. A clock signal output circuit within the processing circuit controls the output of the primary clock signal. Before the primary clock signal generation procedure begins, the output circuit prevents the primary clock signal from being output. Once the generation procedure starts, the clock signal output frequency division unit receives the base clock signal and divides its frequency according to an output divisor number, producing the primary clock signal. The output divisor number is initially set to a value greater than one, resulting in a lower initial output frequency. Over time, the clock signal output processing unit gradually decreases the output divisor number, causing the primary clock signal's frequency to increase from an initial frequency to a final frequency. This controlled frequency ramp-up ensures smooth and stable clock signal generation. The procedure concludes once the final output frequency is reached.
12. The clock generation method of claim 7 , wherein the clock-branching circuits are connected in the form of a daisy chain.
A clock generation method involves distributing clock signals in a daisy chain configuration to reduce skew and improve synchronization in integrated circuits. The method addresses the challenge of maintaining precise timing across multiple clock domains, which is critical for high-performance systems. The daisy chain arrangement ensures that each clock-branching circuit receives a clock signal from the preceding circuit, minimizing propagation delays and phase mismatches. Each branching circuit further distributes the clock signal to downstream components, maintaining consistent timing across the system. The method is particularly useful in large-scale integrated circuits where traditional clock distribution networks may introduce significant skew. By cascading the branching circuits, the system achieves uniform clock distribution with reduced latency and improved reliability. This approach is applicable in digital signal processing, microprocessors, and other high-speed electronic systems where precise timing is essential. The daisy chain configuration simplifies the design while enhancing performance, making it a practical solution for modern clock distribution challenges.
Unknown
June 23, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.