Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A method for buffering data from non-volatile memory into volatile memory, the method comprises: identifying, by a processing entity of a computing device, a plurality of data units to read from non-volatile memory and to write into ordered buffers of volatile memory, wherein data units of the plurality of data units have a variety of data sizes, wherein the plurality of data units is stored in “n” number of logical data blocks of the non-volatile memory, wherein a data unit of the plurality of data units is at least partially stored in two or more logical data blocks of the “n” number of logical data blocks of the non-volatile memory, and wherein “n” is an integer greater than or equal to two; generating, by the processing entity, read operations regarding the plurality of data units, wherein the number of read operations equals “n”; tagging, by the processing entity, each read operation of the read operations with a unique ordered tag value, wherein a first read operation of the read operations is regarding a first logical data block of the “n” number of logical data blocks of the non-volatile memory and is tagged with a first ordered tag value; receiving, by the processing entity, read responses to the read operations from the non-volatile memory, wherein a first read response of the read responses is in response to the first read operation and includes the first ordered tag value; writing, by the processing entity, data units contained in the read responses into the ordered buffers in accordance with the ordered tag values; and tracking, by the processing entity, consumption of the plurality of data units from the ordered buffers.
This invention relates to data management in computing devices, specifically addressing the challenge of efficiently buffering data from non-volatile memory (like SSDs or hard drives) into volatile memory (RAM). The problem is that data units, which can vary in size, may be fragmented across multiple logical data blocks within the non-volatile memory. The method involves a processing entity identifying multiple data units to be read from non-volatile memory and written into ordered buffers in volatile memory. These data units can span across two or more logical data blocks. To manage this fragmentation, the processing entity generates a number of read operations equal to the number of logical data blocks involved. Each read operation is assigned a unique, ordered tag value. When read responses are received from the non-volatile memory, they are associated with their corresponding tag values. The data units within these responses are then written into the ordered buffers in volatile memory, strictly following the sequence indicated by the ordered tag values. Finally, the system tracks how these buffered data units are consumed from the volatile memory. This ensures that fragmented data is correctly reassembled and processed in the intended order, even when originating from multiple non-volatile memory blocks.
2. The method of claim 1 , wherein the identifying the plurality of data units comprises: receiving, by the processing entity, an operation that includes reading the plurality of data units from the disk memory and writing the plurality of data units into the ordered buffer.
This invention relates to data processing systems, specifically methods for managing data units in memory. The problem addressed is the inefficient handling of data units during read and write operations between disk memory and an ordered buffer, which can lead to performance bottlenecks and increased latency. The method involves a processing entity that identifies a plurality of data units by performing a read operation from disk memory and a write operation into an ordered buffer. The ordered buffer is structured to maintain data units in a specific sequence, ensuring proper alignment and organization for subsequent processing. The processing entity executes these operations to transfer data units from disk memory to the ordered buffer, where they are stored in a predefined order. This ensures that the data units are accessible in the correct sequence for further operations, such as data analysis, retrieval, or transmission. The method optimizes data transfer by coordinating the read and write operations, reducing the time and computational overhead associated with moving data between storage and memory. By maintaining the ordered buffer in a structured manner, the system ensures data integrity and minimizes errors during subsequent processing steps. This approach is particularly useful in applications requiring high-speed data access and efficient memory management, such as database systems, file storage solutions, and real-time data processing environments.
3. The method of claim 1 further comprises: accessing, by the processing entity, metadata regarding the plurality of data units to read; determining, by the processing entity, a specific number “n” of the “n” number of logical data blocks of the non-volatile memory based on the metadata; and allocating, by the processing entity, the specific number of logical data blocks of the volatile memory for the ordered buffers.
This invention relates to data processing systems that manage data transfers between volatile and non-volatile memory, particularly optimizing buffer allocation for efficient data handling. The problem addressed is the inefficient use of volatile memory resources during data transfer operations, which can lead to performance bottlenecks and wasted storage capacity. The method involves a processing entity that reads a plurality of data units from non-volatile memory and writes them to volatile memory using ordered buffers. The processing entity accesses metadata associated with the data units to determine a specific number "n" of logical data blocks in the non-volatile memory that will be read. Based on this metadata, the processing entity allocates exactly "n" logical data blocks in the volatile memory for the ordered buffers. This ensures that the volatile memory allocation precisely matches the data being transferred, preventing over-allocation or under-allocation of buffer space. The method also includes reading the data units from the non-volatile memory into the allocated buffers in the volatile memory, maintaining the order of the data units as specified by the metadata. This approach optimizes memory usage and improves data transfer efficiency by dynamically adjusting buffer allocation based on the actual data requirements.
4. The method of claim 3 further comprises: executing, by the processing entity, an ordered buffer function of a process specific operating system of the computing device, wherein the process specific operating system overrides, with respect to the volatile memory, a general operating system of the computing device.
This invention relates to computing systems where a process-specific operating system (OS) overrides a general OS to manage volatile memory. The problem addressed is ensuring efficient and secure memory management for specialized processes, particularly when the general OS may not provide sufficient control or isolation. The solution involves a computing device with a processing entity that executes a process-specific OS, which takes precedence over the general OS in managing volatile memory. This allows the process-specific OS to enforce custom memory policies, access controls, or performance optimizations tailored to the process, while the general OS continues to manage other system functions. The process-specific OS may include an ordered buffer function to manage memory operations, ensuring data is processed in a specific sequence, which is critical for applications requiring deterministic behavior, such as real-time systems or security-sensitive tasks. By overriding the general OS's memory management for the volatile memory, the process-specific OS can prevent interference from other processes, improving reliability and security. This approach is useful in environments where strict memory isolation or specialized memory handling is required, such as in embedded systems, virtualized environments, or high-assurance computing.
5. The method of claim 1 , wherein the writing comprises: comparing an order tag value of a current received read response of the read responses with a next expected tag value; when the order tag value of the current received read response compares unfavorably with the next expected tag value: queuing the tag of the current received read response; writing one or more partial data units contained in the current received read response to one of the ordered buffers based on the ordered data tag; and indicating that the one or more partial data units are not available for consumption; when the order tag value of the current received read response compares favorably with the next expected tag value: writing the one or more partial data units contained in the current received read response to one of the ordered buffers based on the ordered data tag; indicating that the one or more partial data units are available for consumption; and incrementing the next expected tag value.
In data processing systems, maintaining data integrity and order is critical when handling read responses from storage devices or memory systems. A common challenge arises when read responses arrive out of sequence, which can disrupt processing pipelines and lead to errors. This invention addresses this problem by implementing a method to manage out-of-order read responses while ensuring data consistency and availability. The method involves comparing the order tag value of a received read response with a next expected tag value. If the tag value does not match the expected value, the response is queued, and its partial data units are written to an ordered buffer but marked as unavailable for consumption. This prevents incomplete or misordered data from being processed prematurely. If the tag value matches the expected value, the partial data units are written to the appropriate buffer and immediately marked as available for consumption, and the next expected tag value is incremented. This ensures that data is only consumed when it is in the correct order, maintaining system reliability. The method also includes mechanisms for handling ordered buffers, which store data in a sequence that aligns with the expected order of read responses. By dynamically tracking and validating tag values, the system efficiently manages out-of-order data while minimizing processing delays. This approach is particularly useful in high-performance computing environments where data integrity and timely processing are essential.
6. The method of claim 5 further comprises: when the order tag value of the current received read response compares favorably with the next expected tag value: determining whether the incremented next expected tag value is equal to or exceeds a queued tag; and when the incremented next expected tag value is equal to or exceeds a queued tag, indicating that content of a corresponding read response is now available for consumption.
This invention relates to data processing systems, specifically methods for managing read responses in a queued data retrieval system. The problem addressed is ensuring data integrity and proper sequencing when multiple read responses are received out of order, which can lead to data corruption or processing errors. The method involves tracking expected tag values for read responses to verify their correct order. When a read response is received, its order tag value is compared to the next expected tag value. If they match favorably, the system checks whether the incremented next expected tag value equals or exceeds a queued tag. If this condition is met, it indicates that the content of the corresponding read response is now available for consumption, ensuring that data is processed in the correct sequence. This prevents out-of-order data from being used prematurely, maintaining data integrity in systems where responses may arrive asynchronously or out of sequence. The method also includes mechanisms for handling queued tags, which represent pending read operations. By comparing the incremented next expected tag value to queued tags, the system determines when data from a read response can be safely processed without disrupting the expected order of operations. This is particularly useful in high-performance or distributed systems where response timing may vary. The approach ensures that data is only consumed when the correct sequence is confirmed, reducing errors in data-dependent processes.
7. The method of claim 1 further comprises: determining, by the processing entity, a unique data unit count value for each read operation of the “n” number of read operations, wherein a first data unit count value indicates a number of data units that are at least partially within the first logical data block.
This invention relates to data storage systems, specifically methods for managing read operations in a storage device. The problem addressed is efficiently tracking and processing data units during read operations to ensure accurate data retrieval, particularly when dealing with fragmented or partially overlapping data blocks. The method involves performing a series of "n" read operations to retrieve data from a storage medium. For each read operation, a processing entity determines a unique data unit count value, which represents the number of data units that are at least partially within a specific logical data block being accessed. The first data unit count value specifically indicates how many data units fall within the first logical data block of the storage medium. This count helps in identifying the exact data units that are relevant to the read operation, even if they are only partially contained within the logical block. The method also includes verifying the integrity of the retrieved data by comparing the data unit count values against expected values. If discrepancies are found, corrective actions such as re-reading the data or adjusting the read parameters are performed. This ensures that the data retrieved is accurate and complete, even in cases where the storage medium has fragmented or corrupted data blocks. The invention improves data retrieval efficiency and reliability by providing a precise way to track and validate data units during read operations, reducing errors and improving performance in storage systems.
8. The method of claim 7 , wherein the tracking comprises: decrementing the first data unit count value as data units of the number of data units that are at least partially within the first logical data block are consumed; and when the first data unit count value is zero, releasing an ordered buffer of the ordered buffers associated with the first logical data block.
This invention relates to data management in storage systems, specifically tracking and releasing memory buffers used for logical data blocks. The problem addressed is efficient memory management in systems where data is organized into logical blocks and processed in smaller data units, requiring precise tracking of buffer usage to avoid memory leaks or excessive consumption. The method involves tracking data units within a logical data block to determine when all units have been fully consumed. A count value is maintained for each logical data block, representing the number of data units at least partially contained within it. As data units are processed (consumed), this count is decremented. When the count reaches zero, indicating all data units have been fully processed, the associated ordered buffer is released. This ensures memory is freed only when no longer needed, optimizing system performance and preventing resource waste. The method applies to systems where data is divided into logical blocks and processed in smaller units, such as file systems, databases, or streaming applications. By dynamically tracking and releasing buffers, it improves memory efficiency and reduces overhead in data-intensive operations. The approach is particularly useful in environments with high data throughput or limited memory resources.
9. The method of claim 1 , wherein the processing entity comprises one or more of: one or more processing core resources of the computing device; one or more nodes of the computing device; one or more processing core resources of another computing device; and one or more nodes of the other computing device.
This invention relates to distributed computing systems and addresses the challenge of efficiently allocating and managing processing resources across multiple computing devices or nodes. The method involves dynamically assigning processing tasks to available resources within a computing environment, which may include one or more processing cores or nodes within a single device or across multiple interconnected devices. The system identifies available processing resources, such as individual processing cores or entire nodes, and distributes workloads accordingly to optimize performance and resource utilization. By leveraging both local and remote processing capabilities, the method ensures efficient task execution while balancing computational load. The approach is particularly useful in environments where tasks require varying levels of processing power or where resources are distributed across a network. The invention enhances scalability and flexibility in computing systems by dynamically adapting to available hardware resources, whether they reside within a single device or across multiple interconnected systems. This method improves efficiency in task processing by reducing bottlenecks and ensuring optimal use of available computational power.
10. The method of claim 1 further comprises: the volatile memory including random access memory; and the non-volatile memory including one or more of a solid-state memory device and a disk memory device, wherein the logical data blocks storing the plurality of data units are contiguous and wherein physical memory locations of the disk memory storing the plurality of data units is not contiguous.
This invention relates to a data storage system that manages data units across volatile and non-volatile memory, addressing the challenge of efficiently storing and retrieving data while optimizing performance and storage utilization. The system includes a volatile memory, such as random access memory (RAM), and a non-volatile memory, which may consist of solid-state memory devices (e.g., flash storage) or disk memory devices (e.g., hard disk drives). The data units are organized into logical data blocks that are contiguous in logical address space, but their physical storage locations in the disk memory are non-contiguous. This approach allows for efficient data management, where logical contiguity simplifies access and management, while physical non-contiguity enables flexible storage allocation, reducing fragmentation and improving performance. The system likely employs a mapping mechanism to translate between logical and physical addresses, ensuring that data can be accessed efficiently despite the physical non-contiguity. This method is particularly useful in environments where data must be frequently accessed and modified, such as in database systems or file storage solutions, where maintaining logical contiguity simplifies operations while physical non-contiguity optimizes storage efficiency.
11. A computer readable memory device comprises: a first memory section operable to store operational instructions that, when executed by a processing entity of a computing device, causes the processing entity to: identify a plurality of data units to read from non-volatile memory and to write into ordered buffers of volatile memory, wherein data units of the plurality of data units have a variety of data sizes, wherein the plurality of data units is stored in “n” number of logical data blocks of the non-volatile memory, wherein a data unit of the plurality of data units is at least partially stored in two or more logical data blocks of the “n” number of logical data blocks of the non-volatile memory, and wherein “n” is an integer greater than or equal to two; generate read operations regarding the plurality of data units, wherein the number of read operations equals “n”; and tag each read operation of the read operations with a unique ordered tag value, wherein a first read operation of the read operations is regarding a first logical data block of the “n” number of logical data blocks of the non-volatile memory and is tagged with a first ordered tag value; a second memory section operable to store operational instructions that, when executed by the processing entity, causes the processing entity to: receive read responses to the read operations from the non-volatile memory, wherein a first read response of the read responses is in response to the first read operation and includes the first ordered tag value; write data units contained in the read responses into the ordered buffers in accordance with the ordered tag values; and track consumption of the plurality of data units from the ordered buffers.
This invention relates to data management in computing systems, specifically optimizing the reading and writing of data units of varying sizes from non-volatile memory to volatile memory buffers. The problem addressed is the inefficient handling of data units that span multiple logical data blocks in non-volatile memory, leading to fragmented reads and processing delays. The system includes a computer-readable memory device with two memory sections. The first section stores instructions for identifying data units to read from non-volatile memory and write into ordered buffers in volatile memory. These data units may have varying sizes and may be partially stored across multiple logical data blocks. The system generates read operations equal in number to the logical data blocks (n), each tagged with a unique ordered value. For example, a first read operation targets a first logical data block and is tagged with a first ordered value. The second memory section stores instructions for receiving read responses from non-volatile memory, which include the ordered tag values. The system writes the data units from these responses into the ordered buffers according to their tag values and tracks the consumption of data units from the buffers. This ensures efficient data retrieval and processing, particularly when data spans multiple logical blocks. The method improves performance by maintaining order and tracking data flow in volatile memory buffers.
12. The computer readable memory device of claim 11 , wherein the first memory section further stores operational instructions that, when executed by the processing entity, causes the processing entity to identifying the plurality of data units by: receiving an operation that includes reading the plurality of data units from the disk memory and writing the plurality of data units into the ordered buffer.
This invention relates to a computer-readable memory device configured to manage data operations between a disk memory and an ordered buffer. The problem addressed is the efficient identification and handling of data units during read and write operations to ensure proper sequencing and integrity in data processing systems. The memory device includes a first memory section that stores operational instructions executable by a processing entity. These instructions enable the processing entity to identify a plurality of data units by receiving an operation that involves reading the data units from the disk memory and writing them into the ordered buffer. The ordered buffer is designed to maintain the data units in a specific sequence, ensuring that subsequent processing operations can access the data in the correct order. The processing entity executes the instructions to perform the read and write operations, ensuring that the data units are transferred accurately from the disk memory to the ordered buffer. This process may involve verifying the integrity of the data units during transfer and maintaining their sequential order within the buffer. The system may also include additional memory sections or processing components to support these operations, such as error detection and correction mechanisms to handle any discrepancies during data transfer. The invention aims to improve data management efficiency by ensuring that data units are correctly identified, sequenced, and transferred between storage and processing components, reducing the risk of errors and improving system performance.
13. The computer readable memory device of claim 11 , wherein the first memory section further stores operational instructions that, when executed by the processing entity, causes the processing entity to: access metadata regarding the plurality of data units to read; determine a specific number “n” of the “n” number of logical data blocks of the non-volatile memory based on the metadata; and allocate the specific number of logical data blocks of the volatile memory for the ordered buffers.
This invention relates to memory management in computing systems, specifically optimizing data handling between volatile and non-volatile memory. The problem addressed is inefficient data transfer and storage, particularly when dealing with large datasets that require buffering in volatile memory before being written to non-volatile storage. The solution involves dynamically allocating memory blocks based on metadata to improve performance and resource utilization. The system includes a computer-readable memory device with a first memory section that stores operational instructions. When executed by a processing entity, these instructions cause the system to access metadata associated with a plurality of data units to be read. The metadata is used to determine a specific number "n" of logical data blocks in non-volatile memory that will be involved in the operation. Based on this determination, the system allocates the same number "n" of logical data blocks in volatile memory to serve as ordered buffers. This ensures that the volatile memory is efficiently utilized according to the actual data requirements, reducing unnecessary allocations and improving system performance. The invention also includes a second memory section that stores data units and a processing entity that executes the instructions to manage data transfers between the volatile and non-volatile memory. The dynamic allocation of buffers based on metadata allows for adaptive memory management, which is particularly useful in systems handling variable-sized datasets or workloads with fluctuating memory demands. This approach minimizes latency and maximizes throughput by aligning buffer allocation with the actual data transfer needs.
14. The computer readable memory device of claim 13 , wherein the first memory section further stores operational instructions that, when executed by the processing entity, causes the processing entity to: execute an ordered buffer function of a process specific operating system of the computing device, wherein the process specific operating system overrides, with respect to the volatile memory, a general operating system of the computing device.
This invention relates to memory management in computing systems, specifically addressing the challenge of optimizing memory usage in environments where multiple operating systems or processes compete for volatile memory resources. The system involves a computer-readable memory device with a first memory section that stores operational instructions for a processing entity. These instructions enable the execution of an ordered buffer function within a process-specific operating system running on the computing device. The process-specific operating system overrides the general operating system's memory management functions with respect to volatile memory, allowing for more efficient and controlled allocation of memory resources. This override ensures that the process-specific operating system can prioritize and manage memory buffers independently of the general operating system's default behavior, improving performance and resource utilization in scenarios where multiple processes or operating systems coexist. The solution is particularly useful in systems requiring fine-grained control over memory allocation, such as embedded systems, virtualized environments, or real-time computing applications.
15. The computer readable memory device of claim 11 , wherein the second memory section further stores operational instructions that, when executed by the processing entity, causes the processing entity to write the data units by: comparing an order tag value of a current received read response of the read responses with a next expected tag value; when the order tag value of the current received read response compares unfavorably with the next expected tag value: queuing the tag of the current received read response; writing one or more partial data units contained in the current received read response to one of the ordered buffers based on the ordered data tag; and indicating that the one or more partial data units are not available for consumption; when the order tag value of the current received read response compares favorably with the next expected tag value: writing the one or more partial data units contained in the current received read response to one of the ordered buffers based on the ordered data tag; indicating that the one or more partial data units are available for consumption; and incrementing the next expected tag value.
This invention relates to data processing systems, specifically handling read responses in a memory system to ensure data integrity and ordered consumption. The problem addressed is maintaining correct data order and availability in systems where read responses may arrive out of sequence, which can disrupt processing or cause errors. The system includes a memory device with a processing entity and multiple memory sections. One section stores operational instructions for managing read responses. When a read response is received, the system compares its order tag value with the next expected tag value. If the tag does not match, the response is queued, partial data is written to an ordered buffer, and the data is marked as unavailable for consumption. If the tag matches, the partial data is written to the buffer, marked as available, and the next expected tag value is incremented. This ensures that data is only consumed in the correct order, preventing errors from out-of-sequence responses. The system also handles partial data units, allowing processing to continue even if a full response is not yet available. This approach improves reliability in memory systems where read operations may return responses asynchronously or out of order.
16. The computer readable memory device of claim 15 , wherein the second memory section further stores operational instructions that, when executed by the processing entity, causes the processing entity to: when the order tag value of the current received read response compares favorably with the next expected tag value: determining whether the incremented next expected tag value is equal to or exceeds a queued tag; and when the incremented next expected tag value is equal to or exceeds a queued tag, indicating that content of a corresponding read response is now available for consumption.
This invention relates to memory systems, specifically a method for managing read responses in a memory device to ensure data consistency and availability. The problem addressed is the need to track and validate read responses in a memory system to prevent data corruption or inconsistencies when multiple read operations are pending. The system includes a memory device with at least two memory sections: a first section storing operational instructions and a second section storing data and additional instructions. The second section contains a next expected tag value, which is incremented after each read response is successfully processed. The system also maintains a queued tag, representing a read operation that has been issued but not yet completed. When a read response is received, the system compares its order tag value with the next expected tag value. If they match, the system checks whether the incremented next expected tag value equals or exceeds the queued tag. If so, it indicates that the corresponding read response data is now available for consumption, ensuring that the data is valid and can be safely used by the processing entity. This mechanism prevents out-of-order read responses from being incorrectly processed, maintaining data integrity in the system.
17. The computer readable memory device of claim 11 , wherein the first memory section further stores operational instructions that, when executed by the processing entity, causes the processing entity to: determine a unique data unit count value for each read operation of the “n” number of read operations, wherein a first data unit count value indicates a number of data units that are at least partially within the first logical data block.
This invention relates to data storage systems, specifically methods for managing read operations in memory devices to improve efficiency and accuracy. The problem addressed is the need to track and process data units that span across logical data blocks during read operations, ensuring accurate data retrieval and minimizing errors. The system includes a memory device with multiple memory sections, where one section stores operational instructions for a processing entity. These instructions enable the processing entity to perform a series of read operations on a memory array. The memory array is divided into logical data blocks, and the system is designed to handle cases where data units (e.g., bits, bytes, or larger data segments) are partially located within a first logical data block and partially in adjacent blocks. A key feature is the determination of a unique data unit count value for each read operation. This count value indicates the number of data units that are at least partially within the first logical data block during each read operation. By tracking this count, the system can accurately identify and process data units that span block boundaries, ensuring that no data is lost or corrupted during retrieval. This is particularly useful in high-density storage systems where data alignment may not perfectly match logical block boundaries. The system may also include additional features, such as error correction mechanisms, to further enhance data integrity. The processing entity executes the stored instructions to perform the read operations and generate the data unit count values, providing a robust solution for managing data across logical block boundaries in memory devices.
18. The computer readable memory device of claim 17 , wherein the second memory section further stores operational instructions that, when executed by the processing entity, causes the processing entity to track by: decrementing the first data unit count value as data units of the number of data units that are at least partially within the first logical data block are consumed; and when the first data unit count value is zero, releasing an ordered buffer of the ordered buffers associated with the first logical data block.
This invention relates to memory management in computing systems, specifically for tracking and releasing memory buffers associated with logical data blocks. The problem addressed is efficient memory utilization and proper buffer management when data units within a logical data block are consumed or processed. The system involves a computer-readable memory device storing operational instructions for a processing entity. The memory device includes a first memory section storing a plurality of ordered buffers, each associated with a logical data block, and a second memory section storing data unit count values for each logical data block. The count values track the number of data units within each logical data block that remain unprocessed. When data units within a logical data block are consumed, the system decrements the corresponding data unit count value. Once the count value reaches zero, indicating all data units in the logical data block have been processed, the system releases the associated ordered buffer. This ensures memory is freed only when no remaining data units depend on the buffer, preventing premature release and potential data loss while optimizing memory usage. The system may also handle cases where data units span multiple logical data blocks, ensuring accurate tracking and release of buffers.
19. The computer readable memory device of claim 11 , wherein the processing entity comprises one or more of: one or more processing core resources of the computing device; one or more nodes of the computing device; one or more processing core resources of another computing device; and one or more nodes of the other computing device.
This invention relates to distributed computing systems and addresses the challenge of efficiently allocating and managing processing resources across multiple computing devices or nodes. The system involves a computer-readable memory device storing instructions that, when executed, enable a processing entity to dynamically allocate and utilize processing resources. The processing entity can include one or more processing core resources or nodes from the same computing device or from another computing device. This flexibility allows the system to optimize resource allocation based on workload demands, improving performance and efficiency in distributed computing environments. The invention ensures that processing tasks are distributed across available resources, whether they are local to the device or remote, enhancing scalability and fault tolerance. By leveraging multiple processing cores or nodes, the system can handle complex computations more effectively, reducing bottlenecks and improving overall system responsiveness. The invention is particularly useful in scenarios requiring high-performance computing, such as data processing, scientific simulations, or real-time analytics, where efficient resource management is critical.
20. The computer readable memory device of claim 11 further comprises: the volatile memory including random access memory; and the non-volatile memory including one or more of a solid-state memory device and a disk memory device, wherein the logical data blocks storing the plurality of data units are contiguous and wherein physical memory locations of the disk memory storing the plurality of data units is not contiguous.
This invention relates to a computer-readable memory device designed to optimize data storage and retrieval efficiency. The device addresses the challenge of managing data units across different memory types, particularly when dealing with non-contiguous physical storage locations in disk memory while maintaining logical contiguity for performance and simplicity. The memory device includes both volatile and non-volatile memory components. The volatile memory consists of random access memory (RAM), which provides fast access for active data. The non-volatile memory includes at least one of a solid-state memory device (e.g., flash storage) or a disk memory device (e.g., hard disk drive), which offers persistent storage for data units. The data units are stored in logical data blocks that appear contiguous to the system, even though their physical locations in disk memory may be non-contiguous. This separation of logical and physical storage allows for efficient data management, particularly in systems where disk fragmentation or wear-leveling techniques are employed. The invention ensures that data retrieval and storage operations remain streamlined, regardless of the underlying physical storage layout. This approach is particularly useful in systems requiring high performance and reliability, such as databases, file systems, or embedded storage solutions.
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July 14, 2020
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