Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A device capable of activating memory at runtime, comprising: processing circuitry to execute operations related to at least an operating system in the device and to suspend execution of the operations when in system management mode; and memory circuitry to receive at least one memory module, wherein upon receiving the at least one memory module the memory circuitry is to trigger the operating system to at least prepare configuration data related to the at least one memory module for application during a quiescent period in the device, wherein the processing circuitry is to apply the configuration data during the quiescent period that is initiated after entering the system management mode; wherein the operating system is further to perform operations related to activating the at least one memory module; wherein the processing circuitry comprises at least memory controller circuitry and the memory activation operations comprise training the memory controller circuitry to interact with the at least one memory module; wherein the memory circuitry comprises at least dual data rate interface circuitry and the memory activation operations comprise training the dual data rate interface circuitry to interact with the at least one memory module; and wherein the memory activation operations comprise testing at least one of the memory controller circuitry or the dual data rate circuitry with the at least one memory module.
A device capable of activating memory at runtime efficiently separates tasks between its operating system (OS) and system management mode (SMM). It includes processing circuitry, which executes OS operations but suspends them when in SMM, and memory circuitry to receive memory modules. Upon receiving a memory module, the memory circuitry triggers the OS to perform memory activation operations and prepare configuration data for the module. These OS operations include training the processing circuitry's memory controller circuitry and the memory circuitry's dual data rate interface circuitry to interact with the new module, and also testing these trained components. The processing circuitry then applies the prepared configuration data during a quiescent (inactive) period, which is initiated after the device enters SMM, thereby minimizing SMM's impact on normal operations.
2. The device of claim 1 , wherein the at least one memory module comprises at least one memory riser including at least one dual in-line memory module.
This device efficiently activates memory at runtime by having its operating system (OS) perform initial memory activation operations, such as preparing configuration data and training memory controller and dual data rate interface circuitry for a new memory module, before a brief system management mode (SMM) period. During a quiescent period in SMM, processing circuitry applies this pre-prepared data, including training and testing results, to fully activate the module. Specifically, the memory module that is activated by this device is a memory riser, which itself contains at least one dual in-line memory module (DIMM).
3. The device of claim 1 , wherein the memory activation operations comprise causing the device to provide power to the at least one memory module.
This device efficiently activates memory at runtime by offloading much of the activation work to its operating system (OS). When a memory module is received, the OS prepares configuration data and performs activation operations, which include training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing these components. Subsequently, the device's processing circuitry applies this data during a quiescent period within system management mode (SMM) to minimize disruption. A key memory activation operation performed by the OS involves causing the device to provide electrical power to the newly installed memory module.
4. The device of claim 1 , wherein in preparing the configuration data the operating system is to configure at least one of operational features of the at least one memory module or address decoding corresponding to the at least one memory module.
This device efficiently activates memory at runtime by leveraging its operating system (OS) to perform critical activation steps. When a memory module is received, the OS prepares configuration data and executes memory activation operations, such as training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing these components. The device's processing circuitry then applies this data during a quiescent period in system management mode (SMM) to reduce SMM overhead. When the OS prepares this configuration data, it specifically involves setting up either the operational features of the memory module or its address decoding scheme.
5. The device of claim 1 , wherein the operating system is to provide the configuration data to a system management interrupt handler in the processing circuitry to apply during the system management mode.
This device efficiently activates memory at runtime by separating memory activation tasks. Its operating system (OS) performs initial activation operations upon receiving a memory module, including preparing configuration data, training memory controller circuitry and dual data rate interface circuitry for interaction with the module, and testing these components. The processing circuitry then applies this data during a quiescent period in system management mode (SMM). More specifically, the OS provides the prepared configuration data directly to a system management interrupt (SMI) handler located within the processing circuitry, enabling the SMI handler to apply this data effectively during SMM.
6. A method for activating memory at runtime in a device, comprising: powering on at least one memory module received in memory circuitry in the device; causing an operating system in the device to perform memory activation operations including at least preparing configuration data related to the at least one memory module to be applied during a quiescent period occurring in a system management mode in the device; causing the operating system to provide the configuration data to processing circuitry in the device; causing the processing circuitry to enter system management mode in the device; and causing the processing circuitry to apply the configuration data during the quiescent period; wherein performing the memory activation operations comprises training memory controller circuitry in the processing circuitry to interact with the at least one memory module; wherein performing the memory activation operations comprises training dual data rate interface circuitry in the memory circuitry to interact with the at least one memory module; and wherein performing the memory activation operations comprises testing at least one of the memory controller circuitry or the dual data rate circuitry with the at least one memory module.
A method for activating memory at runtime in a device starts by powering on a memory module received in the device's memory circuitry. Next, the operating system (OS) is instructed to perform memory activation operations. These OS tasks include preparing configuration data related to the memory module, which will be applied during a quiescent (inactive) period in system management mode (SMM). The OS's activation specifically involves training the processing circuitry's memory controller circuitry and the memory circuitry's dual data rate interface circuitry to interact correctly with the new memory module, and testing these components. The OS then provides this configuration data to the processing circuitry, which subsequently enters SMM and applies the data during the quiescent period, allowing for efficient memory activation with minimal SMM disruption.
7. The method of claim 6 , further comprising: initializing a driver for the at least one memory module in the operating system prior to powering on the at least one memory module.
This method for efficiently activating memory at runtime in a device involves powering on a memory module and having the operating system (OS) perform key activation operations. These OS operations include preparing configuration data for application during a quiescent period in system management mode (SMM), as well as training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing them. The OS then provides this data to the processing circuitry, which enters SMM and applies the data during the quiescent period. An additional step in this process is initializing a dedicated driver for the memory module within the OS before the memory module is powered on.
8. The method of claim 6 , wherein the at least one memory module comprises at least one memory riser including at least one dual in-line memory module.
A method for managing memory modules in a computing system addresses the challenge of efficiently organizing and expanding memory capacity. The method involves using at least one memory module, which includes at least one memory riser, to support at least one dual in-line memory module (DIMM). The memory riser provides a physical and electrical interface that allows the DIMM to be connected to the system's memory controller, enabling data transfer and communication. The DIMM itself is a standardized memory module containing integrated circuits for storing data, typically used in personal computers and servers. The method ensures compatibility and scalability by allowing multiple DIMMs to be installed via the riser, expanding the system's memory capacity while maintaining proper signal integrity and performance. This approach simplifies memory upgrades and optimizes space utilization in compact computing environments. The memory riser may also include additional components, such as connectors or circuit traces, to facilitate reliable data transmission between the DIMM and the system's memory controller. The method is particularly useful in systems where direct DIMM installation is impractical due to space constraints or design limitations, providing a flexible solution for memory expansion.
9. The method of claim 6 , wherein preparing the configuration data comprises configuring at least one of operational features of the at least one memory module or address decoding corresponding to the at least one memory module.
This method for efficiently activating memory at runtime in a device involves powering on a memory module and having the operating system (OS) perform key activation operations. These OS operations include preparing configuration data for application during a quiescent period in system management mode (SMM), as well as training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing them. The OS then provides this data to the processing circuitry, which enters SMM and applies the data during the quiescent period. Specifically, the step of preparing the configuration data involves configuring either the operational features of the memory module or its address decoding scheme.
10. The method of claim 6 , wherein the configuration data is provided to a system management interrupt handler in the processing circuitry to apply during the system management mode.
This method for efficiently activating memory at runtime in a device involves powering on a memory module and having the operating system (OS) perform key activation operations. These OS operations include preparing configuration data for application during a quiescent period in system management mode (SMM), as well as training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing them. The OS then provides this data to the processing circuitry, which enters SMM and applies the data during the quiescent period. More specifically, the prepared configuration data is provided to a system management interrupt (SMI) handler located within the processing circuitry for application during SMM.
11. At least one machine-readable storage device having stored thereon, individually or in combination, instructions for activating memory at runtime in a device that, when executed by one or more processors, cause the one or more processors to: power on at least one memory module received in memory circuitry in a device; cause an operating system in the device to perform memory activation operations including at least preparing configuration data related to the at least one memory module to be applied during a quiescent period occurring in a system management mode in the device; cause the operating system to provide the configuration data to processing circuitry in the device; cause the processing circuitry to enter system management mode in the device; and cause the processing circuitry to apply the configuration data during the quiescent period; wherein the instructions to perform the memory activation operations comprise instructions to train memory controller circuitry in the processing circuitry to interact with the at least one memory module; wherein the instructions to perform the memory activation operations comprise instructions to train dual data rate interface circuitry in the memory circuitry to interact with the at least one memory module; and wherein the instructions to perform the memory activation operation comprises instructions to test at least one of the memory controller circuitry or the dual data rate circuitry with the at least one memory module.
A machine-readable storage device contains instructions for activating memory at runtime in a device. When executed by one or more processors, these instructions cause the processors to power on a memory module received in the device's memory circuitry. The instructions then cause an operating system (OS) to perform memory activation operations, which include preparing configuration data for the memory module. This data is intended for application during a quiescent (inactive) period when the device is in system management mode (SMM). The OS's activation operations specifically comprise training memory controller circuitry within the processing circuitry and dual data rate interface circuitry within the memory circuitry to interact with the memory module, along with testing these trained components. After preparation, the instructions cause the OS to provide the configuration data to the processing circuitry, which then enters SMM and applies the configuration data during the quiescent period.
12. The machine-readable storage device of claim 11 , further comprising, instructions that, when executed by one or more processors, cause the one or more processors to: initialize a driver for the at least one memory module in the operating system prior to powering on the at least one memory module.
A machine-readable storage device contains instructions for efficiently activating memory at runtime in a device. When executed, these instructions cause processors to power on a memory module, then cause the operating system (OS) to perform memory activation operations. These OS tasks include preparing configuration data for application during a quiescent period in system management mode (SMM), training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing them. The instructions then cause the OS to provide this data to the processing circuitry, which enters SMM and applies the data. Additionally, the storage device includes instructions to initialize a driver for the memory module within the OS prior to the memory module being powered on.
13. The machine-readable storage device of claim 11 , wherein the at least one memory module comprises at least one memory riser including at least one dual in-line memory module.
A machine-readable storage device contains instructions for efficiently activating memory at runtime in a device. When executed, these instructions cause processors to power on a memory module, then cause the operating system (OS) to perform memory activation operations. These OS tasks include preparing configuration data for application during a quiescent period in system management mode (SMM), training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing them. The instructions then cause the OS to provide this data to the processing circuitry, which enters SMM and applies the data. Specifically, the memory module referred to in these instructions is a memory riser, which itself includes at least one dual in-line memory module (DIMM).
14. The machine-readable storage device of claim 11 , wherein the instructions to prepare the configuration data comprises instructions to configure at least one of operational features of the at least one memory module or address decoding corresponding to the at least one memory module.
A machine-readable storage device contains instructions for efficiently activating memory at runtime in a device. When executed, these instructions cause processors to power on a memory module, then cause the operating system (OS) to perform memory activation operations. These OS tasks include preparing configuration data for application during a quiescent period in system management mode (SMM), training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing them. The instructions then cause the OS to provide this data to the processing circuitry, which enters SMM and applies the data. More specifically, the instructions for preparing the configuration data involve configuring either the operational features of the memory module or its address decoding scheme.
15. The machine-readable storage device of claim 11 , wherein the configuration data is provided to a system management interrupt handler in the processing circuitry to apply during the system management mode.
A machine-readable storage device contains instructions for efficiently activating memory at runtime in a device. When executed, these instructions cause processors to power on a memory module, then cause the operating system (OS) to perform memory activation operations. These OS tasks include preparing configuration data for application during a quiescent period in system management mode (SMM), training memory controller circuitry and dual data rate interface circuitry to interact with the module, and testing them. The instructions then cause the OS to provide this data to the processing circuitry, which enters SMM and applies the data. Specifically, the prepared configuration data is provided to a system management interrupt (SMI) handler located within the processing circuitry for application during SMM.
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July 21, 2020
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