Efficient Memory Activation at Runtime

1. A device capable of activating memory at runtime, comprising: processing circuitry to execute operations related to at least an operating system in the device and to suspend execution of the operations when in system management mode; and memory circuitry to receive at least one memory module, wherein upon receiving the at least one memory module the memory circuitry is to trigger the operating system to at least prepare configuration data related to the at least one memory module for application during a quiescent period in the device, wherein the processing circuitry is to apply the configuration data during the quiescent period that is initiated after entering the system management mode; wherein the operating system is further to perform operations related to activating the at least one memory module; wherein the processing circuitry comprises at least memory controller circuitry and the memory activation operations comprise training the memory controller circuitry to interact with the at least one memory module; wherein the memory circuitry comprises at least dual data rate interface circuitry and the memory activation operations comprise training the dual data rate interface circuitry to interact with the at least one memory module; and wherein the memory activation operations comprise testing at least one of the memory controller circuitry or the dual data rate circuitry with the at least one memory module.

2. The device of claim 1 , wherein the at least one memory module comprises at least one memory riser including at least one dual in-line memory module.

3. The device of claim 1 , wherein the memory activation operations comprise causing the device to provide power to the at least one memory module.

4. The device of claim 1 , wherein in preparing the configuration data the operating system is to configure at least one of operational features of the at least one memory module or address decoding corresponding to the at least one memory module.

5. The device of claim 1 , wherein the operating system is to provide the configuration data to a system management interrupt handler in the processing circuitry to apply during the system management mode.

6. A method for activating memory at runtime in a device, comprising: powering on at least one memory module received in memory circuitry in the device; causing an operating system in the device to perform memory activation operations including at least preparing configuration data related to the at least one memory module to be applied during a quiescent period occurring in a system management mode in the device; causing the operating system to provide the configuration data to processing circuitry in the device; causing the processing circuitry to enter system management mode in the device; and causing the processing circuitry to apply the configuration data during the quiescent period; wherein performing the memory activation operations comprises training memory controller circuitry in the processing circuitry to interact with the at least one memory module; wherein performing the memory activation operations comprises training dual data rate interface circuitry in the memory circuitry to interact with the at least one memory module; and wherein performing the memory activation operations comprises testing at least one of the memory controller circuitry or the dual data rate circuitry with the at least one memory module.

7. The method of claim 6 , further comprising: initializing a driver for the at least one memory module in the operating system prior to powering on the at least one memory module.

8. The method of claim 6 , wherein the at least one memory module comprises at least one memory riser including at least one dual in-line memory module.

9. The method of claim 6 , wherein preparing the configuration data comprises configuring at least one of operational features of the at least one memory module or address decoding corresponding to the at least one memory module.

10. The method of claim 6 , wherein the configuration data is provided to a system management interrupt handler in the processing circuitry to apply during the system management mode.

11. At least one machine-readable storage device having stored thereon, individually or in combination, instructions for activating memory at runtime in a device that, when executed by one or more processors, cause the one or more processors to: power on at least one memory module received in memory circuitry in a device; cause an operating system in the device to perform memory activation operations including at least preparing configuration data related to the at least one memory module to be applied during a quiescent period occurring in a system management mode in the device; cause the operating system to provide the configuration data to processing circuitry in the device; cause the processing circuitry to enter system management mode in the device; and cause the processing circuitry to apply the configuration data during the quiescent period; wherein the instructions to perform the memory activation operations comprise instructions to train memory controller circuitry in the processing circuitry to interact with the at least one memory module; wherein the instructions to perform the memory activation operations comprise instructions to train dual data rate interface circuitry in the memory circuitry to interact with the at least one memory module; and wherein the instructions to perform the memory activation operation comprises instructions to test at least one of the memory controller circuitry or the dual data rate circuitry with the at least one memory module.

12. The machine-readable storage device of claim 11 , further comprising, instructions that, when executed by one or more processors, cause the one or more processors to: initialize a driver for the at least one memory module in the operating system prior to powering on the at least one memory module.

13. The machine-readable storage device of claim 11 , wherein the at least one memory module comprises at least one memory riser including at least one dual in-line memory module.

14. The machine-readable storage device of claim 11 , wherein the instructions to prepare the configuration data comprises instructions to configure at least one of operational features of the at least one memory module or address decoding corresponding to the at least one memory module.

15. The machine-readable storage device of claim 11 , wherein the configuration data is provided to a system management interrupt handler in the processing circuitry to apply during the system management mode.