Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. An electronic device, comprising: a circuit board; a semiconductor device package mounted on the circuit board, the semiconductor device package including: a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, the second semiconductor device including a plurality of semiconductor chips stacked on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding covering a top surface of an uppermost semiconductor chip of the plurality of semiconductor chips of the second semiconductor device but not covering a top surface of the first semiconductor device; and a heat dissipation structure on the semiconductor device package, wherein: the top surface of the first semiconductor device is in contact with the heat dissipation structure, the top surface of the uppermost semiconductor chip of the plurality of semiconductor chips of the second semiconductor device is spaced apart from the heat dissipation structure by the molding, and no semiconductor chip is located between the uppermost semiconductor chip and the heat dissipation structure.
An electronic device includes a circuit board and a semiconductor device package mounted on it. The package has a substrate, a first semiconductor device, and a second semiconductor device placed side by side. The second device consists of multiple semiconductor chips stacked on the substrate. A molding surrounds the sidewalls of both devices. Critically, the molding covers the top surface of the uppermost chip of the second device, but *not* the top surface of the first device. A heat dissipation structure is positioned on the package. The first device's top surface directly contacts this heat dissipation structure. However, the top surface of the second device's uppermost chip is separated from the heat dissipation structure by the molding, with no other chips in between.
2. The electronic device as claimed in claim 1 , wherein a maximum length of the heat dissipation structure in a first direction parallel to the circuit board is greater than a maximum length of the semiconductor device package in the first direction.
An electronic device includes a circuit board and a semiconductor device package mounted on it. The package has a substrate, a first semiconductor device, and a second semiconductor device placed side by side. The second device consists of multiple semiconductor chips stacked on the substrate. A molding surrounds the sidewalls of both devices. Critically, the molding covers the top surface of the uppermost chip of the second device, but *not* the top surface of the first device. A heat dissipation structure is positioned on the package. The first device's top surface directly contacts this heat dissipation structure. However, the top surface of the second device's uppermost chip is separated from the heat dissipation structure by the molding, with no other chips in between. Additionally, the heat dissipation structure is larger than the semiconductor device package; specifically, its maximum length in a direction parallel to the circuit board is greater than the package's maximum length in that same direction.
3. The electronic device as claimed in claim 1 , wherein the heat dissipation structure includes a heat absorber, which is in contact with the semiconductor device package, and a heat transferer, which extends in a direction away from the semiconductor device package.
An electronic device includes a circuit board and a semiconductor device package mounted on it. The package has a substrate, a first semiconductor device, and a second semiconductor device placed side by side. The second device consists of multiple semiconductor chips stacked on the substrate. A molding surrounds the sidewalls of both devices. Critically, the molding covers the top surface of the uppermost chip of the second device, but *not* the top surface of the first device. A heat dissipation structure is positioned on the package. The first device's top surface directly contacts this heat dissipation structure. However, the top surface of the second device's uppermost chip is separated from the heat dissipation structure by the molding, with no other chips in between. This heat dissipation structure is further defined to include a heat absorber, which directly contacts the semiconductor device package, and a heat transferer, which extends outwards from the package to dissipate heat further.
4. The electronic device as claimed in claim 1 , further comprising a thermal interface material (TIM) layer between the top surface of the first semiconductor device and the heat dissipation structure.
An electronic device includes a circuit board and a semiconductor device package mounted on it. The package has a substrate, a first semiconductor device, and a second semiconductor device placed side by side. The second device consists of multiple semiconductor chips stacked on the substrate. A molding surrounds the sidewalls of both devices. Critically, the molding covers the top surface of the uppermost chip of the second device, but *not* the top surface of the first device. A heat dissipation structure is positioned on the package. Instead of direct contact, a thermal interface material (TIM) layer is placed between the top surface of the first device and the heat dissipation structure, improving thermal conductivity. The top surface of the second device's uppermost chip remains separated from the heat dissipation structure by the molding, with no other chips in between.
5. An electronic device, comprising: a circuit board; a semiconductor device package mounted on the circuit board; a thermal interface material (TIM) layer in contact with an upper portion of the semiconductor device package; and a heat dissipation structure in contact with the TIM layer, wherein the semiconductor device package includes: a package substrate connected to the circuit board; a first semiconductor device mounted on the package substrate, the first semiconductor device being in contact with the TIM layer; a second semiconductor device mounted on the package substrate, the second semiconductor device being spaced apart from the first semiconductor device in a first, lateral direction parallel to the circuit board; and a molding covering a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, wherein the second semiconductor device includes a plurality of semiconductor chips stacked in a second direction perpendicular to the package substrate, wherein a thickness of the first semiconductor device in the second direction is substantially equal to a thickness of the second semiconductor device in the second direction, and the molding does not cover a top surface of an uppermost semiconductor chip of the plurality of semiconductor chips of the second semiconductor device, wherein the top surface of the uppermost semiconductor chip of the plurality of semiconductor chips of the second semiconductor device is not covered with the TIM layer and is spaced apart from the heat dissipation structure, and wherein no semiconductor chip is located between the uppermost semiconductor chip and the heat dissipation structure.
An electronic device includes a circuit board and a semiconductor device package mounted on it. A thermal interface material (TIM) layer is placed on the package, with a heat dissipation structure on top of the TIM layer. The package has a substrate, a first semiconductor device (which contacts the TIM layer), and a second semiconductor device, laterally spaced from the first. The second device has multiple vertically stacked semiconductor chips. A molding covers the sidewalls of both devices. The vertical thickness of the first device is substantially equal to that of the second device. The molding does not cover the top surface of the second device's uppermost chip. This uppermost chip's top surface is not covered by the TIM layer and is spaced from the heat dissipation structure, with no semiconductor chips directly above it.
6. The electronic device as claimed in claim 5 , wherein a planar area of the heat dissipation structure is greater than a planar area of the semiconductor device package.
An electronic device includes a circuit board and a semiconductor device package mounted on it. A thermal interface material (TIM) layer is placed on the package, with a heat dissipation structure on top of the TIM layer. The package has a substrate, a first semiconductor device (which contacts the TIM layer), and a second semiconductor device, laterally spaced from the first. The second device has multiple vertically stacked semiconductor chips. A molding covers the sidewalls of both devices. The vertical thickness of the first device is substantially equal to that of the second device. The molding does not cover the top surface of the second device's uppermost chip. This uppermost chip's top surface is not covered by the TIM layer and is spaced from the heat dissipation structure, with no semiconductor chips directly above it. Additionally, the heat dissipation structure has a larger planar area than the semiconductor device package.
7. The electronic device as claimed in claim 5 , wherein a thickness of the first semiconductor device in the second direction is greater than a thickness of the second semiconductor device in the second direction.
An electronic device includes a circuit board and a semiconductor device package mounted on it. A thermal interface material (TIM) layer is placed on the package, with a heat dissipation structure on top of the TIM layer. The package has a substrate, a first semiconductor device (which contacts the TIM layer), and a second semiconductor device, laterally spaced from the first. The second device has multiple vertically stacked semiconductor chips. A molding covers the sidewalls of both devices. In this configuration, the vertical thickness of the first semiconductor device is greater than the vertical thickness of the second semiconductor device. The molding does not cover the top surface of the second device's uppermost chip. This uppermost chip's top surface is not covered by the TIM layer and is spaced from the heat dissipation structure, with no semiconductor chips directly above it.
8. The electronic device as claimed in claim 5 , wherein a thermal conductivity of the molding is lower than a thermal conductivity of the first semiconductor device.
An electronic device includes a circuit board and a semiconductor device package mounted on it. A thermal interface material (TIM) layer is placed on the package, with a heat dissipation structure on top of the TIM layer. The package has a substrate, a first semiconductor device (which contacts the TIM layer), and a second semiconductor device, laterally spaced from the first. The second device has multiple vertically stacked semiconductor chips. A molding covers the sidewalls of both devices. The vertical thickness of the first device is substantially equal to that of the second device. The molding does not cover the top surface of the second device's uppermost chip. This uppermost chip's top surface is not covered by the TIM layer and is spaced from the heat dissipation structure, with no semiconductor chips directly above it. Furthermore, the molding's thermal conductivity is lower than that of the first semiconductor device.
9. The electronic device as claimed in claim 5 , wherein the plurality of semiconductor chips are connected to one another through through-silicon vias (TSVs).
An electronic device includes a circuit board and a semiconductor device package mounted on it. A thermal interface material (TIM) layer is placed on the package, with a heat dissipation structure on top of the TIM layer. The package has a substrate, a first semiconductor device (which contacts the TIM layer), and a second semiconductor device, laterally spaced from the first. The second device has multiple vertically stacked semiconductor chips. These stacked chips are interconnected using through-silicon vias (TSVs). A molding covers the sidewalls of both devices. The vertical thickness of the first device is substantially equal to that of the second device. The molding does not cover the top surface of the second device's uppermost chip. This uppermost chip's top surface is not covered by the TIM layer and is spaced from the heat dissipation structure, with no semiconductor chips directly above it.
10. The electronic device as claimed in claim 5 , wherein an amount of heat generated by the first semiconductor device is greater than an amount of heat generated by the second semiconductor device.
An electronic device includes a circuit board and a semiconductor device package mounted on it. A thermal interface material (TIM) layer is placed on the package, with a heat dissipation structure on top of the TIM layer. The package has a substrate, a first semiconductor device (which contacts the TIM layer), and a second semiconductor device, laterally spaced from the first. The second device has multiple vertically stacked semiconductor chips. A molding covers the sidewalls of both devices. The vertical thickness of the first device is substantially equal to that of the second device. The molding does not cover the top surface of the second device's uppermost chip. This uppermost chip's top surface is not covered by the TIM layer and is spaced from the heat dissipation structure, with no semiconductor chips directly above it. Crucially, the first semiconductor device generates a greater amount of heat than the second semiconductor device.
11. An electronic device, comprising: a circuit board having a first region and a second region that are apart from each other; a semiconductor device package mounted on the first region of the circuit board, the semiconductor device package including: a package substrate, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, the second semiconductor device including a plurality of semiconductor chips stacked on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device but covering a top surface of an uppermost semiconductor chip of the plurality of semiconductor chips of the second semiconductor device; a heat dissipation structure on the semiconductor device package, the heat dissipation structure extending over the second region of the circuit board; and a thermal interface material (TIM) layer between the semiconductor device package and the heat dissipation structure, the top surface of the first semiconductor device being in contact with the TIM layer, wherein the top surface of the uppermost semiconductor chip of the plurality of semiconductor chips of the second semiconductor device is spaced apart from the heat dissipation structure by the molding, and wherein no semiconductor chip is located between the uppermost semiconductor chip and the heat dissipation structure.
The invention relates to an electronic device with an improved heat dissipation structure for semiconductor device packages. The device addresses the challenge of efficiently cooling high-density semiconductor packages, particularly those with stacked semiconductor chips, while maintaining structural integrity and thermal performance. The electronic device includes a circuit board with two distinct regions. A semiconductor device package is mounted on the first region of the circuit board. The package contains a package substrate with a first semiconductor device and a second semiconductor device mounted side by side. The second semiconductor device consists of multiple semiconductor chips stacked on the package substrate. A molding material surrounds the sidewalls of both semiconductor devices but does not cover the top surface of the first semiconductor device, allowing direct thermal contact. However, the molding does cover the top surface of the uppermost chip in the second semiconductor device, preventing direct contact with the heat dissipation structure. A heat dissipation structure is placed over the second region of the circuit board and extends over the semiconductor device package. A thermal interface material (TIM) layer is positioned between the package and the heat dissipation structure, ensuring thermal conductivity. The first semiconductor device's top surface directly contacts the TIM layer, while the uppermost chip of the second semiconductor device remains spaced apart from the heat dissipation structure due to the molding. No additional semiconductor chips are placed between the uppermost chip and the heat dissipation structure, optimizing heat transfer while maintaining structural stability. This design ensures efficient cooling for both single and
Unknown
July 28, 2020
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.