Self-Timed Clocked Processor Architecture

1. A self-timed clocked synchronous processor comprising: a combinatorial logic (CL) block operated at an operating voltage of the processor, the CL block having: CL logic to process the CL input data signals from a first register using CL data process values to output CL output data signals to a second register, the CL logic having a critical path with propagation delay that is a minimum allowable clock period to perform data processing of the CL logic at the operating voltage of the processor without a timing error; a critical path oscillator operated at the operating voltage of the processor and having: oscillator logic to simulate the critical path and to create an oscillator clock signal with a period that is greater than the minimum allowable clock period; an oscillator output to output an oscillator clock signal to clock the first register, the second register and a power manager; and the power manager operated at the operating voltage of the processor and having: an oscillator clock signal input to receive the oscillator clock signal; a time reference input to receive an external time reference signal; and a bias voltage output to output the operating voltage of the processor based on the time reference signal and the oscillator clock signal.

2. The self-timed processor of claim 1 , wherein the critical path and the critical path oscillator each have a propagation delay between when they receive inputs and when they provide an output that are dependent upon the operating voltage; and wherein the critical path oscillator estimates a propagation delay of the critical path and generates the oscillator clock signal certain to have a period longer than the delay time of the critical path.

3. The self-timed processor of claim 1 , wherein the critical path has a first set CL logic gates; and wherein the critical path oscillator has a second set of gates that includes the first set of gates and at least one additional gate.

4. The self-timed processor of claim 1 , wherein the critical path oscillator has an odd number of inverting gates connected in a ring and has a number of gates that is at least half a number of gates of the critical path.

5. The self-timed processor of claim 1 , wherein the CL logic has digital logic gates and digital registers to process the CL input data signals using CL data process values to create the CL output data signals from the CL data process values.

6. The self-timed processor of claim 1 , wherein the power manager includes circuitry to reduce the operating voltage to a lowest value needed for the critical path to perform data processing of the CL logic at the operating voltage of the processor without a timing error.

7. The self-timed processor of claim 1 , wherein the power manager includes circuitry to output the operating voltage at a level sufficient to cause the critical path to perform data processing of the CL logic at the operating voltage of the processor without a timing error.

8. The self-timed processor of claim 1 , wherein the power manager includes a comparator to compare the oscillator clock signal and the time reference signal to set the operating voltage such that the period of the oscillator clock signal is shorter than a period of the time reference signal.

9. The self-timed processor of claim 2 , wherein a timing for the first register to read data from the CL block is determined by the oscillator clock signal.

10. A self-timed clocked synchronous processor comprising: a combinatorial logic (CL) block operated at a speed dependent upon an operating voltage of the processor, the CL block having: CL logic to process CL input data signals received from a first register using CL data process values, the CL logic having a critical path with propagation delay between receiving the input data and outputting data to a second register that is a minimum allowable clock period to perform data processing of the CL logic at the operating voltage of the processor without a timing error; a critical path oscillator operated at a speed dependent upon the operating voltage of the processor and having: an oscillator output to output an oscillator clock signal to clock the first register, the second register and a power manager, the oscillator clock signal having a period that is greater than the minimum allowable clock period; and the power manager having: a bias voltage generator to output the operating voltage of the processor based on the oscillator clock signal and an external time reference signal.

11. The self-timed processor of claim 10 , wherein the critical path and the critical path oscillator each have a propagation delay between when they receive inputs and when they provide an output that are dependent upon the operating voltage; wherein a timing for the first register to read data from the CL block is determined by the oscillator clock signal; and wherein the critical path oscillator estimates a propagation delay of the critical path and generates the oscillator clock signal certain to have a period longer than the delay time of the critical path.

12. The self-timed processor of claim 10 , wherein the critical path has a first set CL logic gates; and wherein the critical path oscillator has a second set of gates that includes the first set of gates and at least one additional gate; or wherein the critical path oscillator has an odd number of inverting gates connected in a ring and has a number of gates that is at least half a number of gates of the critical path.

13. The self-timed processor of claim 10 , wherein the CL logic has digital logic gates and digital registers to process the CL input data signals using CL data process values to create the CL output data signals from the CL data process values.

14. The self-timed processor of claim 10 , wherein the power manager includes circuitry to reduce the operating voltage to a lowest value needed for the critical path to perform data processing of the CL logic at the operating voltage of the processor without a timing error.

15. The self-timed processor of claim 10 , wherein the power manager includes a comparator to compare the oscillator clock signal and the time reference signal to set the operating voltage such that the period of the oscillator clock signal is shorter than a period of the time reference signal.

16. A method of processing data within a self-timed clocked synchronous processor comprising: operating a combinatorial logic (CL) block at an operating voltage of the processor to process CL input data signals from a first register using CL data process values and to provide CL output data signals from the CL block to a second register, the CL block having a critical path that operates at the operating voltage with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block of the processor without a timing error; operating a critical path oscillator at the operating voltage of the processor to output an oscillator clock signal with a period that is greater than the minimum allowable clock period to clock the first register, the second register and a power manager; and operating the power manager to output the operating voltage of the processor based on the oscillator clock signal and an external time reference signal.

17. The method of claim 16 , wherein the critical path and the critical path oscillator each have a propagation delay between when they receive inputs and when they provide an output that are dependent upon the operating voltage; wherein a timing for the first register to read data from the CL block is determined by the oscillator clock signal; and wherein operating the critical path oscillator generates the oscillator clock signal certain to have a period longer than the delay time of the critical path.

18. The method of claim 16 , wherein the propagation delay of the critical path oscillator is at least a delay of one logic gate more than the propagation delay of the critical path.

19. The method of claim 16 , wherein the power manager reduces the operating voltage to a lowest value needed for the critical path to perform data processing of the CL block at the operating voltage of the processor without a timing error.

20. The method of claim 16 , wherein outputting the operating voltage includes comparing the oscillator clock signal and the time reference signal, and setting the operating voltage such that the period of the oscillator clock signal is shorter than a period of the time reference signal.