Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A self-timed clocked synchronous processor comprising: a combinatorial logic (CL) block operated at an operating voltage of the processor, the CL block having: CL logic to process the CL input data signals from a first register using CL data process values to output CL output data signals to a second register, the CL logic having a critical path with propagation delay that is a minimum allowable clock period to perform data processing of the CL logic at the operating voltage of the processor without a timing error; a critical path oscillator operated at the operating voltage of the processor and having: oscillator logic to simulate the critical path and to create an oscillator clock signal with a period that is greater than the minimum allowable clock period; an oscillator output to output an oscillator clock signal to clock the first register, the second register and a power manager; and the power manager operated at the operating voltage of the processor and having: an oscillator clock signal input to receive the oscillator clock signal; a time reference input to receive an external time reference signal; and a bias voltage output to output the operating voltage of the processor based on the time reference signal and the oscillator clock signal.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path whose propagation delay defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, which simulates this critical path and generates an oscillator clock signal with a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals to ensure correct operation.
2. The self-timed processor of claim 1 , wherein the critical path and the critical path oscillator each have a propagation delay between when they receive inputs and when they provide an output that are dependent upon the operating voltage; and wherein the critical path oscillator estimates a propagation delay of the critical path and generates the oscillator clock signal certain to have a period longer than the delay time of the critical path.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path whose propagation delay, which is dependent on the operating voltage, defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, and whose propagation delay is also dependent on the operating voltage. This oscillator simulates and estimates the propagation delay of the critical path, generating an oscillator clock signal that is certain to have a period safely greater than the critical path's delay. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals to ensure correct operation.
3. The self-timed processor of claim 1 , wherein the critical path has a first set CL logic gates; and wherein the critical path oscillator has a second set of gates that includes the first set of gates and at least one additional gate.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path (composed of a first set of CL logic gates) whose propagation delay defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, which simulates this critical path. This critical path oscillator consists of a second set of gates that includes all the gates from the critical path's first set, plus at least one additional gate, ensuring its oscillator clock signal has a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals to ensure correct operation.
4. The self-timed processor of claim 1 , wherein the critical path oscillator has an odd number of inverting gates connected in a ring and has a number of gates that is at least half a number of gates of the critical path.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path whose propagation delay defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, which simulates this critical path. This oscillator is structured with an odd number of inverting gates connected in a ring, and it contains at least half the number of gates found in the critical path, generating an oscillator clock signal with a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals to ensure correct operation.
5. The self-timed processor of claim 1 , wherein the CL logic has digital logic gates and digital registers to process the CL input data signals using CL data process values to create the CL output data signals from the CL data process values.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block's CL logic, composed of digital logic gates and digital registers, operates at the processor's operating voltage and processes CL input data signals using specific data process values. The CL block has a critical path whose propagation delay defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, which simulates this critical path and generates an oscillator clock signal with a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals to ensure correct operation.
6. The self-timed processor of claim 1 , wherein the power manager includes circuitry to reduce the operating voltage to a lowest value needed for the critical path to perform data processing of the CL logic at the operating voltage of the processor without a timing error.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path whose propagation delay defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, which simulates this critical path and generates an oscillator clock signal with a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals. Specifically, the power manager includes circuitry to reduce the operating voltage to the lowest value required for the CL logic's critical path to perform data processing without any timing errors.
7. The self-timed processor of claim 1 , wherein the power manager includes circuitry to output the operating voltage at a level sufficient to cause the critical path to perform data processing of the CL logic at the operating voltage of the processor without a timing error.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path whose propagation delay defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, which simulates this critical path and generates an oscillator clock signal with a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals. The power manager ensures the operating voltage is at a level sufficient for the CL logic's critical path to perform data processing without any timing errors.
8. The self-timed processor of claim 1 , wherein the power manager includes a comparator to compare the oscillator clock signal and the time reference signal to set the operating voltage such that the period of the oscillator clock signal is shorter than a period of the time reference signal.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path whose propagation delay defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, which simulates this critical path and generates an oscillator clock signal with a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks both the first and second registers, and is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals. The power manager includes a comparator to compare the oscillator clock signal and the time reference signal, setting the operating voltage so that the oscillator clock signal's period is shorter than the time reference signal's period, thus making the processor effectively run faster than the reference.
9. The self-timed processor of claim 2 , wherein a timing for the first register to read data from the CL block is determined by the oscillator clock signal.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block that processes input data signals from a first register and outputs data signals to a second register. This CL block operates at the processor's operating voltage and has a critical path whose propagation delay, which is dependent on the operating voltage, defines the minimum safe clock period for error-free data processing. The processor also has a critical path oscillator, operating at the same voltage, and whose propagation delay is also dependent on the operating voltage. This oscillator simulates and estimates the propagation delay of the critical path, generating an oscillator clock signal that is certain to have a period safely greater than the critical path's delay. This oscillator clock signal clocks both the first and second registers, and determines the timing for the first register to read data from the CL block. It is also sent to a power manager. The power manager receives this oscillator clock and an external time reference signal, then outputs the processor's operating voltage, dynamically adjusting it based on these two signals to ensure correct operation.
10. A self-timed clocked synchronous processor comprising: a combinatorial logic (CL) block operated at a speed dependent upon an operating voltage of the processor, the CL block having: CL logic to process CL input data signals received from a first register using CL data process values, the CL logic having a critical path with propagation delay between receiving the input data and outputting data to a second register that is a minimum allowable clock period to perform data processing of the CL logic at the operating voltage of the processor without a timing error; a critical path oscillator operated at a speed dependent upon the operating voltage of the processor and having: an oscillator output to output an oscillator clock signal to clock the first register, the second register and a power manager, the oscillator clock signal having a period that is greater than the minimum allowable clock period; and the power manager having: a bias voltage generator to output the operating voltage of the processor based on the oscillator clock signal and an external time reference signal.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block whose speed depends on the processor's operating voltage. The CL block has CL logic that processes input data signals from a first register and outputs data to a second register. This CL logic contains a critical path whose propagation delay (from input to output to the second register) defines the minimum allowable clock period for error-free data processing at that operating voltage. The processor also has a critical path oscillator, whose speed also depends on the operating voltage. This oscillator outputs an oscillator clock signal with a period safely greater than the minimum allowable clock period, which clocks both the first and second registers, and a power manager. The power manager includes a bias voltage generator that outputs the processor's operating voltage, dynamically setting it based on the oscillator clock signal and an external time reference signal.
11. The self-timed processor of claim 10 , wherein the critical path and the critical path oscillator each have a propagation delay between when they receive inputs and when they provide an output that are dependent upon the operating voltage; wherein a timing for the first register to read data from the CL block is determined by the oscillator clock signal; and wherein the critical path oscillator estimates a propagation delay of the critical path and generates the oscillator clock signal certain to have a period longer than the delay time of the critical path.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block whose speed depends on the processor's operating voltage. The CL block has CL logic that processes input data signals from a first register and outputs data to a second register. This CL logic contains a critical path whose propagation delay (from input to output to the second register), which is dependent on the operating voltage, defines the minimum allowable clock period for error-free data processing at that operating voltage. The processor also has a critical path oscillator, whose speed also depends on the operating voltage, and whose propagation delay is also dependent on the operating voltage. This oscillator estimates the propagation delay of the critical path and generates an oscillator clock signal that is certain to have a period safely greater than the critical path's delay. This oscillator clock signal clocks both the first and second registers, and determines the timing for the first register to read data from the CL block. It is also sent to a power manager. The power manager includes a bias voltage generator that outputs the processor's operating voltage, dynamically setting it based on the oscillator clock signal and an external time reference signal.
12. The self-timed processor of claim 10 , wherein the critical path has a first set CL logic gates; and wherein the critical path oscillator has a second set of gates that includes the first set of gates and at least one additional gate; or wherein the critical path oscillator has an odd number of inverting gates connected in a ring and has a number of gates that is at least half a number of gates of the critical path.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block whose speed depends on the processor's operating voltage. The CL block has CL logic that processes input data signals from a first register and outputs data to a second register. This CL logic contains a critical path (comprising a first set of CL logic gates) whose propagation delay (from input to output to the second register) defines the minimum allowable clock period for error-free data processing at that operating voltage. The processor also has a critical path oscillator, whose speed also depends on the operating voltage. This oscillator outputs an oscillator clock signal with a period safely greater than the minimum allowable clock period. The critical path oscillator either has a second set of gates that includes all the gates from the critical path's first set plus at least one additional gate; or it has an odd number of inverting gates connected in a ring and its gate count is at least half the number of gates of the critical path. This oscillator clock signal clocks both the first and second registers, and a power manager. The power manager includes a bias voltage generator that outputs the processor's operating voltage, dynamically setting it based on the oscillator clock signal and an external time reference signal.
13. The self-timed processor of claim 10 , wherein the CL logic has digital logic gates and digital registers to process the CL input data signals using CL data process values to create the CL output data signals from the CL data process values.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block whose speed depends on the processor's operating voltage. The CL block has CL logic, comprising digital logic gates and digital registers, that processes input data signals from a first register using specific data process values and outputs data to a second register. This CL logic contains a critical path whose propagation delay (from input to output to the second register) defines the minimum allowable clock period for error-free data processing at that operating voltage. The processor also has a critical path oscillator, whose speed also depends on the operating voltage. This oscillator outputs an oscillator clock signal with a period safely greater than the minimum allowable clock period, which clocks both the first and second registers, and a power manager. The power manager includes a bias voltage generator that outputs the processor's operating voltage, dynamically setting it based on the oscillator clock signal and an external time reference signal.
14. The self-timed processor of claim 10 , wherein the power manager includes circuitry to reduce the operating voltage to a lowest value needed for the critical path to perform data processing of the CL logic at the operating voltage of the processor without a timing error.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block whose speed depends on the processor's operating voltage. The CL block has CL logic that processes input data signals from a first register and outputs data to a second register. This CL logic contains a critical path whose propagation delay (from input to output to the second register) defines the minimum allowable clock period for error-free data processing at that operating voltage. The processor also has a critical path oscillator, whose speed also depends on the operating voltage. This oscillator outputs an oscillator clock signal with a period safely greater than the minimum allowable clock period, which clocks both the first and second registers, and a power manager. The power manager includes a bias voltage generator that outputs the processor's operating voltage, dynamically setting it based on the oscillator clock signal and an external time reference signal. Specifically, the power manager includes circuitry to reduce the operating voltage to the lowest value required for the CL logic's critical path to perform data processing without any timing errors.
15. The self-timed processor of claim 10 , wherein the power manager includes a comparator to compare the oscillator clock signal and the time reference signal to set the operating voltage such that the period of the oscillator clock signal is shorter than a period of the time reference signal.
A self-timed clocked synchronous processor includes a combinatorial logic (CL) block whose speed depends on the processor's operating voltage. The CL block has CL logic that processes input data signals from a first register and outputs data to a second register. This CL logic contains a critical path whose propagation delay (from input to output to the second register) defines the minimum allowable clock period for error-free data processing at that operating voltage. The processor also has a critical path oscillator, whose speed also depends on the operating voltage. This oscillator outputs an oscillator clock signal with a period safely greater than the minimum allowable clock period, which clocks both the first and second registers, and a power manager. The power manager includes a bias voltage generator that outputs the processor's operating voltage, dynamically setting it based on the oscillator clock signal and an external time reference signal. The power manager specifically includes a comparator to compare the oscillator clock signal and the time reference signal, setting the operating voltage so that the oscillator clock signal's period is shorter than the time reference signal's period, making the processor effectively run faster than the reference.
16. A method of processing data within a self-timed clocked synchronous processor comprising: operating a combinatorial logic (CL) block at an operating voltage of the processor to process CL input data signals from a first register using CL data process values and to provide CL output data signals from the CL block to a second register, the CL block having a critical path that operates at the operating voltage with a propagation delay that is a minimum allowable clock period to perform data processing of the CL block of the processor without a timing error; operating a critical path oscillator at the operating voltage of the processor to output an oscillator clock signal with a period that is greater than the minimum allowable clock period to clock the first register, the second register and a power manager; and operating the power manager to output the operating voltage of the processor based on the oscillator clock signal and an external time reference signal.
This method describes how a self-timed processor dynamically adjusts its operating voltage. First, a combinatorial logic (CL) block processes data between registers. Its critical path, the slowest data processing route, has a voltage-dependent propagation delay that defines the minimum safe clock period for error-free operation. Simultaneously, a critical path oscillator, also sensitive to the operating voltage, generates an oscillator clock signal. This signal's period is reliably longer than the critical path's delay, ensuring correct timing, and it clocks the data registers and a power manager. The power manager receives both this oscillator clock signal and an external time reference. By comparing these, the power manager continuously adjusts the processor's operating voltage. It targets the lowest possible voltage that prevents timing errors, setting the voltage so the oscillator clock period is shorter than the external time reference period, thus optimizing power efficiency.
17. The method of claim 16 , wherein the critical path and the critical path oscillator each have a propagation delay between when they receive inputs and when they provide an output that are dependent upon the operating voltage; wherein a timing for the first register to read data from the CL block is determined by the oscillator clock signal; and wherein operating the critical path oscillator generates the oscillator clock signal certain to have a period longer than the delay time of the critical path.
A method of processing data within a self-timed clocked synchronous processor involves: operating a combinatorial logic (CL) block at the processor's operating voltage to process input data signals from a first register and provide output data signals to a second register. This CL block has a critical path whose propagation delay, which is dependent on the operating voltage, establishes the minimum allowable clock period for error-free data processing. The method further involves operating a critical path oscillator, whose propagation delay is also dependent on the operating voltage, to output an oscillator clock signal. This oscillator operation generates a clock signal that is certain to have a period safely greater than the critical path's delay. This oscillator clock signal clocks the first register, the second register, and a power manager, and determines the timing for the first register to read data from the CL block. The method also includes operating the power manager to output the processor's operating voltage, dynamically adjusting it based on the oscillator clock signal and an external time reference signal.
18. The method of claim 16 , wherein the propagation delay of the critical path oscillator is at least a delay of one logic gate more than the propagation delay of the critical path.
A method of processing data within a self-timed clocked synchronous processor involves: operating a combinatorial logic (CL) block at the processor's operating voltage to process input data signals from a first register and provide output data signals to a second register. This CL block has a critical path whose propagation delay at that operating voltage establishes the minimum allowable clock period for error-free data processing. The method further involves operating a critical path oscillator at the same operating voltage to output an oscillator clock signal. The propagation delay of this critical path oscillator is at least the delay of one logic gate more than the propagation delay of the critical path, ensuring its oscillator clock signal has a period safely greater than the minimum allowable clock period. This oscillator clock signal clocks the first register, the second register, and a power manager. The method also includes operating the power manager to output the processor's operating voltage, dynamically adjusting it based on the oscillator clock signal and an external time reference signal.
19. The method of claim 16 , wherein the power manager reduces the operating voltage to a lowest value needed for the critical path to perform data processing of the CL block at the operating voltage of the processor without a timing error.
A method of processing data within a self-timed clocked synchronous processor involves: operating a combinatorial logic (CL) block at the processor's operating voltage to process input data signals from a first register and provide output data signals to a second register. This CL block has a critical path whose propagation delay at that operating voltage establishes the minimum allowable clock period for error-free data processing. The method further involves operating a critical path oscillator at the same operating voltage to output an oscillator clock signal. This oscillator clock signal has a period safely greater than the minimum allowable clock period and is used to clock the first register, the second register, and a power manager. The method also includes operating the power manager to output the processor's operating voltage, dynamically adjusting it based on the oscillator clock signal and an external time reference signal. Specifically, the power manager reduces the operating voltage to the lowest value required for the CL block's critical path to perform data processing without any timing errors.
20. The method of claim 16 , wherein outputting the operating voltage includes comparing the oscillator clock signal and the time reference signal, and setting the operating voltage such that the period of the oscillator clock signal is shorter than a period of the time reference signal.
A method of processing data within a self-timed clocked synchronous processor involves: operating a combinatorial logic (CL) block at the processor's operating voltage to process input data signals from a first register and provide output data signals to a second register. This CL block has a critical path whose propagation delay at that operating voltage establishes the minimum allowable clock period for error-free data processing. The method further involves operating a critical path oscillator at the same operating voltage to output an oscillator clock signal. This oscillator clock signal has a period safely greater than the minimum allowable clock period and is used to clock the first register, the second register, and a power manager. The method also includes operating the power manager to output the processor's operating voltage, dynamically adjusting it based on the oscillator clock signal and an external time reference signal. This adjustment specifically involves comparing the oscillator clock signal and the time reference signal, then setting the operating voltage such that the period of the oscillator clock signal is shorter than the period of the time reference signal, making the processor effectively run faster than the reference.
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August 4, 2020
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