Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A physical unclonable function (PUF) generator comprising: a PUF cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells is configurable into at least two different stable states; a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to: access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells; and a reset circuit coupled to the PUF cell array, wherein the reset circuit is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the PUF cell array.
A physical unclonable function (PUF) generator is described, designed to create unique digital signatures from physical variations in silicon. It comprises a PUF cell array, which consists of multiple bit cells, each capable of settling into at least two different stable states. A PUF control circuit is connected to this array; its role is to access each bit cell upon power-up to determine its stable state, then generate a PUF signature based on these determined states. Crucially, a reset circuit is also coupled to the PUF cell array. This reset circuit is configured to restore all bit cells to their predetermined initialization data if it detects a voltage tempering event affecting the array's supply voltage, thereby protecting the PUF from manipulation.
2. The PUF generator of claim 1 , wherein the initialization data of the plurality of bit cells are predetermined based on their initial logical states before the PUF cell array stores any user data and the initial logical states of the plurality of bit cells are equal to all logic 0s or all logic 1s.
This invention describes a physical unclonable function (PUF) generator. This generator includes a PUF cell array with bit cells that settle into stable states, a PUF control circuit that reads these states on power-up to generate a PUF signature, and a reset circuit. The reset circuit is designed to set all bit cells back to specific initialization data if a voltage tempering event is detected on the array's supply voltage. Specifically, this initialization data for the bit cells is predetermined based on their initial logical states. These initial logical states exist before any user data is stored in the PUF cell array, and they are uniformly set to either all logic 0s or all logic 1s across the array.
3. The PUF generator of claim 1 , wherein the voltage tempering event happens when there is a voltage droop or glitch of the supply voltage of the PUF cell array.
This invention describes a physical unclonable function (PUF) generator. This generator includes a PUF cell array with bit cells that settle into stable states, a PUF control circuit that reads these states on power-up to generate a PUF signature, and a reset circuit. The reset circuit is designed to set all bit cells back to specific initialization data if an indication of a voltage tempering event is received, protecting the array's supply voltage from manipulation. A voltage tempering event, in this context, specifically refers to an occurrence where there is a voltage droop (a dip) or a voltage glitch (a sudden, temporary spike or dip) in the supply voltage of the PUF cell array.
4. The PUF generator of claim 1 , further comprising a voltage tempering detector that is configured to: detect the voltage tempering event of the supply voltage of the PUF cell array; and send the indication to the reset circuit upon the detection.
This invention describes a physical unclonable function (PUF) generator designed to create unique digital signatures. It includes a PUF cell array of bit cells configurable into stable states, a PUF control circuit to generate a signature from these cells' power-up states, and a reset circuit. The reset circuit sets bit cells to initialization data upon indication of a voltage tempering event on the array's supply voltage. To facilitate this protection, the PUF generator further comprises a dedicated voltage tempering detector. This detector is specifically configured to actively detect any voltage tempering event of the PUF cell array's supply voltage and, upon such detection, send the necessary indication directly to the reset circuit, triggering the protective reset action.
5. The PUF generator of claim 1 , wherein: each column of the PUF cell array includes a bit line and a bit bar line; each bit line is electrically connected to a drain end of a first transistor, wherein a source end of the first transistor is electrically connected to a system ground, and wherein a gate end of the first transistor is controlled by a clear signal generated by the reset circuit based on the indication of the voltage tempering event; and each bit bar line is electrically connected to a drain end of a second transistor, wherein a source end of the second transistor is electrically connected to a logic high voltage, and wherein a gate end of the second transistor is controlled by a clear bar signal that is a reverse of the clear signal.
This invention describes a physical unclonable function (PUF) generator. It comprises a PUF cell array of bit cells configurable into stable states, a PUF control circuit to generate a PUF signature from these states on power-up, and a reset circuit. The reset circuit sets the bit cells to initialization data upon indication of a voltage tempering event of the array's supply voltage. Delving into the physical structure, each column within the PUF cell array includes a bit line and a bit bar line. Each bit line is electrically connected to the drain of a first transistor, whose source is connected to system ground, and its gate is controlled by a "clear signal" generated by the reset circuit based on the voltage tempering indication. Similarly, each bit bar line is connected to the drain of a second transistor, whose source is connected to a logic high voltage, and its gate is controlled by a "clear bar signal," which is the inverse of the clear signal.
6. The PUF generator of claim 1 , wherein: the clear signal triggers the first transistor to lock the bit line to its initial logical state; and the clear bar signal triggers the second transistor to lock the bit bar line to its initial logical state.
This invention describes a physical unclonable function (PUF) generator that includes a PUF cell array, a PUF control circuit for generating a signature from the array's power-up states, and a reset circuit that sets bit cells to initialization data if a voltage tempering event is detected. Specifically, the PUF cell array features columns with a bit line and a bit bar line, each connected to a transistor. A first transistor connected to the bit line is controlled by a "clear signal," and a second transistor connected to the bit bar line is controlled by a "clear bar signal" (the reverse of the clear signal). The invention specifies that the clear signal triggers the first transistor, which in turn locks the associated bit line to its predetermined initial logical state. Concurrently, the clear bar signal triggers the second transistor, which locks the associated bit bar line to its predetermined initial logical state, ensuring a consistent reset response.
7. The PUF generator of claim 5 , wherein the reset circuit is further configured to determine a voltage droop based on the indication; compare the voltage droop with a predetermined threshold; generate the clear signal and the clear bar signal in response to the voltage droop being larger than the predetermined threshold; use the clear signal to lock a logic 0 on each bit line; and use the clear bar signal to lock a logic 1 on each bit bar line.
This invention describes a physical unclonable function (PUF) generator with a PUF cell array, a PUF control circuit for signature generation, and a reset circuit that sets bit cells to initialization data upon detecting a voltage tempering event. The PUF cell array columns utilize bit lines and bit bar lines connected to first and second transistors, respectively, controlled by "clear" and "clear bar" signals from the reset circuit. Expanding on the reset circuit's function, it is configured to actively determine the extent of a voltage droop based on the voltage tempering indication. This determined voltage droop is then compared against a predetermined threshold. If the voltage droop is found to be larger than this threshold, the reset circuit generates both the clear signal and the clear bar signal. Subsequently, the clear signal is used to lock a logic 0 onto each bit line, while the clear bar signal is used to lock a logic 1 onto each bit bar line, thereby enforcing the reset.
8. The PUF generator of claim 5 , further comprising a row decoder coupled to all word lines of the PUF cell array, wherein the row decoder is configured to: receive a row address of the PUF cell array; assert a word line at the row address; receive the clear bar signal generated by the reset circuit; and lock each word line to a logic 1 based on the clear bar signal.
This invention describes a physical unclonable function (PUF) generator with a PUF cell array, a PUF control circuit for signature generation, and a reset circuit that sets bit cells to initialization data upon detecting a voltage tempering event. The PUF cell array columns utilize bit lines and bit bar lines connected to first and second transistors, respectively, controlled by "clear" and "clear bar" signals from the reset circuit. The generator further includes a row decoder. This row decoder is coupled to all word lines of the PUF cell array and is configured to receive a row address for the array, assert the word line corresponding to that address, receive the clear bar signal generated by the reset circuit, and then use this clear bar signal to lock each word line to a logic 1 state, providing an additional layer of reset control during tempering events.
9. The PUF generator of claim 8 , wherein the row decoder comprises: a plurality of inverters each having an output connected to a corresponding word line of the PUF cell array; a plurality of AND gates each having an output connected to an input of one of the plurality of inverters; and a plurality of NAND gates each having an output connected to a first input of one of the plurality of AND gates, wherein a second input of each of the plurality of AND gates receives the clear bar signal.
This invention describes a physical unclonable function (PUF) generator that includes a PUF cell array, a PUF control circuit for signature generation, and a reset circuit that sets bit cells to initialization data upon detecting a voltage tempering event. The PUF cell array columns utilize bit lines and bit bar lines connected to transistors controlled by "clear" and "clear bar" signals. A row decoder, coupled to the array's word lines, receives row addresses, asserts word lines, and receives the clear bar signal to lock each word line to a logic 1. Specifically, this row decoder comprises a plurality of inverters, each with an output connected to a corresponding word line of the PUF cell array. It also includes a plurality of AND gates, each with an output connected to an input of one of these inverters. Furthermore, a plurality of NAND gates are present, each with an output connected to a first input of one of the AND gates. Crucially, a second input of each of these AND gates receives the clear bar signal, integrating it into the word line control logic to enforce the logic 1 lock.
10. The PUF generator of claim 1 , wherein the PUF cell array is a memory cell array configured for storing user data.
This invention describes a physical unclonable function (PUF) generator designed to create unique digital signatures from physical variations in silicon. It comprises a PUF cell array, which consists of multiple bit cells, each capable of settling into at least two different stable states. A PUF control circuit is connected to this array; its role is to access each bit cell upon power-up to determine its stable state, then generate a PUF signature based on these determined states. A reset circuit is also coupled to the PUF cell array, configured to restore all bit cells to their predetermined initialization data if it detects a voltage tempering event affecting the array's supply voltage. In this specific embodiment, the PUF cell array is additionally configured as a memory cell array, capable of storing user data alongside its PUF functionality.
11. The PUF generator of claim 1 , wherein the reset circuit is configured to set the plurality of bit cells to their initial logical states simultaneously.
This invention describes a physical unclonable function (PUF) generator designed to create unique digital signatures. It comprises a PUF cell array of bit cells configurable into stable states, a PUF control circuit to generate a PUF signature from these states on power-up, and a reset circuit. The reset circuit is configured to restore all bit cells to their predetermined initialization data if it detects a voltage tempering event affecting the array's supply voltage, thereby protecting the PUF from manipulation. A key feature of this reset circuit's operation is that it sets the plurality of bit cells to their initial logical states simultaneously, ensuring a rapid and uniform reset across the entire array in response to a tempering event.
12. The PUF generator of claim 1 , wherein the reset circuit comprises a finite state machine (FSM) that resets bit cells of each row to their initial logical states, one row at a time.
This invention describes a physical unclonable function (PUF) generator designed to create unique digital signatures. It comprises a PUF cell array of bit cells configurable into stable states, a PUF control circuit to generate a PUF signature from these states on power-up, and a reset circuit. The reset circuit is configured to restore all bit cells to their predetermined initialization data if it detects a voltage tempering event affecting the array's supply voltage, thereby protecting the PUF from manipulation. In this specific implementation, the reset circuit comprises a finite state machine (FSM) that manages the resetting process by resetting bit cells of each row to their initial logical states sequentially, one row at a time.
13. A memory device, comprising: a memory cell array that comprises a plurality of bit cells, wherein each of the plurality of bit cells is configurable into at least two different stable states; a physical unclonable function (PUF) control circuit coupled to the memory cell array, wherein the PUF control circuit is configured to: access each of the plurality of bit cells to determine one of the at least two different stable states upon a power-up of the plurality of bit cells, and generate a PUF signature based on the determined stable states of the plurality of bit cells; and a reset circuit coupled to the memory cell array, wherein the reset circuit is configured to set the plurality of bit cells to represent their initialization data based on an indication of a voltage tempering event of a supply voltage of the memory cell array.
A memory device is described, incorporating physical unclonable function (PUF) protection. It comprises a memory cell array with multiple bit cells, each capable of settling into at least two different stable states. A PUF control circuit is coupled to this memory cell array and is configured to access each bit cell upon power-up to determine one of its stable states, subsequently generating a PUF signature based on these determined states. Furthermore, a reset circuit is coupled to the memory cell array. This reset circuit is designed to set all the bit cells to represent their predetermined initialization data based on an indication of a voltage tempering event affecting the supply voltage of the memory cell array, providing security against external attacks.
14. The memory device of claim 13 , wherein the initialization data of the plurality of bit cells are predetermined based on their initial logical states before the memory cell array stores any user data and the initial logical states of the plurality of bit cells are equal to all logic 0s or all logic 1s.
This invention describes a memory device that incorporates physical unclonable function (PUF) protection. It includes a memory cell array with bit cells that settle into stable states, a PUF control circuit that reads these states on power-up to generate a PUF signature, and a reset circuit. The reset circuit is designed to set all bit cells back to specific initialization data if a voltage tempering event is detected on the array's supply voltage. Specifically, this initialization data for the bit cells is predetermined based on their initial logical states. These initial logical states exist before the memory cell array stores any user data, and they are uniformly set to either all logic 0s or all logic 1s across the array.
15. The memory device of claim 13 , wherein: each column of the memory cell array includes a bit line and a bit bar line; each bit line is electrically connected to a drain end of a first transistor, wherein a source end of the first transistor is electrically connected to a system ground, a gate end of the first transistor is controlled by a clear signal generated by the reset circuit based on the indication of the voltage tempering event, and the clear signal triggers the first transistor to lock the bit line to its initial logical state; and each bit bar line is electrically connected to a drain end of a second transistor, wherein a source end of the second transistor is electrically connected to a logic high voltage, a gate end of the second transistor is controlled by a clear bar signal that is a reverse of the clear signal, and the clear bar signal triggers the second transistor to lock the bit bar line to its initial logical state.
This invention describes a memory device incorporating physical unclonable function (PUF) protection. It comprises a memory cell array, a PUF control circuit to generate a PUF signature from the array's power-up states, and a reset circuit that sets bit cells to initialization data upon detecting a voltage tempering event of the array's supply voltage. Delving into the physical structure, each column within the memory cell array includes a bit line and a bit bar line. Each bit line is electrically connected to the drain of a first transistor, whose source is connected to system ground, and its gate is controlled by a "clear signal" generated by the reset circuit based on the voltage tempering indication. This clear signal triggers the first transistor to lock the bit line to its predetermined initial logical state. Similarly, each bit bar line is connected to the drain of a second transistor, whose source is connected to a logic high voltage, and its gate is controlled by a "clear bar signal" (the reverse of the clear signal). This clear bar signal triggers the second transistor to lock the bit bar line to its predetermined initial logical state, ensuring a consistent reset response.
16. The memory device of claim 13 , wherein the reset circuit is further configured to determine a voltage droop based on the indication; compare the voltage droop with a predetermined threshold; generate the clear signal and the clear bar signal in response to the voltage droop being larger than the predetermined threshold; use the clear signal to lock a logic 0 on each bit line; and use the clear bar signal to lock a logic 1 on each bit bar line.
This invention describes a memory device incorporating physical unclonable function (PUF) protection. It comprises a memory cell array with bit cells, a PUF control circuit for signature generation, and a reset circuit that sets bit cells to initialization data upon detecting a voltage tempering event of the array's supply voltage. Expanding on the reset circuit's function, it is configured to actively determine the extent of a voltage droop based on the voltage tempering indication. This determined voltage droop is then compared against a predetermined threshold. If the voltage droop is found to be larger than this threshold, the reset circuit generates both a clear signal and a clear bar signal. Subsequently, the clear signal is used to lock a logic 0 onto each bit line of the memory cell array, while the clear bar signal is used to lock a logic 1 onto each bit bar line, thereby enforcing the reset to a known state.
17. The memory device of claim 13 , further comprising a row decoder coupled to all word lines of the memory cell array, wherein the row decoder comprises: a plurality of inverters each having an output connected to a corresponding word line of the memory cell array; a plurality of AND gates each having an output connected to an input of one of the plurality of inverters; and a plurality of NAND gates each having an output connected to a first input of one of the plurality of AND gates, wherein a second input of each of the plurality of AND gates receives the clear bar signal to lock each word line to a logic 1 based on the clear bar signal.
This invention describes a memory device incorporating physical unclonable function (PUF) protection. It comprises a memory cell array with bit cells, a PUF control circuit for signature generation, and a reset circuit that sets bit cells to initialization data upon detecting a voltage tempering event of the array's supply voltage. The device further includes a row decoder coupled to all word lines of the memory cell array. This row decoder comprises a plurality of inverters, each having an output connected to a corresponding word line. It also includes a plurality of AND gates, each with an output connected to an input of one of the inverters. Additionally, a plurality of NAND gates are present, each with an output connected to a first input of one of the AND gates. Crucially, a second input of each of these AND gates receives the clear bar signal, allowing it to lock each word line to a logic 1 based on the clear bar signal, reinforcing the reset state.
18. A method for protecting a physical unclonable function (PUF) generator from attack, the method comprising: monitoring voltage changes of a supply voltage of a memory cell array, wherein the memory cell array comprises a plurality of bit cells whose stable logical states upon a power-up of the memory cell array are used to generate a PUF signature; detecting a voltage tempering event of the supply voltage based on the monitoring; generating a clear signal based on the voltage tempering event; and setting each of the plurality of bit cells to its initial logical state based on the clear signal.
A method is described for protecting a physical unclonable function (PUF) generator from attack. The method involves continuously monitoring voltage changes of a supply voltage feeding a memory cell array, where this array's bit cells determine stable logical states upon power-up, which are then used to generate a PUF signature. The next step is detecting a specific voltage tempering event in the supply voltage based on the ongoing monitoring. Upon detection, a clear signal is generated in response to the voltage tempering event. Finally, based on this generated clear signal, each of the plurality of bit cells within the memory cell array is set to its predetermined initial logical state, effectively safeguarding the PUF integrity against voltage manipulation.
19. The method of claim 18 , further comprising generating a clear bar signal that is a reverse of the clear signal based on the clear signal, wherein the setting comprises: locking a logic 0 on each bit line of the memory cell array based on the clear signal; and locking a logic 1 on each bit bar line of the memory cell array based on the clear bar signal.
A method is described for protecting a physical unclonable function (PUF) generator from attack. This method involves monitoring voltage changes of a memory cell array's supply voltage (whose power-up stable states generate a PUF signature), detecting a voltage tempering event, generating a clear signal based on the event, and setting each bit cell to its initial logical state based on the clear signal. The method further comprises generating a clear bar signal, which is the exact reverse of the clear signal. The setting of bit cells to their initial logical states then specifically includes two actions: locking a logic 0 onto each bit line of the memory cell array using the clear signal, and simultaneously locking a logic 1 onto each bit bar line of the memory cell array using the clear bar signal, ensuring a robust and complementary reset.
20. The method of claim 18 , wherein bit cells of each row of the memory cell array are set to their initial logical states, one row at a time.
A method is described for protecting a physical unclonable function (PUF) generator from attack. This method involves monitoring voltage changes of a memory cell array's supply voltage (whose power-up stable states generate a PUF signature), detecting a voltage tempering event, generating a clear signal based on the event, and setting each bit cell to its initial logical state based on the clear signal. In this particular method, the process of setting the plurality of bit cells to their initial logical states is performed by resetting bit cells of each row of the memory cell array sequentially, one row at a time.
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August 4, 2020
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