Legal claims defining the scope of protection. Each claim is shown in both the original legal language and a plain English translation.
1. A transmitter of a filter bank multicarrier communication system based on a discrete Hartley transform (DHT), said transmitter comprising: a serial-to-parallel conversion unit configured to perform serial-to-parallel conversion on M complex input data symbols, which are inputted thereto in series and each of which includes a real part and an imaginary part, and to output M real parts and M imaginary parts of the complex input data symbols in parallel, where M is a positive even integer; a first pre-processing unit coupled to the serial-to-parallel conversion unit for receiving the M real parts of the complex input data symbols, and configured to generate M pre-processed real-part components based on a pre-processing model and the M real parts of the complex input data symbols; a second pre-processing unit coupled to the serial-to-parallel conversion unit for receiving the M imaginary parts of the complex input data symbols, and configured to generate M pre-processed imaginary-part components based on the pre-processing model and the M imaginary parts of the complex input data symbols; a first data separator coupled to the first pre-processing unit for receiving the M pre-processed real-part components, and configured to separate the M pre-processed real-part components into M/2 even-numbered pre-processed real-part components and M/2 odd-numbered pre-processed real-part components; a second data separator coupled to the second pre-processing unit for receiving the M pre-processed imaginary-part components, and configured to separate the M pre-processed imaginary-part components into M/2 even-numbered pre-processed imaginary-part components and M/2 odd-numbered pre-processed imaginary-part components; a first synthesis filter bank coupled to the first data separator for receiving the M/2 even-numbered pre-processed real-part components and the M/2 odd-numbered pre-processed real-part components, and configured to generate a first-channel transmitted (Tx) baseband signal of M points by performing at least up-sampling, filtering, inverse discrete Hartley transform (IDHT), data combination, and parallel-to-serial conversion on pre-processed real-part components, the pre-processed real-part components consisting of the M/2 even-numbered pre-processed real-part components and the M/2 odd-numbered pre-processed real-part components; and a second synthesis filter bank coupled to the second data separator for receiving the M/2 even-numbered pre-processed imaginary-part components and the M/2 odd-numbered pre-processed imaginary-part components, and configured to generate a second-channel Tx baseband signal of M points by performing at least up-sampling, filtering, IDHT, data combination, and parallel-to-serial conversion on pre-processed imaginary-part components, the pre-processed imaginary-part components consisting of the M/2 even-numbered pre-processed imaginary-part components and the M/2 odd-numbered pre-processed imaginary-part components.
A transmitter for a Discrete Hartley Transform (DHT)-based filter bank multicarrier communication system. This transmitter processes M complex input data symbols (each with real and imaginary parts, M is a positive even integer) received serially. It includes a serial-to-parallel conversion unit that outputs M real and M imaginary parts in parallel. A first pre-processing unit generates M pre-processed real-part components, while a second unit generates M pre-processed imaginary-part components. These are then separated into M/2 even-numbered and M/2 odd-numbered components by first and second data separators. Finally, a first synthesis filter bank generates a first-channel transmitted baseband signal (M points) from the real-part components, and a second synthesis filter bank generates a second-channel transmitted baseband signal (M points) from the imaginary-part components. Both filter banks perform up-sampling, filtering, Inverse Discrete Hartley Transform (IDHT), data combination, and parallel-to-serial conversion.
2. The transmitter of claim 1 , wherein the first synthesis filter bank includes: M/2 first up-sampling modules coupled to the first data separator for respectively receiving the M/2 even-numbered pre-processed real-part components, wherein each of the first up-sampling modules is configured to perform up-sampling on the respective one of the M/2 even-numbered pre-processed real-part components; M/2 second up-sampling modules coupled to the first data separator for respectively receiving the M/2 odd-numbered pre-processed real-part components, wherein each of the second up-sampling modules is configured to perform up-sampling on the respective one of the M/2 odd-numbered pre-processed real-part components; M/2 first prototype filters respectively coupled to the M/2 first up-sampling modules for respectively receiving the M/2 even-numbered pre-processed real-part components that have been up-sampled by the M/2 first up-sampling modules, wherein each of the first prototype filters is configured to perform filtering on the respective one of the M/2 even-numbered pre-processed real-part components that has been up-sampled; M/2 second prototype filters respectively coupled to the M/2 second up-sampling modules for respectively receiving the M/2 odd-numbered pre-processed real-part components that have been up-sampled by the M/2 second up-sampling modules, wherein each of the second prototype filters is configured to perform filtering on the respective one of the M/2 odd-numbered pre-processed real-part components that has been up-sampled; a first IDHT module coupled to the M/2 first prototype filters for receiving the M/2 even-numbered pre-processed real-part components that have been up-sampled by the first up-sampling modules and filtered by the first prototype filters, and configured to generate a first part of the first-channel Tx baseband signal by performing M/2-point IDHTs on two sets of the M/2 even-numbered pre-processed real-part components that have been up-sampled and filtered and that are received consecutively by the first IDHT module; a second IDHT module coupled to the M/2 second prototype filters for receiving the M/2 odd-numbered pre-processed real-part components that have been up-sampled by the second up-sampling modules and filtered by the second prototype filters, and configured to consecutively generate two serial second-IDHT results of M/2 points, where the M/2 points of each of the serial second-IDHT results are outputted in series, by performing M/2-point IDHTs on two sets of the M/2 odd-numbered pre-processed real-part components that have been up-sampled and filtered and that are received consecutively by the second IDHT module; a first serial-to-parallel conversion module coupled to the second IDHT module for receiving the two serial second-IDHT results of M/2 points, and configured to consecutively output two parallel second-IDHT results of M/2 points, where the M/2 points of each of the parallel second-IDHT results are outputted in parallel, by performing serial-to-parallel conversion on each of the two serial second-IDHT results of M/2 points; and a first data combination and parallel-to-serial conversion module coupled to the first serial-to-parallel conversion module for receiving the two parallel second-IDHT results of M/2 points, and configured to generate a second part of the first-channel Tx baseband signal by, for each of the two parallel second-IDHT results of M/2 points, performing data combination on the parallel second-IDHT result of M/2 points to obtain a data combination result, and performing parallel-to-serial conversion on the data combination result for the parallel second-IDHT result of M/2 points; and wherein the second synthesis filter bank includes: M/2 third up-sampling modules coupled to the second data separator for respectively receiving the M/2 even-numbered pre-processed imaginary-part components, wherein each of the third up-sampling modules is configured to perform up-sampling on the respective one of the M/2 even-numbered pre-processed imaginary-part components received thereby; M/2 fourth up-sampling modules coupled to the second data separator for respectively receiving the M/2 odd-numbered pre-processed imaginary-part components, wherein each of the fourth up-sampling modules is configured to perform up-sampling on the respective one of the M/2 odd-numbered pre-processed imaginary-part components received thereby; M/2 third prototype filters respectively coupled to the M/2 third up-sampling modules for respectively receiving the M/2 even-numbered pre-processed imaginary-part components that have been up-sampled by the M/2 third up-sampling modules, wherein each of the third prototype filters is configured to perform filtering on the respective one of the M/2 even-numbered pre-processed imaginary-part components received thereby; M/2 fourth prototype filters respectively coupled to the M/2 fourth up-sampling modules for respectively receiving the M/2 odd-numbered pre-processed imaginary-part components that have been up-sampled by the M/2 fourth up-sampling modules, wherein each of the fourth prototype filters is configured to perform filtering on the respective one of the M/2 odd-numbered pre-processed imaginary-part components received thereby; a third IDHT module coupled to the M/2 third prototype filters for receiving the M/2 even-numbered pre-processed imaginary-part components that have been up-sampled by the third up-sampling modules and filtered by the third prototype filters, and configured to generate a first part of the second-channel Tx baseband signal by performing M/2-point IDHTs on two sets of the M/2 even-numbered pre-processed imaginary-part components that have been up-sampled and filtered and that are received consecutively by the third IDHT module; a fourth IDHT module coupled to the M/2 fourth prototype filters for receiving the M/2 odd-numbered pre-processed imaginary-part components that have been up-sampled by the fourth up-sampling modules and filtered by the fourth prototype filters, and configured to consecutively output two serial fourth-IDHT results of M/2 points, where the M/2 points of each of the serial fourth-IDHT results are outputted in series, by performing M/2-point IDHTs on two sets of the M/2 odd-numbered pre-processed imaginary-part components that have been up-sampled and filtered and that are received consecutively by the fourth IDHT module; a second serial-to-parallel conversion module coupled to the fourth IDHT module for receiving the two serial fourth-IDHT results of M/2 points, and configured to perform serial-to-parallel conversion on each of the two serial fourth-IDHT results of M/2 points, and to consecutively output two parallel fourth-IDHT results of M/2 points, wherein for each of the two parallel fourth-IDHT results of M/2 points, the M/2 points of the parallel fourth-IDHT result are outputted in parallel; and a second data combination and parallel-to-serial conversion module coupled to the second serial-to-parallel conversion module for receiving the two parallel fourth-IDHT results of M/2 points, and configured to generate a second part of the second-channel Tx baseband signal by, for each of the two parallel fourth-IDHT results of M/2 points, performing data combination on the parallel fourth-IDHT result of M/2 points to obtain a data combination result, and performing parallel-to-serial conversion on the data combination result for the parallel fourth-IDHT result of M/2 points.
A transmitter for a Discrete Hartley Transform (DHT)-based multicarrier communication system processes M complex input data symbols (M is a positive even integer). It uses serial-to-parallel conversion, separate pre-processing for real and imaginary parts, and separates these into M/2 even and odd components. The first synthesis filter bank (for real-part components) includes M/2 up-sampling modules and M/2 prototype filters for both even and odd components. A first IDHT module performs M/2-point IDHTs on consecutive up-sampled/filtered even components, forming a first part of the first-channel baseband signal. A second IDHT module similarly processes odd components, outputting serial results. These results undergo serial-to-parallel conversion and then data combination with parallel-to-serial conversion to produce a second part of the first-channel baseband signal. The second synthesis filter bank (for imaginary-part components) mirrors this structure, using M/2 up-sampling modules, M/2 prototype filters, and third/fourth IDHT modules. A third IDHT module generates a first part of the second-channel baseband signal from even imaginary components. A fourth IDHT module processes odd imaginary components, with its serial output undergoing serial-to-parallel conversion, then data combination and parallel-to-serial conversion, to form a second part of the second-channel baseband signal.
4. The transmitter of claim 1 , wherein the first synthesis filter bank includes: a first IDHT module coupled to the first data separator for receiving the M/2 even-numbered pre-processed real-part components, and configured to generate a first-IDHT result of M/2 points by performing an M/2-point IDHT on the M/2 even-numbered pre-processed real-part components; a second IDHT module coupled to the first data separator for receiving the M/2 odd-numbered pre-processed real-part components, and configured to generate a second-IDHT result of M/2 points by performing an M/2-point IDHT on the M/2 odd-numbered pre-processed real-part components; a first data combination module coupled to the second IDHT module for receiving the second-IDHT result of M/2 points, and configured to perform data combination on the second-IDHT result of M/2 points; M/2 different first polyphase filters each coupled to the first IDHT module for receiving a respective one of the M/2 points of the first-IDHT result, the first polyphase filters being configured to respectively generate M/2 first filtered outputs, wherein each of the first polyphase filters generates the respective one of the first filtered outputs by sequentially performing up-sampling and filtering on the respective one of the M/2 points of the first-IDHT result received thereby; M/2 different second polyphase filters each coupled to the first data combination module for receiving a respective one of the M/2 points of the second-IDHT result on which the data combination has been performed, the second polyphase filters being configured to respectively generate M/2 second filtered outputs, wherein each of the second polyphase filters generates the respective one of the second filtered outputs by sequentially performing up-sampling and filtering on the respective one of the M/2 points of the second-IDHT result received thereby; a first parallel-to-serial conversion module coupled to the M/2 first polyphase filters for receiving the M/2 first filtered outputs, and configured to generate a first part of the first-channel Tx baseband signal by sequentially performing up-sampling and parallel-to-serial conversion on the M/2 first filtered outputs; and a second parallel-to-serial conversion module coupled to the M/2 second polyphase filters for receiving the M/2 second filtered outputs, and configured to generate a second part of the first-channel Tx baseband signal by sequentially performing up-sampling and parallel-to-serial conversion on the M/2 second filtered outputs; and wherein the second synthesis filter bank includes: a third IDHT module coupled to the second data separator for receiving the M/2 even-numbered pre-processed imaginary-part components, and configured to generate a third-IDHT result of M/2 points by performing an M/2-point IDHT on the M/2 even-numbered pre-processed imaginary-part components; a fourth IDHT module coupled to the second data separator for receiving the M/2 odd-numbered pre-processed imaginary-part components, and configured to generate a fourth-IDHT result of M/2 points by performing an M/2-point IDHT on the M/2 odd-numbered pre-processed imaginary-part components; a second data combination module coupled to the fourth IDHT module for receiving the fourth-IDHT result of M/2 points, and configured to perform data combination on the fourth-IDHT result of M/2 points; M/2 different third polyphase filters each coupled to the third IDHT module for receiving a respective one of the M/2 points of the third-IDHT result, the third polyphase filters being configured to respectively generate M/2 third filtered outputs, wherein each of the third polyphase filters generates the respective one of the third filtered outputs by sequentially performing up-sampling and filtering on the respective one of the M/2 points of the third-IDHT result received thereby; M/2 different fourth polyphase filters each coupled to the second data combination module for receiving a respective one of the M/2 points of the fourth-IDHT result on which the data combination has been performed, the fourth polyphase filters being configured to respectively generate M/2 fourth filtered outputs, wherein each of the fourth polyphase filters generates the respective one of the fourth filtered outputs by sequentially performing up-sampling and filtering on the respective one of the M/2 points of the fourth-IDHT result received thereby; a third parallel-to-serial conversion module coupled to the M/2 third polyphase filters for receiving the M/2 third filtered outputs, and configured to generate a first part of the second-channel Tx baseband signal by sequentially performing up-sampling and parallel-to-serial conversion on the M/2 third filtered outputs; and a fourth parallel-to-serial conversion module coupled to the M/2 fourth polyphase filters for receiving the M/2 fourth filtered outputs, and configured to generate a second part of the second-channel Tx baseband signal by sequentially performing up-sampling and parallel-to-serial conversion on the M/2 fourth filtered outputs.
A transmitter for a Discrete Hartley Transform (DHT)-based multicarrier communication system processes M complex input data symbols (M is a positive even integer). It employs serial-to-parallel conversion, pre-processing for real and imaginary parts, and separation into M/2 even and odd components. The first synthesis filter bank (for real-part components) includes: A first IDHT module performs M/2-point IDHT on even-numbered real components. A second IDHT module performs M/2-point IDHT on odd-numbered real components, with its result undergoing data combination. M/2 first polyphase filters each up-sample and filter individual points from the first IDHT result. M/2 second polyphase filters similarly up-sample and filter individual points from the combined second IDHT result. Two parallel-to-serial conversion modules then process these respective filtered outputs, generating parts of the first-channel transmitted baseband signal. The second synthesis filter bank (for imaginary-part components) mirrors this structure: A third IDHT module performs M/2-point IDHT on even-numbered imaginary components. A fourth IDHT module performs M/2-point IDHT on odd-numbered imaginary components, followed by data combination. M/2 third polyphase filters up-sample and filter points from the third IDHT result. M/2 fourth polyphase filters up-sample and filter points from the combined fourth IDHT result. Two additional parallel-to-serial conversion modules then process these respective filtered outputs, generating parts of the second-channel transmitted baseband signal.
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August 4, 2020
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